 mrg
|
537e862d48
|
Add -full to LVS script
|
2020-11-10 20:38:41 -08:00 |
|
|
mrg
|
03dad01e4c
|
Use readspice to define ports from sp netlist in Magic extract.
|
2020-11-10 17:06:24 -08:00 |
|
|
mrg
|
56c2222c2b
|
Temp comment Magic GDS filter code.
|
2020-11-10 13:37:18 -08:00 |
|
|
mrg
|
0ba2feee53
|
Fix errors in new run_sim calls and corners
|
2020-11-09 13:59:46 -08:00 |
|
|
mrg
|
10542d6cc3
|
Output DRC and LVS run files to output directory.
|
2020-11-09 11:12:31 -08:00 |
|
|
mrg
|
a52aac5f31
|
Add gds flatten option for Magic
|
2020-11-05 13:12:08 -08:00 |
|
|
mrg
|
9a38f7a5f4
|
Enable gds readonly in Magic DRC/LVS
|
2020-11-04 10:50:53 -08:00 |
|
|
mrg
|
45cdecdea9
|
Improve error message about missing DRC/LVS tools.
|
2020-11-03 15:47:04 -08:00 |
|
|
mrg
|
da721a677d
|
Remove EOL whitespace globally
|
2020-11-03 06:29:17 -08:00 |
|
|
mrg
|
1e24b780bb
|
Initial pex sram test.
|
2020-10-02 13:32:52 -07:00 |
|
|
mrg
|
b32c123dab
|
PEP8 cleanup. Un-hard-code bitcell layers. Remove dead variable.
|
2020-10-01 11:10:18 -07:00 |
|
|
mrg
|
11f2b6b809
|
Do not do final verification if supplies were not routed
|
2020-09-15 13:39:00 -07:00 |
|
|
mrg
|
652f160aca
|
Merge branch 'wlbuffer' into dev
|
2020-08-25 15:50:08 -07:00 |
|
|
mrg
|
856cce1e62
|
Add -json for detailed LVS output
|
2020-08-25 13:58:28 -07:00 |
|
 jcirimel
|
9cecf367ee
|
Merge branch 'dev' into pex
|
2020-08-17 17:49:41 -07:00 |
|
|
mrg
|
2c43d315db
|
Revert gds readonly true
|
2020-08-17 12:19:23 -07:00 |
|
|
mrg
|
604e433e22
|
Add readonly true for Magic scripts
|
2020-08-14 10:40:31 -07:00 |
|
|
jcirimel
|
38648027d0
|
fix pinv unit test
|
2020-08-04 04:40:20 -07:00 |
|
|
jcirimel
|
02e65a00ef
|
update pex to work with dev changes
|
2020-08-03 17:14:34 -07:00 |
|
 Bob Vanhoof
|
487bb6c6e9
|
Merge branch 'dev' of github:VLSIDA/OpenRAM into CalibrePexFilesUpdate
|
2020-08-03 09:32:27 +02:00 |
|
|
Bob Vanhoof
|
dc55ededc1
|
fix regession tests after calibre fix
|
2020-07-31 12:51:34 +02:00 |
|
|
mrg
|
487027a9f2
|
Fix pex file names
|
2020-07-30 11:35:13 -07:00 |
|
|
mrg
|
8fa0065aaf
|
Undo PR 82 changes -- broke unit test.
|
2020-07-30 11:09:19 -07:00 |
|
|
Matt Guthaus
|
68387ec525
|
Merge pull request #84 from bvhoof/CalibrePexFilesUpdate
calibrepex: file copy fix
|
2020-07-30 08:40:35 -07:00 |
|
|
jcirimel
|
1d9296ceb1
|
fix magic.py conflict
|
2020-07-21 11:50:25 -07:00 |
|
|
jcirimel
|
df4a231c04
|
fix merge conflicts
|
2020-07-21 11:38:34 -07:00 |
|
|
Bob Vanhoof
|
ee3da91232
|
calibrepex: file copy fix
|
2020-07-15 11:50:21 +02:00 |
|
|
mrg
|
bb8157b3b7
|
Exit on DRC not run, check for LVSDRC before running in sram_base.
|
2020-07-14 08:38:49 -07:00 |
|
|
mrg
|
2b7d89d2c1
|
Fix netlist_only in sky130
|
2020-07-13 14:59:31 -07:00 |
|
|
mrg
|
a989ea63a0
|
Move magic/netgen files to tech dir
|
2020-07-09 11:33:14 -07:00 |
|
|
Matt Guthaus
|
9b939c9a1a
|
DRC/LVS and errors fixes.
Only enact pdb if assert fails in debug.error.
Only run drc/lvs one time in parse_info by saving result.
Cleanup drc/lvs output.
|
2020-06-30 07:16:05 -07:00 |
|
|
mrg
|
7ea3366ef1
|
Disable magic filter in sky130
|
2020-06-22 16:58:01 -07:00 |
|
|
mrg
|
a2d160dbf5
|
Copy magic config for filter code
|
2020-06-19 13:40:45 -07:00 |
|
|
mrg
|
617a84d4b8
|
Fix output name of magic gds filter
|
2020-06-19 07:15:27 -07:00 |
|
|
mrg
|
7dfc462ef6
|
Add magic filter before calibre for sky130
|
2020-06-15 13:58:26 -07:00 |
|
|
mrg
|
443b8fbe23
|
Change s8 to sky130
|
2020-06-12 14:23:26 -07:00 |
|
|
jcirimel
|
575278998d
|
write only used bitcells to top level in stim and pex output
|
2020-05-28 23:56:15 -07:00 |
|
|
jcirimel
|
0f9e38881c
|
update stim for large pex layouts
|
2020-05-04 03:05:33 -07:00 |
|
|
mrg
|
2850b9efb5
|
Don't force check in lib characterization. PEP8 formatting.
|
2020-04-02 12:52:42 -07:00 |
|
|
mrg
|
2f353187ba
|
Skywater extraction mode for si unit scales
|
2020-03-24 12:41:15 -07:00 |
|
|
Jesse Cirimelli-Low
|
6e070925b6
|
update magic for multiport
|
2020-01-28 02:32:34 +00:00 |
|
|
Jesse Cirimelli-Low
|
1a97dfc63e
|
syncronize bitline naming convention betwen bitcell and pbitcell
|
2020-01-27 11:50:43 +00:00 |
|
|
Jesse Cirimelli-Low
|
d42cd9a281
|
pbitcell working with bitline adjustments
|
2020-01-27 10:03:31 +00:00 |
|
|
jcirimel
|
40c01dab85
|
fix bl in stim file
|
2020-01-21 01:44:15 -08:00 |
|
|
jcirimel
|
73691f6054
|
fix bug in top level bitline label placement
|
2020-01-21 00:20:52 -08:00 |
|
|
jcirimel
|
075bf0d841
|
label bitcell in stim, add s_en top level to stim
|
2020-01-16 03:51:29 -08:00 |
|
|
jcirimel
|
f0958b0b11
|
squashed update of pex progress due to timezone error
|
2019-12-18 03:03:13 -08:00 |
|
|
Matt Guthaus
|
d511f648c6
|
Move DRC/LVS/PEX tools to tech file.
|
2019-11-29 12:01:33 -08:00 |
|
 Bin Wu
|
8e5fa7c7ae
|
fix the run_pex function for calibre
|
2019-06-25 15:06:07 -07:00 |
|
|
Bin Wu
|
3f3ee9b885
|
add pex function for magic and openram test
|
2019-06-25 11:24:25 -07:00 |
|