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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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03dad01e4cefbaae4785243161bdab701e6a888e
OpenRAM/compiler/verify
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mrg 03dad01e4c Use readspice to define ports from sp netlist in Magic extract.
2020-11-10 17:06:24 -08:00
..
__init__.py
Temp comment Magic GDS filter code.
2020-11-10 13:37:18 -08:00
assura.py
Output DRC and LVS run files to output directory.
2020-11-09 11:12:31 -08:00
calibre.py
Use readspice to define ports from sp netlist in Magic extract.
2020-11-10 17:06:24 -08:00
magic.py
Use readspice to define ports from sp netlist in Magic extract.
2020-11-10 17:06:24 -08:00
none.py
Use readspice to define ports from sp netlist in Magic extract.
2020-11-10 17:06:24 -08:00
run_script.py
Output DRC and LVS run files to output directory.
2020-11-09 11:12:31 -08:00
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