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358 Commits

Author SHA1 Message Date
mrg 848241a3ad PEP8 cleanup 2020-05-11 16:22:17 -07:00
mrg b7c66d7e07 Changes to simplify metal preferred directions and pitches. 
Changes to allow decoder height to be a 2x multiple of bitcell height.
Split of control logic tests.
Fixed track spacing in SRAM and channel router
PEP8 cleanup.
 2020-05-10 11:32:45 -07:00
mrg dd73afc983 Changes to allow decoder height to be a 2x multiple of bitcell height. 
Convert to use li layer in pgates.
Fix multifinger devices with li layers.
Simplify wordline driver input routing.
Fix power pin direction option update.
PEP8 cleanup
Changes to simplify metal preferred directions and pitches.
Split of control logic tests.
 2020-05-10 06:56:22 -07:00
Joey Kunzler e642b8521b increase col_mux bitline spacing to fix cyclic vcg 2020-05-06 13:02:33 -07:00
Joey Kunzler 91dbbed9ba added horizontal trunk route edit to vertical trunk route 2020-05-05 12:18:26 -07:00
Joey Kunzler 1b6634bb97 port data routing fix 2020-04-29 15:48:15 -07:00
Joey Kunzler 0bae652be9 fix merge conflicts 2020-04-23 11:51:46 -07:00
mrg ab91d0ab1d Add purpose to string output 2020-04-21 15:20:30 -07:00
mrg dfbf6fe45c Default is to use preferred layer directions 2020-04-20 15:33:53 -07:00
mrg 7f65176908 Configured bitline directions into prot_data 2020-04-20 14:23:40 -07:00
Joey Kunzler 7920b0cef9 m3 min area rounding fix 2020-04-17 12:36:48 -07:00
mrg d1319d633d Don't widen too short wires either 2020-04-16 11:02:54 -07:00
mrg b347e3f7a8 Try both layers for reversed layer stacks. 2020-04-15 16:49:04 -07:00
mrg 94eb2afa36 Change to callable DRC rule. Use bottom coordinate for bus offsets. 2020-04-15 15:29:55 -07:00
mrg 43fe1ae023 Improve pitch computation 2020-04-15 11:16:45 -07:00
mrg 331a4f4606 Fix wire width bug in short jogs. PEP8 cleanup. 2020-04-15 09:48:42 -07:00
mrg ade3b78711 Add exception errors file 2020-04-08 16:55:45 -07:00
mrg cd8dc8e20b Output lvs model instead of spice model 2020-04-06 14:08:38 -07:00
mrg ab5dd47182 Ptx is in microns if lvs_lib exists 2020-04-03 14:06:56 -07:00
mrg f358de78bb Add optional lvs_lib netlists for LVS usage (sp_lib is for simulation) 2020-04-03 13:39:54 -07:00
mrg 8603d3edd6 PEP8 cleanup 2020-04-03 11:37:06 -07:00
mrg 2850b9efb5 Don't force check in lib characterization. PEP8 formatting. 2020-04-02 12:52:42 -07:00
mrg 67de7efd49 Fix syntax error. No DRC/LVS in netlist only mode. 2020-04-02 11:31:28 -07:00
mrg 5349323acd PEP8 cleanup. DRC/LVS returns errors. 2020-04-02 09:47:39 -07:00
mrg a9d3548be1 Refactor drc/lvs error output 2020-04-01 15:54:06 -07:00
mrg 9907daaffa Min area only for multiple layers 2020-03-26 13:05:02 -07:00
mrg d2c97d75a7 Add well contact and min area to power pin of precharge 2020-03-26 11:49:32 -07:00
mrg ad98137cd4 Merge branch 'dev' into tech_migration 2020-03-05 14:18:06 -08:00
mrg 287a31f598 Precharge updates. 
Enable different layers for bitlines.
Jog bitlines to fit precharge transistors for close proximity bitlines.
PEP8 cleanup.
 2020-03-04 17:39:11 -08:00
Joey Kunzler d7529ce526 Vdd/gnd via stacks now use perferred directions, added cell property to override 2020-03-04 17:05:19 -08:00
mrg 7ba9e09e12 Incomplete precharge layer decoupling 2020-03-04 22:23:05 +00:00
mrg e1b97f58e1 Add instance center location 2020-02-28 18:24:09 +00:00
mrg e80677caf7 Merge remote-tracking branch 'origin/dev' into tech_migration 2020-02-25 00:36:43 +00:00
mrg 35110a4453 Improve debug of non-manhattan error 2020-02-25 00:34:28 +00:00
Joey Kunzler 4c9b3c5864 Merge branch 's8_update' into dev 
Add lpp to addText(), remove reference to specific technology in gdsMill
 2020-02-24 14:02:18 -08:00
Joey Kunzler c9cb387912 fixed variable typo 2020-02-20 18:35:54 -08:00
Joey Kunzler d6987ac584 added purposes to addText(), removed reference to specific tech from gdsMill 2020-02-19 16:26:52 -08:00
Bastian Koppelmann 76256a2f1b sense_amp: Allow custom pin names 
we don't want to propagate the sense amp's bl/br names out of the
sense_amp_array. Thus the sense_amp_array gets them named as
"bl"/"br" again.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-17 15:20:12 +01:00
Bastian Koppelmann 9a12b68680 write_driver: Allow custom pin names 
we don't want to propagate the write driver bl/br names out of the
write_driver_array. Thus the write_driver_array gets them named as
"bl"/"br" again.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-17 14:25:00 +01:00
Bastian Koppelmann c97bad72db custom_cell_properties: Add bitcell pin name API 
this allows users to overrride the pin names to match the names of their
GDS.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-12 15:37:51 +01:00
Jesse Cirimelli-Low a23f72d5a3 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev 2020-02-12 06:54:03 +00:00
Jesse Cirimelli-Low aedbc5f968 merge custom cell and module properties 2020-02-12 04:09:40 +00:00
mrg 5928a93772 Merge branch 'dev' into tech_migration 2020-02-10 22:42:50 +00:00
jcirimel b212b3e85a s8 gdsless netlist only working up to dff array 2020-02-09 21:37:09 -08:00
Jesse Cirimelli-Low 3a06141030 add simple sram sizing for netlist only 2020-02-06 12:10:49 +00:00
mrg 04d254542d Add general well_extend_active DRC in design class. 2020-02-05 18:22:22 +00:00
mrg 4526986de3 Update contact well support. 
Add asymmetric tap overlap support in DRC rules.
Add static nwell and pwell contact in class for measurements.
 2020-02-05 18:21:01 +00:00
mrg 53217e4030 Check min well width in contact and redo position 2020-02-04 17:37:58 +00:00
mrg 79391b84da Cleanup and rename vias. 2020-01-30 01:45:33 +00:00
Bastian Koppelmann 9749c522d1 tech: Make power_grid configurable 
this is the first step to allow engineers, porting technologies, more room
for routing their handmade cells.

For now, we don't allow the specification of power_grids where the lower layer
prefers to be routed vertically. This is due to the router not
connecting some pins properly in that case.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-28 12:06:34 +01:00
Bastian Koppelmann 988df8ebb9 hierarchy_layout: Add methods to create via stacks 
this allows us to simplify add_power_pin() and gives a clean
API to create vias through multiple layers.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-28 11:47:32 +01:00
Matt Guthaus e62beae805 Merge branch 'tech_migration' into dev 2020-01-25 12:03:56 -08:00
mrg 877ea53b7f Fix conflicting boundary name 2020-01-24 21:24:44 +00:00
mrg 71cbe74017 Round middle position fix 2020-01-24 18:00:28 +00:00
mrg 9beb0f4ece Add separate well design rules. 
Needed to fix various pgates with wells.
Did some cleanup of these gates as well.
 2020-01-23 19:43:41 +00:00
mrg 306740f0f3 Add empty minarea function 2020-01-16 19:27:59 +00:00
mrg 262782cba0 Remove print, fix compare 2020-01-16 19:27:39 +00:00
mrg a2387da29d PEP format design 2020-01-16 19:26:57 +00:00
mrg ea00258be9 Cleanup contact 2020-01-16 19:26:43 +00:00
Bastian Koppelmann c0c89e465a vector: Implement hash cache for vector3d and vector 
this gives us a small runtime improvement in the router.

For FreePDK45 word_size=8, num_words=256

Improved
*** Maze routing supplies: 89.8 seconds
** Routing: 279.3 seconds

Non-improved
*** Maze routing supplies: 105.1 seconds
** Routing: 293.5 seconds

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-03 12:16:10 +01:00
Bastian Koppelmann 7ff5121d8c base/pin_layout: Implement hash cache 
the hash value only depends of the properties 'rect' and 'layer' so we
only compute the hash if those values are changed. Otherwise we just
return the precomputed value. This gives us a major speedup (~10x) if
the hash is used as a key in a dict.

During the grouping of pins in analyze_pins() this gives the best
improvements. For example for FreePDK45 with num_bits=8, num_words=256

Improved
**** Analyzing pins: 20.9 seconds
** Routing: 293.8 seconds
** SRAM creation: 349.8 seconds

Non-improved
**** Analyzing pins: 267.9 seconds
** Routing: 537.5 seconds
** SRAM creation: 592.9 seconds

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-03 11:39:59 +01:00
Bastian Koppelmann 14e8a26246 base/pin_layout: Make rect and layer properties 
only rect and layer are used to compute the hash for a pin. Having
those as properties allows us to cache the hash value and only update it
if either rect or layer are written.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-03 11:33:34 +01:00
Matthew Guthaus bec12f5b94 Cleanup. 2019-12-23 21:16:08 +00:00
Matt Guthaus 4ad920eaf7 Small fixes to tech usage. 2019-12-23 08:42:52 -08:00
Matt Guthaus 9e8b03d6c2 Merge branch 'dev' into tech_migration 2019-12-19 16:23:22 -08:00
Matt Guthaus b7d78ec2ec Fix ptx active contact orientation to non-default M1 direction. 2019-12-19 12:54:10 -08:00
Matt Guthaus 36cb675150 Fix minwidth for multiple via bug. 2019-12-18 09:30:00 -08:00
Bastian Koppelmann de6b207798 hierachy_layout: Move number of via arg to add_power_pins() 
this allows custom modules to state how many vias they need
for power rails.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2019-12-18 17:33:43 +01:00
Matthew Guthaus 8e151553e4 Update contact types. 
Use preferred directions in tech files.
Programmatically generate based on interconnect stacks.
 2019-12-17 23:45:07 +00:00
Matthew Guthaus fc4685c7f7 Cleanup. 2019-12-17 23:07:01 +00:00
Matt Guthaus c025ce6356 Add li to preferred direction 2019-12-17 14:06:23 -08:00
Matt Guthaus 24546461ad Fix over-writing of active spacing rule. 2019-12-17 11:23:59 -08:00
Matt Guthaus ed28b4983b Clean up and generalize layer rules. 
Convert metalN to mN.
Generalize helper constants in modules for
space, width, enclose, etc.
Use layer stacks whever possible.
Try to remove drc() calls in liu of helper constants.
 2019-12-17 11:03:36 -08:00
Matt Guthaus a79d03fef4 Remove poly contact 2019-12-16 17:18:49 -08:00
Matt Guthaus e143a6033f Use layer stacks from tech file in design class and throughout 2019-12-13 14:13:41 -08:00
Matt Guthaus e048ada23c Abstract basic DRC checks 2019-12-11 17:56:55 -08:00
Matt Guthaus f9a66e86b4 Add npc option to contact 2019-12-11 09:09:59 -08:00
Matt Guthaus 4a1b10ff0d Remove extra cast 2019-12-05 21:33:13 -08:00
Matthew Guthaus 5af22b79e2 Only add boundary for if there's a DRC stdc layer 2019-12-06 02:17:58 +00:00
Matt Guthaus 53c72c6054 Merge branch 'tech_migration' of github.com:VLSIDA/PrivateRAM into tech_migration 2019-12-05 15:41:56 -08:00
Matt Guthaus d150b165de Merge branch 'tech_migration' of github.com:VLSIDA/PrivateRAM into tech_migration 2019-12-05 15:38:29 -08:00
Matt Guthaus b1d8a35aa7 Add contact variation 2019-12-05 15:38:25 -08:00
Matthew Guthaus 3deeaf7164 Decrease verbosity of boundary layer 2019-12-05 23:33:23 +00:00
Matthew Guthaus 7397f110c5 Add bbox for special DRC rule boundary 2019-12-05 23:14:25 +00:00
Matt Guthaus 69bb245f28 Updates to gdsMill/tech layers 
Create active and poly contact types.
Define standard cell boundary option.
DataType and PurposeLayer are the same. Text must have type 0.
Remove vector from vlsiLayout. More debug in reader.
 2019-12-04 16:12:53 -08:00
Matt Guthaus 909321326d Ignore unused layers 2019-11-26 13:21:29 -08:00
Matthew Guthaus c4cf8134fe Undo changes for config expansion. Change unit tests to use OPENRAM_HOME. 2019-11-15 18:47:59 +00:00
Matthew Guthaus 131f4bda4a Add layer-purpose GDS support. Various PEP8 fixes. 2019-11-14 18:17:20 +00:00
Matthew Guthaus 32f1cde897 PEP8 formatting 2019-11-07 16:48:37 +00:00
Matt Guthaus 38213d998f Add separate layer and purpose pairs to tech layers. 2019-10-25 10:03:25 -07:00
mrg d583695959 Remove some flake8 errors/warnings. 2019-10-02 23:26:02 +00:00
Matt Guthaus 289d3b3988 Feedthru port edits. 
Comment about write driver size for write through to work, but
disable write through in functional simulation.
Provide warning in Verilog about write throughs.
 2019-09-27 14:18:49 -07:00
Matt Guthaus 4c3b171b72 Share nominal temperature and voltage. Nominal instead of typical. 2019-09-04 16:53:58 -07:00
jsowash 01bdea23ae Merge branch 'add_wmask' of https://github.com/VLSIDA/PrivateRAM into add_wmask 2019-09-03 11:50:57 -07:00
jsowash b5ca417b26 Added fix for column mux lib generation.: 2019-09-03 11:50:39 -07:00
Matt Guthaus 69c5608b53 Allow gds to be written with supplies off. Fix extraction bug with new options. 2019-09-03 11:23:35 -07:00
Matt Guthaus 7fe9e5704d Convert vcg and nets to ordered dict 2019-08-29 16:06:34 -07:00
Matt Guthaus ee2456f433 Merge branch 'add_wmask' into dev 2019-08-22 15:01:41 -07:00
Matt Guthaus bdf29c3a26 Fix non-preferred route width again. This time it is likely right. 2019-08-22 13:57:14 -07:00
Matt Guthaus afaa946f9c Fix width of non-preferred trunk wire 2019-08-22 12:03:38 -07:00