mirror of https://github.com/VLSIDA/OpenRAM.git
Add general well_extend_active DRC in design class.
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@ -113,6 +113,15 @@ class design(hierarchy_design):
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if match:
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setattr(self, match.group(0), drc(match.group(0)))
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# Create the maximum well extend active that gets used
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# by cells to extend the wells for interaction with other cells
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from tech import layer
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self.well_extend_active = 0
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if "nwell" in layer:
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self.well_extend_active = max(self.well_extend_active, self.nwell_extend_active)
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if "pwell" in layer:
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self.well_extend_active = max(self.well_extend_active, self.pwell_extend_active)
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# These are for debugging previous manual rules
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if False:
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print("poly_width", self.poly_width)
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