mirror of https://github.com/VLSIDA/OpenRAM.git
hierarchy_layout: Add methods to create via stacks
this allows us to simplify add_power_pin() and gives a clean API to create vias through multiple layers. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
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@ -11,6 +11,7 @@ import gdsMill
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import debug
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from tech import drc, GDS
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from tech import layer as techlayer
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from tech import layer_stacks
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import os
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from globals import OPTS
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from vector import vector
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@ -508,6 +509,71 @@ class layout():
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# We don't model the logical connectivity of wires/paths
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self.connect_inst([])
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return inst
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def add_via_stack(self, offset, direction, from_layer, to_layer,
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size=[1,1]):
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"""
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Punch a stack of vias from a start layer to a target layer.
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"""
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return self.__add_via_stack_internal(offset=offset,
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direction=direction,
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from_layer=from_layer,
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to_layer=to_layer,
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via_func=self.add_via,
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last_via=None,
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size=size)
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def add_via_stack_center(self, offset, direction, from_layer, to_layer,
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size=[1,1]):
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"""
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Punch a stack of vias from a start layer to a target layer by the center
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coordinate accounting for mirroring and rotation.
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"""
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return self.__add_via_stack_internal(offset=offset,
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direction=direction,
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from_layer=from_layer,
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to_layer=to_layer,
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via_func=self.add_via_center,
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last_via=None,
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size=size)
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def __add_via_stack_internal(self, offset, direction, from_layer, to_layer,
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via_func, last_via, size):
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"""
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Punch a stack of vias from a start layer to a target layer. Here we
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figure out whether to punch it up or down the stack.
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"""
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if from_layer == to_layer:
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return last_via
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from_id = int(from_layer[1])
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to_id = int(to_layer[1])
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if from_id < to_id: # grow the stack up
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search_id = 0
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next_id = 2
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else: # grow the stack down
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search_id = 2
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next_id = 0
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curr_stack = next(filter(lambda stack: stack[search_id] == from_layer, layer_stacks), None)
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if curr_stack is None:
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raise ValueError("Cannot create via from '{0}' to '{1}'." \
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"Layer '{0}' not defined"
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.format(from_layer, to_layer))
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via = via_func(layers=curr_stack, size=size, offset=offset, directions=direction)
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return self.__add_via_stack_internal(offset=offset,
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direction=direction,
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from_layer=curr_stack[next_id],
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to_layer=to_layer,
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via_func=via_func,
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last_via=via,
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size=size)
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def add_ptx(self, offset, mirror="R0", rotate=0, width=1, mults=1, tx_type="nmos"):
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"""Adds a ptx module to the design."""
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@ -1131,17 +1197,12 @@ class layout():
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else:
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direction = ("H", "H")
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if start_layer == "m1":
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self.add_via_center(layers=self.m1_stack,
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size=size,
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offset=loc,
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directions=direction)
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via = self.add_via_stack_center(from_layer=start_layer,
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to_layer="m3",
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size=size,
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offset=loc,
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direction=direction)
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if start_layer == "m1" or start_layer == "m2":
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via = self.add_via_center(layers=self.m2_stack,
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size=size,
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offset=loc,
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directions=direction)
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if start_layer == "m3":
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self.add_layout_pin_rect_center(text=name,
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layer="m3",
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