 Matt Guthaus
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f8513da162
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Remove local temp dir
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2018-11-28 17:04:53 -08:00 |
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Matt Guthaus
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a2a9cea37e
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Make column decoder same height as control to control and supply overlaps
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2018-11-28 16:59:58 -08:00 |
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 Jesse Cirimelli-Low
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79c4b3c4cd
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added files links
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2018-11-28 16:56:24 -08:00 |
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Matt Guthaus
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3cfe74cefb
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Functional simulation uses threshold for high and low noise margins
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2018-11-28 16:55:04 -08:00 |
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Jesse Cirimelli-Low
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44638cb885
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jinja2 file browser working
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2018-11-28 16:48:24 -08:00 |
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Matt Guthaus
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25ae3a5eae
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Fix error of no control bus width
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2018-11-28 15:42:51 -08:00 |
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Matt Guthaus
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d99dcd33e2
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Fix SRAM level control routing errors.
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2018-11-28 15:30:52 -08:00 |
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Matt Guthaus
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143e4ed7f9
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Change hierchical decoder output order to match changes to netlist.
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2018-11-28 14:09:45 -08:00 |
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 Matt Guthaus
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b5b691b73d
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Fix missing via in clk input of control
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2018-11-28 13:20:39 -08:00 |
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Matt Guthaus
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2ed8fc1506
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pgate inputs and outputs are all on M1 for flexible via placement when using gates.
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2018-11-28 12:42:29 -08:00 |
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Matt Guthaus
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93904d9f2d
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Control logic passes DRC/LVS in SCMOS
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2018-11-28 11:02:24 -08:00 |
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Matt Guthaus
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410115e830
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Modify dff_buf to stagger Q and Qb outputs.
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2018-11-28 10:43:11 -08:00 |
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Matt Guthaus
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25611fcbc1
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Remove dff_inv since we can just use dff_buf
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2018-11-28 10:42:22 -08:00 |
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Matt Guthaus
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ea6abfadb7
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Stagger outputs of dff_buf
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2018-11-28 09:48:16 -08:00 |
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Matt Guthaus
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d2ca2efdbe
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Limit ps, pd, as, ad precision in ptx.
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2018-11-28 09:47:54 -08:00 |
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Jesse Cirimelli-Low
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a56e3f609b
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removed debug print statements
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2018-11-28 09:39:58 -08:00 |
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Jesse Cirimelli-Low
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0920321a2e
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start of static html generation code
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2018-11-27 19:49:05 -08:00 |
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Matt Guthaus
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c43a140b5e
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All control routed and DRC clean. LVS errors.
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2018-11-27 17:18:03 -08:00 |
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Matt Guthaus
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5d59863efc
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Fix p_en_bar at top level. Change default scn4m period to 10ns.
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2018-11-27 14:44:55 -08:00 |
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Matt Guthaus
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c45f990413
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Change en to en_bar in precharge. Fix logic for inverted p_en_bar.
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2018-11-27 14:17:55 -08:00 |
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Matt Guthaus
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0c286d6c29
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Revert to 5V example until we fix spice models in scn4m_subm
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2018-11-27 14:17:06 -08:00 |
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Jesse Cirimelli-Low
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5aa8c46c16
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Merge branch 'dev' into datasheet_gen
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2018-11-27 13:54:21 -08:00 |
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Matt Guthaus
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bf31126679
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Correct decoder output numbers to follow address order
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2018-11-27 12:03:13 -08:00 |
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Matt Guthaus
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b912f289a6
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Remove extra X in instance names
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2018-11-27 12:02:53 -08:00 |
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Matt Guthaus
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2237af0463
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Merge branch 'multiport_control_fix' of ssh://scone/home/mrg/openram into multiport_control_fix
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2018-11-26 18:01:34 -08:00 |
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Matt Guthaus
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cf23eacd0e
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Add wl_en
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2018-11-26 18:00:59 -08:00 |
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Matt Guthaus
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21759d59b4
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Remove inverter in wordline driver
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2018-11-26 16:41:31 -08:00 |
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Matt Guthaus
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9e0b31d685
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Make pand2 and pbuf derive pgate. Initial DRC wrong layout.
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2018-11-26 16:19:18 -08:00 |
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Matt Guthaus
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dd79fc560b
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Corretct modules for add_inst
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2018-11-26 15:35:29 -08:00 |
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Matt Guthaus
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b440031855
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Add netlist only mode to new pgates
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2018-11-26 15:29:42 -08:00 |
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Matt Guthaus
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2eff166527
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Rotate vias in pand2
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2018-11-26 14:05:04 -08:00 |
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Matt Guthaus
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5209619987
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Move pnand2 output to allow input pin access on M2
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2018-11-26 13:59:53 -08:00 |
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Matt Guthaus
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8fba32ca12
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Add pand2 draft
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2018-11-26 13:45:22 -08:00 |
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 Jennifer Eve Sowash
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524334d24d
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Merge branch 'dev' into pdriver
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2018-11-26 13:15:47 -08:00 |
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 Hunter Nichols
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b06aa84824
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Functional tests now find a feasible period instead of using a heuristic. Bug found, trimming pbitcell netlists causes bit flips.
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2018-11-23 18:55:15 -08:00 |
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Hunter Nichols
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5f954689a5
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In delay.py, altered dummy address based on column mux. Added some hacks to make min_period work for srams with columns muxes.
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2018-11-23 13:19:55 -08:00 |
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Jennifer Eve Sowash
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bb7773ca7f
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Editted pbuf.py to pass regression.
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2018-11-20 14:39:11 -08:00 |
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Jesse Cirimelli-Low
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29f19ad70f
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replaced absolute links with relative links
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2018-11-20 12:27:54 -08:00 |
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Jesse Cirimelli-Low
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7d070c2652
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Added links to logos
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2018-11-20 11:51:38 -08:00 |
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Hunter Nichols
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67977bab3e
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Fixed port issue in bank. Changed golden data due to netlist change.
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2018-11-20 11:39:14 -08:00 |
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Jesse Cirimelli-Low
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1942ef33ac
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Merge branch 'dev' into datasheet_gen
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2018-11-20 11:23:42 -08:00 |
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Hunter Nichols
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62cbbca852
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Merged, fixed conflict bt matching control logic creation to dev.
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2018-11-19 22:20:20 -08:00 |
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Hunter Nichols
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2f29ad5510
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Disabled resizing based on rise/fall delays. It creates delay chains which cannot be routed.
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2018-11-19 22:13:58 -08:00 |
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Matt Guthaus
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b8299565eb
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Use grid furthest from blockages when blocked pin. Enclose multiple connectors.
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2018-11-19 17:32:55 -08:00 |
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Hunter Nichols
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8257e4fe8c
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Changed syntax in replica_bl tests, golden data to fit new values in delay tests.
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2018-11-19 16:51:43 -08:00 |
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Matt Guthaus
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20d4e390f6
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Add bounding box of connector for when there are multiple connectors
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2018-11-19 15:45:07 -08:00 |
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Matt Guthaus
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2694ee1a4c
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Add all insufficient grids that overlap the pin at all
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2018-11-19 15:43:19 -08:00 |
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Hunter Nichols
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e8f1c19af6
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Merge branch 'dev' into multiport_characterization
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2018-11-19 15:42:48 -08:00 |
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Matt Guthaus
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a47509de26
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Move via away from cell edges
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2018-11-19 15:42:22 -08:00 |
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Hunter Nichols
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a55d907d03
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High-to-low delays and slews are copied from the low-to-high values to simplify lib file results. FIXME
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2018-11-19 15:40:26 -08:00 |
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