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base
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Use grid furthest from blockages when blocked pin. Enclose multiple connectors.
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2018-11-19 17:32:55 -08:00 |
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bitcells
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Merge branch 'dev' into multiport_layout
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2018-11-08 18:00:28 -08:00 |
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characterizer
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Fixed small bugs with new port index stuff and layout.
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2018-11-08 17:40:22 -08:00 |
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datasheet
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moved flask_table warning from sram.py to datasheet_gen.py
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2018-10-18 09:58:19 -07:00 |
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drc
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Moving wide metal spacing to routing grid level
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2018-10-15 09:59:16 -07:00 |
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gdsMill
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Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names.
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2018-11-16 11:48:41 -08:00 |
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modules
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All control routed and DRC clean. LVS errors.
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2018-11-27 17:18:03 -08:00 |
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pgates
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Limit ps, pd, as, ad precision in ptx.
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2018-11-28 09:47:54 -08:00 |
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router
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Use grid furthest from blockages when blocked pin. Enclose multiple connectors.
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2018-11-19 17:32:55 -08:00 |
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tests
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Add pand2 draft
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2018-11-26 13:45:22 -08:00 |
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verify
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Remove redundant DRC run in magic.
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2018-11-05 13:30:42 -08:00 |
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Makefile
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Add Makefile for parallel test execution.
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2018-01-22 13:39:07 -08:00 |
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debug.py
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Output debug warnings and errors to stderr. Clean up regress script a bit.
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2018-07-11 09:51:28 -07:00 |
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example_config_freepdk45.py
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Remove options from example config files
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2018-11-05 12:47:47 -08:00 |
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example_config_scn4m_subm.py
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Revert to 5V example until we fix spice models in scn4m_subm
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2018-11-27 14:17:06 -08:00 |
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gen_stimulus.py
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Convert entire OpenRAM to use python3. Works with Python 3.6.
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2018-05-14 16:15:45 -07:00 |
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globals.py
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Fix date/time formatting to remove fraction seconds.
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2018-11-14 10:31:33 -08:00 |
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openram.py
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Merge branch 'dev' into supply_routing
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2018-10-20 14:29:19 -07:00 |
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options.py
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Add wl_en
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2018-11-26 18:00:59 -08:00 |
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sram.py
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Fixed merge conflicts with sram.py
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2018-10-22 17:29:14 -07:00 |
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sram_1bank.py
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Use array ur instead of bank ur to pace row addr dff
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2018-11-19 08:41:26 -08:00 |
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sram_2bank.py
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Cleanup some items with new sram_config. Update unit tests accordingly.
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2018-09-04 10:47:24 -07:00 |
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sram_4bank.py
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Converted all submodules to use _bit notation instead of [bit]
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2018-10-11 09:53:08 -07:00 |
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sram_base.py
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Fix p_en_bar at top level. Change default scn4m period to 10ns.
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2018-11-27 14:44:55 -08:00 |
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sram_config.py
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Added custom 1rw+1r bitcell. Testing are currently failing.
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2018-10-22 17:02:21 -07:00 |
d2ca2efdbe