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OpenRAM
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70 Commits

Author SHA1 Message Date
mrg 30976df48f Change inheritance inits to use super 2020-08-06 11:33:26 -07:00
mrg c7bc01c3a9 Clean up binning. Fix mults to 1 for certain gates. 2020-07-15 17:15:42 -07:00
mrg ee0a003298 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-06-25 08:57:37 -07:00
jcirimel 59562f2b92 move accuracy_requirement from techfile to config 2020-06-25 06:44:07 -07:00
jcirimel 812cf11e95 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev 2020-06-25 06:32:29 -07:00
jcirimel 57b6d49edb fix pinv size bining 2020-06-25 06:32:07 -07:00
mrg da900b89ba Only expand implants in sky130 2020-06-24 13:48:30 -07:00
mrg ba92467fec Add no well enclosure for techs without wells 2020-06-24 12:07:47 -07:00
mrg e694622f28 use add_enclosure to extend implants 2020-06-24 11:54:59 -07:00
mrg 98ec9442c6 Add npc enclosure for pnand2, pnand3, pnor2 2020-06-24 10:00:00 -07:00
mrg a32b5b13e8 Rename nwell yoffset for consistency 2020-06-24 08:26:15 -07:00
mrg 443b8fbe23 Change s8 to sky130 2020-06-12 14:23:26 -07:00
mrg 54e4d147f6 Rail to ptx spacing based on routing layer not m1 2020-06-11 15:03:50 -07:00
mrg dff28a9997 Merge branch 'tech_migration' into dev 2020-06-10 17:09:05 -07:00
mrg 196e5998c8 Half poly space per cell at top and bottom. 2020-06-10 16:52:51 -07:00
jcirimel 08f6bd8d24 optimize tx binning for area 2020-06-05 02:53:03 -07:00
mrg 4a67f7dc71 Thin-cell decoder changes. 
Add hard decoder gates (nand, inv, pnan)
Add conditions for routing using LI layer in s8.
Generalize bus layers for decoders.
Move custom cells to own directory.
Fixed via directions, etc.
Add 4x16 hierarchical decoder and test case
 2020-05-29 10:36:07 -07:00
mrg 617bf302d1 Add option to remove wells. Save area in pgates with redundant wells. 2020-05-13 14:46:42 -07:00
mrg c96a6d0b9d Add no well option. Add stack gates vertical option. 2020-05-11 16:22:08 -07:00
mrg b7c66d7e07 Changes to simplify metal preferred directions and pitches. 
Changes to allow decoder height to be a 2x multiple of bitcell height.
Split of control logic tests.
Fixed track spacing in SRAM and channel router
PEP8 cleanup.
 2020-05-10 11:32:45 -07:00
mrg dd73afc983 Changes to allow decoder height to be a 2x multiple of bitcell height. 
Convert to use li layer in pgates.
Fix multifinger devices with li layers.
Simplify wordline driver input routing.
Fix power pin direction option update.
PEP8 cleanup
Changes to simplify metal preferred directions and pitches.
Split of control logic tests.
 2020-05-10 06:56:22 -07:00
jcirimel d8a51ecafb remove prints, scaling bug fix 2020-05-05 21:59:28 -07:00
jcirimel 71a1dd8f38 fix tx binning in col mux for memories with >1 word per row 2020-05-05 16:35:51 -07:00
jcirimel f590ecf83c fix minimum pinv sizing 2020-04-18 05:51:21 -07:00
jcirimel add9ec7b28 remove excess newlines 2020-04-18 05:42:23 -07:00
jcirimel 1f094b03bc use more optimal discrete pinv sizing 2020-04-18 05:26:39 -07:00
jcirimel 486819ae0d fix width bin typo 2020-04-17 15:27:36 -07:00
jcirimel 6c1c72c520 fix pgates binning off-by-one 2020-04-15 04:09:58 -07:00
jcirimel a0eb9839ad revert units on sp_lib, begin discrete tx simulation 2020-04-09 19:39:21 -07:00
mrg e9d0db44fd Add li_stack contact to ptx and pgate if it exists. 2020-03-23 16:55:38 -07:00
mrg 7ba9e09e12 Incomplete precharge layer decoupling 2020-03-04 22:23:05 +00:00
mrg bb2305d56a PEP8 format fixes 2020-02-28 18:24:39 +00:00
mrg 266d68c395 Generalize pgate width based on nwell/pwell contacts 2020-02-25 17:09:07 +00:00
mrg 6bcffb8efb Change default cell height and fix contact width error 2020-02-25 00:34:59 +00:00
mrg f7915ec55e Route to top of NMOS to prevent poly overlap nmos 2020-02-10 17:12:39 +00:00
mrg f0ecf385e8 Nwell fixes in pgates. 
Fix minor PEP8 format fixes.
Fix nwell to be 55% of cell height.
Move contact in hierarchical decoder for DRC error.
 2020-02-06 16:20:09 +00:00
mrg 596302d9a9 Update pgate well and well contacts. 
Extend well left and right past a cell boundary.
Use asymmetric well contacts.
 2020-02-05 18:22:45 +00:00
mrg 304971ff60 Fix ptx so nmos and pmos have same active offset and gates align 2020-02-04 17:38:35 +00:00
mrg 400cf0333a Pgates are 8 M1 high by default. Port data is bitcell height. 2020-01-30 03:34:04 +00:00
mrg 79391b84da Cleanup and rename vias. 2020-01-30 01:45:33 +00:00
mrg 71cbe74017 Round middle position fix 2020-01-24 18:00:28 +00:00
mrg 9beb0f4ece Add separate well design rules. 
Needed to fix various pgates with wells.
Did some cleanup of these gates as well.
 2020-01-23 19:43:41 +00:00
Matthew Guthaus a6f5e59e18 Remove unused layers and simplify layer check to work without it. 2019-12-23 21:49:47 +00:00
Matt Guthaus 0da8164ea6 Remove some unnecessary via directions. 2019-12-19 13:54:50 -08:00
Matt Guthaus b7d78ec2ec Fix ptx active contact orientation to non-default M1 direction. 2019-12-19 12:54:10 -08:00
Matt Guthaus aceaa9fb21 Standardize contact names. 2019-12-17 15:55:20 -08:00
Matt Guthaus ed28b4983b Clean up and generalize layer rules. 
Convert metalN to mN.
Generalize helper constants in modules for
space, width, enclose, etc.
Use layer stacks whever possible.
Try to remove drc() calls in liu of helper constants.
 2019-12-17 11:03:36 -08:00
Matt Guthaus f71cfe0d9d Generalize active and poly stacks 2019-12-13 14:56:14 -08:00
Matt Guthaus e143a6033f Use layer stacks from tech file in design class and throughout 2019-12-13 14:13:41 -08:00
Matt Guthaus b71d630643 None for layer means unused. 2019-11-26 13:34:39 -08:00