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OpenRAM
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4,804 Commits 4 Branches 63 Tags 78 MiB
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44 Commits

Author SHA1 Message Date
Jesse Cirimelli-Low 788d7e5474 fix VPB/VNB pins not being found 2023-10-31 18:07:35 -07:00
Sam Crow 539dfc979a conform default behavior for sky130 custom modules to unit test 2023-06-07 17:31:12 -07:00
samuelkcrow 672c585355 fixes to the custom module fix 2023-03-04 19:17:29 -08:00
Sam Crow f1d91efebd fix single port by using existing custom modules 2023-03-03 14:17:57 -08:00
mrg 1db9881ce7 Add sky130 corners to tech file. 2023-03-01 09:26:16 -08:00
Eren Dogan e5fc25da6f Update copyright year 2023-01-28 22:56:27 -08:00
Jesse Cirimelli-Low 69c988f853 rewrite wordline strap pin copying to not use exceptions 2022-12-19 17:30:05 -08:00
mrg 18df0f55eb Must over-ride build_graph in dummy bitcell. 2022-12-19 11:52:39 -08:00
Eren Dogan 96e57507bf Add copyright check to code format test 2022-11-30 14:50:43 -08:00
Eren Dogan fccdc3c45b Use library imports globally 2022-11-27 13:01:20 -08:00
Jesse Cirimelli-Low 3b02a8846d sky130 rba passing :) 2022-09-12 16:07:00 -07:00
Jesse Cirimelli-Low 11fa0777e8 add flatglob to tech file; sky130 replica col lvs working 2022-08-22 15:30:11 -07:00
mrg d92c7a634d Use packages for imports. 
Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.
 2022-07-13 15:55:57 -07:00
Jesse Cirimelli-Low 374562f354 rbc substrate issues 2022-06-16 15:17:07 -07:00
Jesse Cirimelli-Low 98fe4c74a4 colend fixes in progress 2022-06-15 22:34:21 -07:00
mrg bbfccd1e00 Remove netlist bl/br swaps on flipped cells 2022-05-23 17:16:36 -07:00
Jesse Cirimelli-Low 825ada8293 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2022-05-19 21:51:13 -07:00
Jesse Cirimelli-Low 172d070880 fix bl routing in rba 2022-05-19 21:45:48 -07:00
mrg 25fa0a8de3 Fix missing cell syntax error. 2022-05-19 14:53:17 -07:00
mrg bdd334bce9 Add layer and directions to pbitcell 2022-05-16 16:11:13 -07:00
mrg 64f2f90664 Rework replica_bitcell_array supplies 
Uses layer and direction preferences in tech file.
Places straps on left/right or top/bottom.
 2022-04-19 08:50:11 -07:00
Jesse Cirimelli-Low 0667a93d53 single port rba passing lvs 2022-03-07 13:45:50 -08:00
Jesse Cirimelli-Low 038acd1568 single port rba lvs progress 2022-03-07 01:20:59 -08:00
mrg 63a6168b35 Merge branch 'dev' into klayout 2022-02-01 11:57:56 -08:00
mrg 47690e0076 Merge branch 'dev' into docker 2021-12-29 14:42:32 -08:00
Jesse Cirimelli-Low 8d9166a01b only rba lvs errors is colend body extraction 2021-12-29 12:43:02 -08:00
Jesse Cirimelli-Low 9e85d17fbe merge rbc lvs fixes 2021-12-23 21:21:10 -08:00
Jesse Cirimelli-Low cf8c486cea merge sky130_dummy_array 2021-12-22 16:00:59 -08:00
Jesse Cirimelli-Low de60a1c38a merge in opc fixes 2021-12-22 15:53:36 -08:00
Jesse Cirimelli-Low 468de963f6 remove add_mod in sky130 2021-12-22 15:51:49 -08:00
Jesse Cirimelli-Low 8a0450afac adjust replica col wls 2021-12-22 15:46:03 -08:00
mrg e6e9d09369 Remove add_mod from sky130 modules 2021-12-17 10:30:55 -08:00
mrg 02364c6cdf Add klayout option in config. No tool specific LVS libs 2021-12-17 10:29:17 -08:00
mrg d555e67fb1 Add initial sky130 LVS/DRC rules. 2021-12-17 10:27:13 -08:00
Jesse Cirimelli-Low 8879820af4 replica col lvs fix 2021-12-15 14:19:52 -08:00
Jesse Cirimelli-Low 4e5744df50 remove add_mod() 2021-12-15 01:36:56 -08:00
Jesse Cirimelli-Low ddb76c4aff fix dummy array opc 2021-12-15 01:28:30 -08:00
Jesse Cirimelli-Low 8eb6caa248 fix bitcell array opc errors 2021-12-14 22:15:27 -08:00
mrg f764ac446c Use Caravel-like sky130 install path with ngspice models. 2021-11-17 13:19:23 -08:00
mrg 968a233b82 Don't install in share/pdk 2021-11-08 09:31:56 -08:00
mrg d7a20bc69b Debug initial docker run scripts 2021-11-02 15:07:18 -07:00
mrg fa2232fc11 Initial commit of sky130 config files 2021-10-04 15:16:28 -07:00
mrg fecf3b2009 Remove sky130 link 2020-10-12 16:25:07 -07:00
jcirimel d22164bd48 single port progess 2020-09-14 18:11:38 -07:00