luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
2,655 Commits 4 Branches 63 Tags 78 MiB
Commit Graph

315 Commits

Author SHA1 Message Date
mrg c10a6a29c0 Simplify precharge pin layer 2020-06-27 08:22:16 -07:00
mrg ee0a003298 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-06-25 08:57:37 -07:00
jcirimel 5941e01b51 add missing parens 2020-06-25 08:02:08 -07:00
jcirimel 59562f2b92 move accuracy_requirement from techfile to config 2020-06-25 06:44:07 -07:00
jcirimel 812cf11e95 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev 2020-06-25 06:32:29 -07:00
jcirimel 57b6d49edb fix pinv size bining 2020-06-25 06:32:07 -07:00
mrg da900b89ba Only expand implants in sky130 2020-06-24 13:48:30 -07:00
mrg ba92467fec Add no well enclosure for techs without wells 2020-06-24 12:07:47 -07:00
mrg 6c523a7556 use add_enclosure for npc contacts 2020-06-24 11:55:44 -07:00
mrg e694622f28 use add_enclosure to extend implants 2020-06-24 11:54:59 -07:00
mrg 98ec9442c6 Add npc enclosure for pnand2, pnand3, pnor2 2020-06-24 10:00:00 -07:00
mrg 1340908330 Remove fudge factor for pin spacing 2020-06-24 09:24:26 -07:00
mrg cddb16dabc Separate active and poly contact to gate rule 2020-06-24 09:17:39 -07:00
mrg a32b5b13e8 Rename nwell yoffset for consistency 2020-06-24 08:26:15 -07:00
mrg e849a9b973 Use different LVS libs based on tech and sky130 2020-06-23 14:53:24 -07:00
mrg 231f90f492 Fix missing space in ptx spice line 2020-06-19 06:47:46 -07:00
mrg 4cb827c3d7 Add redundant implant for s8 2020-06-15 10:08:07 -07:00
mrg 355474ce2c Playing around with pnand2 pin spacing rules 2020-06-15 10:07:00 -07:00
mrg 6e0008403e Update new tech name 2020-06-15 10:06:17 -07:00
mrg 7dc33285a7 Add contact to gate design rule to max for spacing inputs 2020-06-14 14:18:08 -07:00
mrg 443c401561 pnand2 B input spaced from top 2020-06-14 14:17:04 -07:00
mrg 91f20f2cf6 Better centering of pinv_dec 2020-06-14 14:09:45 -07:00
mrg 33a32101c9 DRC and LVS fixes for pinv_dec 2020-06-12 15:23:51 -07:00
mrg 443b8fbe23 Change s8 to sky130 2020-06-12 14:23:26 -07:00
mrg 54e4d147f6 Rail to ptx spacing based on routing layer not m1 2020-06-11 15:03:50 -07:00
mrg 8d52794c32 Remove printf in precharge 2020-06-11 11:57:52 -07:00
mrg 1a2e0046b1 Add contact to gate spacing for precharge 2020-06-11 11:54:34 -07:00
mrg f973dd6a5c Save LVS model with no u too for Calibre 2020-06-11 11:53:34 -07:00
mrg dff28a9997 Merge branch 'tech_migration' into dev 2020-06-10 17:09:05 -07:00
mrg 196e5998c8 Half poly space per cell at top and bottom. 2020-06-10 16:52:51 -07:00
mrg 0b4b5e7133 More exact input spacing in pnand3 2020-06-10 16:19:24 -07:00
mrg 064fe34edf Fix pinvbuf layers 2020-06-09 17:16:35 -07:00
mrg e6babc301d Incrase space for pnand gates 2020-06-09 16:34:15 -07:00
mrg a28e747a02 Fix precharge offset. Move well rules to design class. 2020-06-09 15:28:50 -07:00
mrg 8c6d5b49be Consider diffusion spacing in active offset 2020-06-09 13:09:52 -07:00
mrg 77fb7017c4 Merge branch 'tech_migration' into dev 2020-06-08 12:54:41 -07:00
mrg 9cc36c6d3a Bus code converted to pins. Fix layers on control signal routes in bank. 2020-06-08 11:01:14 -07:00
jcirimel 9857a3f7e7 Merge branch 'dev' into discrete_models 2020-06-05 16:47:01 -07:00
jcirimel 08f6bd8d24 optimize tx binning for area 2020-06-05 02:53:03 -07:00
mrg e06dc3810a Move precharge pin to bottom 2020-06-04 12:12:19 -07:00
mrg b2b7e7800b Undo same bitline pitch 2020-06-03 16:39:05 -07:00
mrg 4183638f03 Align precharge bitlines with col mux 2020-06-03 16:05:57 -07:00
mrg 4bc1e9a026 Fix the bitline spacing in the column mux to a constant. 2020-06-03 15:47:03 -07:00
Joey Kunzler 84021c9ccb merge conflict 2 - port data 2020-06-02 16:32:08 -07:00
Joey Kunzler 001bf1b827 merge conflict - port data 2020-06-02 14:15:39 -07:00
mrg b0aa70ffda Fix precharge vdd route layer 2020-06-02 09:23:27 -07:00
mrg b3b03d4d39 Hard cells can accept height parameter too. 2020-06-01 16:46:00 -07:00
mrg 82dc937768 Add missing vias by using via stack function 2020-05-29 16:53:47 -07:00
mrg 4a67f7dc71 Thin-cell decoder changes. 
Add hard decoder gates (nand, inv, pnan)
Add conditions for routing using LI layer in s8.
Generalize bus layers for decoders.
Move custom cells to own directory.
Fixed via directions, etc.
Add 4x16 hierarchical decoder and test case
 2020-05-29 10:36:07 -07:00
Joey Kunzler 9a6b38b67e merge conflict 2020-05-26 16:03:36 -07:00