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17,327 Commits 135 Branches 69 Tags 48 MiB
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17327 Commits

Author SHA1 Message Date
Emil J. Tywoniak f592f2f3af WIP 2026-06-10 19:22:53 +02:00
Emil J. Tywoniak 015ab4e45b twine: start indexable colony with integer indices including preallocated twines 2026-06-10 14:54:48 +02:00
Emil J. Tywoniak 8ab96a4285 BROKEN 2026-06-10 14:54:48 +02:00
Emil J. Tywoniak 2117af318c WIP 2026-06-10 14:54:48 +02:00
Emil J. Tywoniak d13dfc21f4 WIP 2026-06-10 14:54:48 +02:00
Emil J. Tywoniak 1a8a95b472 rtlil: fix masquerade 2026-06-10 14:54:45 +02:00
Emil J. Tywoniak 2d3b7e9c92 rtlil: introduce ModuleNameMasq (KNOWN BROKEN, do not merge) 2026-06-10 14:54:43 +02:00
Emil J. Tywoniak e2627b367e rtlil: set Module::design before name at all construction sites 2026-06-10 14:54:39 +02:00
Emil J. Tywoniak 734593e12d rtlil: Module::clone attaches to source design; callers use clone(dst) 2026-06-10 14:54:34 +02:00
Emil J. Tywoniak 8f8a07efee rtlil: replace AttrObject::meta_idx_ with ObjMeta pointer 2026-06-10 14:54:31 +02:00
Emil J. Tywoniak cfd7edc608 Patch: route staged cell names through per-Patch dict 2026-06-10 14:54:27 +02:00
Emil J. Tywoniak 0f31d3089e rtlil: extend per-Design meta vector to hold name slot 2026-06-10 14:54:16 +02:00
Emil J. Tywoniak ca632e82c4 rtlil: set Module* on inner-process AttrObjects at construction 2026-06-10 14:54:12 +02:00
Emil J. Tywoniak f1edb571f2 rtlil: evacuate src_id_ from AttrObject to per-Design meta vector 2026-06-10 14:54:05 +02:00
Emil J. Tywoniak e70eed3296 rtlil: add Module* back-pointer to RTLIL::Memory 2026-06-10 14:53:59 +02:00
Emil J. Tywoniak 9ed93e210b rtlil: add per-Design src meta vector + freelist 2026-06-10 14:53:55 +02:00
Emil J. Tywoniak 29ab42bc4e rtlil: add Module* back-pointer to inner-process AttrObjects 2026-06-10 14:53:48 +02:00
Emil J. Tywoniak 3424c00cd0 twine 2026-06-10 14:53:45 +02:00
Emil J. Tywoniak 3d27e83d0f memory_map: propagate Mem src onto every generated cell 2026-06-10 14:53:42 +02:00
Emil J. Tywoniak 7656347b44 patch: split into single-output patch + multi-output patch_ports; drop input-cone gc 2026-06-10 14:53:37 +02:00
Emil J. Tywoniak 61b0dfd3bf patch: gc collects src from every removed cell; ff.cc routes through Patch 2026-06-10 14:53:28 +02:00
Emil J. Tywoniak e583da906d patch: merge src into existing cells; opt_merge/_inc + onehot + ff.cc use Patch 2026-06-10 14:53:19 +02:00
Emil J. Tywoniak ea41e61a36 utils: add BitGrouper for shared bit-partition logic 2026-06-10 14:53:13 +02:00
Emil J. Tywoniak d952b04e54 opt_expr: convert remaining rewrites to patcher 2026-06-10 14:53:05 +02:00
Emil J. Tywoniak a689cdc6ed patch: don't track root cell deletions for perf 2026-06-10 14:53:04 +02:00
Emil J. Tywoniak e2a77db87a opt_expr: evener morer patcherer 2026-06-10 14:53:03 +02:00
Emil J. Tywoniak edeb649154 opt_expr: even more patcher 2026-06-10 14:53:02 +02:00
Emil J. Tywoniak f18f46cc9b patch: don't gc signorm cells 2026-06-10 14:53:01 +02:00
Emil J. Tywoniak fb021b1a6b opt_expr: more patcher again 2026-06-10 14:53:00 +02:00
Emil J. Tywoniak 48a3b84e88 WIP 2026-06-10 14:52:59 +02:00
Emil J. Tywoniak 1291cddcb1 WIP 2026-06-10 14:52:58 +02:00
Emil J. Tywoniak c264649ae7 rtlil, patch: incremental signorm via connect_incremental, replacing batched sigNormalize in Patch::patch 2026-06-10 14:52:53 +02:00
Emil J. Tywoniak c3457e2e5c WIP 2026-06-10 14:52:50 +02:00
Emil J. Tywoniak dab9a386cc opt_expr: WIP use patcher more 2026-05-28 22:51:30 +02:00
Emil J. Tywoniak b594196a48 opt_expr: cleanup 2026-05-28 14:56:27 +02:00
Emil J. Tywoniak 5cdb189ea0 opt_expr: cleanup 2026-05-28 14:53:21 +02:00
Emil J. Tywoniak 12e94a9a8c patch: cleanup 2026-05-28 14:49:07 +02:00
Emil J. Tywoniak cef8186c4a patch: infer leaves for gc 2026-05-28 12:56:13 +02:00
Emil J. Tywoniak 1cd0d37511 patch: instead of cell->cell, use port->sig rewrites 2026-05-27 18:07:01 +02:00
Emil J. Tywoniak b3a33aeeba opt_expr: use patcher for xor constant folding 2026-05-27 18:06:55 +02:00
Emil J. Tywoniak 688d256edc patch: fix gc 2026-05-27 17:04:31 +02:00
Emil J. Tywoniak 698f6e05c0 patch: fix const handling 2026-05-27 17:04:31 +02:00
Emil J. Tywoniak 5a6568edbe rtlil, patch: update signorm index and driver fields when committing Cell from Patch to Design 2026-05-23 01:09:26 +02:00
Emil J. Tywoniak b0eb50be1b fixup! patch: working multi-cell signorm invariant 2026-05-23 00:11:16 +02:00
Emil J. Tywoniak 9f22b9d2a0 patch: source transfer 2026-05-23 00:10:02 +02:00
Emil J. Tywoniak db1c1d4359 patch: working multi-cell signorm invariant 2026-05-23 00:10:00 +02:00
Emil J. Tywoniak e78e19acfe patch: fix patch mixins 2026-05-23 00:09:17 +02:00
Emil J. Tywoniak 8c26ecd2a6 patch: WIP multicell patch test 2026-05-23 00:09:17 +02:00
Emil J. Tywoniak 6b16a0cac8 patch: wires 2026-05-23 00:09:17 +02:00
Emil J. Tywoniak d2ae9b48e4 patch: signorm, move 2026-05-23 00:09:17 +02:00