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WIP

This commit is contained in:
Emil J. Tywoniak 2026-05-29 18:02:39 +02:00
parent c264649ae7
commit 1291cddcb1
3 changed files with 5 additions and 2 deletions
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3
backends/aiger/xaiger.cc
View File

@ -187,6 +187,9 @@ struct XAigerWriter
TimingInfo timing;
for (auto cell : module->cells()) {
if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
continue;
if (!cell->has_keep_attr()) {
if (cell->type == ID($_NOT_))
{

2
tests/arch/analogdevices/dsp_abc9.ys
View File

@ -37,6 +37,6 @@ verilog_defaults -add -D ALLOW_WHITEBOX_DSP48E1
synth_analogdevices
techmap -autoproc -wb -map +/analogdevices/cells_sim.v
opt -full -fine
select -assert-count 0 t:* t:$assert %d
select -assert-count 0 t:* t:$assert %d t:$*_port %d t:$public %d
sat -verify -prove-asserts

2
tests/arch/xilinx/dsp_abc9.ys
View File

@ -37,7 +37,7 @@ verilog_defaults -add -D ALLOW_WHITEBOX_DSP48E1
synth_xilinx -abc9
techmap -autoproc -wb -map +/xilinx/cells_sim.v
opt -full -fine
select -assert-count 0 t:* t:$assert %d
select -assert-count 0 t:* t:$assert %d t:$*_port %d t:$public %d
sat -verify -prove-asserts