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opt_expr: cleanup
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5cdb189ea0
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b594196a48
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@ -618,11 +618,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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log_abort();
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}
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auto port_a = ID::A;
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if (!sig_a.wire) {
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if (!sig_a.wire)
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std::swap(sig_a, sig_b);
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port_a = ID::B;
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}
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if (sig_b == State::S0 || sig_b == State::S1) {
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if (cell->type.in(ID($xor), ID($_XOR_))) {
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if (sig_b == State::S0) {
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