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WIP

This commit is contained in:
Emil J. Tywoniak 2026-06-10 19:22:53 +02:00
parent 015ab4e45b
commit f592f2f3af
203 changed files with 4575 additions and 4481 deletions
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44
backends/aiger/aiger.cc
View File

@ -223,8 +223,8 @@ struct AigerWriter
{
if (cell->type == ID($_NOT_))
{
SigBit A = sigmap(cell->getPort(ID::A).as_bit());
SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit Y = sigmap(cell->getPort(TW::Y).as_bit());
unused_bits.erase(A);
undriven_bits.erase(Y);
not_map[Y] = A;
@ -233,14 +233,14 @@ struct AigerWriter
if (cell->type.in(ID($_FF_), ID($_DFF_N_), ID($_DFF_P_)))
{
SigBit D = sigmap(cell->getPort(ID::D).as_bit());
SigBit Q = sigmap(cell->getPort(ID::Q).as_bit());
SigBit D = sigmap(cell->getPort(TW::D).as_bit());
SigBit Q = sigmap(cell->getPort(TW::Q).as_bit());
unused_bits.erase(D);
undriven_bits.erase(Q);
ff_map[Q] = D;
if (cell->type != ID($_FF_)) {
auto sig_clk = sigmap(cell->getPort(ID::C).as_bit());
auto sig_clk = sigmap(cell->getPort(TW::C).as_bit());
ywmap_clocks[sig_clk] |= cell->type == ID($_DFF_N_) ? 2 : 1;
}
continue;
@ -248,8 +248,8 @@ struct AigerWriter
if (cell->type == ID($anyinit))
{
auto sig_d = sigmap(cell->getPort(ID::D));
auto sig_q = sigmap(cell->getPort(ID::Q));
auto sig_d = sigmap(cell->getPort(TW::D));
auto sig_q = sigmap(cell->getPort(TW::Q));
for (int i = 0; i < sig_d.size(); i++) {
undriven_bits.erase(sig_q[i]);
ff_map[sig_q[i]] = sig_d[i];
@ -259,9 +259,9 @@ struct AigerWriter
if (cell->type == ID($_AND_))
{
SigBit A = sigmap(cell->getPort(ID::A).as_bit());
SigBit B = sigmap(cell->getPort(ID::B).as_bit());
SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit B = sigmap(cell->getPort(TW::B).as_bit());
SigBit Y = sigmap(cell->getPort(TW::Y).as_bit());
unused_bits.erase(A);
unused_bits.erase(B);
undriven_bits.erase(Y);
@ -271,7 +271,7 @@ struct AigerWriter
if (cell->type == ID($initstate))
{
SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
SigBit Y = sigmap(cell->getPort(TW::Y).as_bit());
undriven_bits.erase(Y);
initstate_bits.insert(Y);
continue;
@ -279,8 +279,8 @@ struct AigerWriter
if (cell->type == ID($assert))
{
SigBit A = sigmap(cell->getPort(ID::A).as_bit());
SigBit EN = sigmap(cell->getPort(ID::EN).as_bit());
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit EN = sigmap(cell->getPort(TW::EN).as_bit());
unused_bits.erase(A);
unused_bits.erase(EN);
asserts.push_back(make_pair(A, EN));
@ -290,8 +290,8 @@ struct AigerWriter
if (cell->type == ID($assume))
{
SigBit A = sigmap(cell->getPort(ID::A).as_bit());
SigBit EN = sigmap(cell->getPort(ID::EN).as_bit());
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit EN = sigmap(cell->getPort(TW::EN).as_bit());
unused_bits.erase(A);
unused_bits.erase(EN);
assumes.push_back(make_pair(A, EN));
@ -301,8 +301,8 @@ struct AigerWriter
if (cell->type == ID($live))
{
SigBit A = sigmap(cell->getPort(ID::A).as_bit());
SigBit EN = sigmap(cell->getPort(ID::EN).as_bit());
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit EN = sigmap(cell->getPort(TW::EN).as_bit());
unused_bits.erase(A);
unused_bits.erase(EN);
liveness.push_back(make_pair(A, EN));
@ -311,8 +311,8 @@ struct AigerWriter
if (cell->type == ID($fair))
{
SigBit A = sigmap(cell->getPort(ID::A).as_bit());
SigBit EN = sigmap(cell->getPort(ID::EN).as_bit());
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit EN = sigmap(cell->getPort(TW::EN).as_bit());
unused_bits.erase(A);
unused_bits.erase(EN);
fairness.push_back(make_pair(A, EN));
@ -321,7 +321,7 @@ struct AigerWriter
if (cell->type == ID($anyconst))
{
for (auto bit : sigmap(cell->getPort(ID::Y))) {
for (auto bit : sigmap(cell->getPort(TW::Y))) {
undriven_bits.erase(bit);
ff_map[bit] = bit;
}
@ -330,7 +330,7 @@ struct AigerWriter
if (cell->type == ID($anyseq))
{
for (auto bit : sigmap(cell->getPort(ID::Y))) {
for (auto bit : sigmap(cell->getPort(TW::Y))) {
undriven_bits.erase(bit);
input_bits.insert(bit);
}
@ -780,7 +780,7 @@ struct AigerWriter
SigSpec sig = sigmap(sig_qy);
if (cell->get_bool_attribute(ID(clk2fflogic)))
sig_qy = cell->getPort(ID::D); // For a clk2fflogic $_FF_ the named signal is the D input not the Q output
sig_qy = cell->getPort(TW::D); // For a clk2fflogic $_FF_ the named signal is the D input not the Q output
for (int i = 0; i < GetSize(sig_qy); i++) {
if (sig_qy[i].wire == nullptr || sig[i].wire == nullptr)

24
backends/aiger/xaiger.cc
View File

@ -193,8 +193,8 @@ struct XAigerWriter
if (!cell->has_keep_attr()) {
if (cell->type == ID($_NOT_))
{
SigBit A = sigmap(cell->getPort(ID::A).as_bit());
SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit Y = sigmap(cell->getPort(TW::Y).as_bit());
unused_bits.erase(A);
undriven_bits.erase(Y);
not_map[Y] = A;
@ -203,9 +203,9 @@ struct XAigerWriter
if (cell->type == ID($_AND_))
{
SigBit A = sigmap(cell->getPort(ID::A).as_bit());
SigBit B = sigmap(cell->getPort(ID::B).as_bit());
SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit B = sigmap(cell->getPort(TW::B).as_bit());
SigBit Y = sigmap(cell->getPort(TW::Y).as_bit());
unused_bits.erase(A);
unused_bits.erase(B);
undriven_bits.erase(Y);
@ -215,8 +215,8 @@ struct XAigerWriter
if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_)) && !cell->get_bool_attribute(ID::abc9_keep))
{
SigBit D = sigmap(cell->getPort(ID::D).as_bit());
SigBit Q = sigmap(cell->getPort(ID::Q).as_bit());
SigBit D = sigmap(cell->getPort(TW::D).as_bit());
SigBit Q = sigmap(cell->getPort(TW::Q).as_bit());
unused_bits.erase(D);
undriven_bits.erase(Q);
alias_map[Q] = D;
@ -413,7 +413,7 @@ struct XAigerWriter
}
for (auto cell : ff_list) {
const SigBit &q = sigmap(cell->getPort(ID::Q));
const SigBit &q = sigmap(cell->getPort(TW::Q));
aig_m++, aig_i++;
log_assert(!aig_map.count(q));
aig_map[q] = 2*aig_m;
@ -461,7 +461,7 @@ struct XAigerWriter
}
for (auto cell : ff_list) {
const SigBit &d = sigmap(cell->getPort(ID::D));
const SigBit &d = sigmap(cell->getPort(TW::D));
aig_o++;
aig_outputs.push_back(aig_map.at(d));
}
@ -605,10 +605,10 @@ struct XAigerWriter
dict<SigSpec, int> clk_to_mergeability;
for (const auto cell : ff_list) {
const SigBit &d = sigmap(cell->getPort(ID::D));
const SigBit &q = sigmap(cell->getPort(ID::Q));
const SigBit &d = sigmap(cell->getPort(TW::D));
const SigBit &q = sigmap(cell->getPort(TW::Q));
SigSpec clk_and_pol{sigmap(cell->getPort(ID::C)), cell->type[6] == 'P' ? State::S1 : State::S0};
SigSpec clk_and_pol{sigmap(cell->getPort(TW::C)), cell->type[6] == 'P' ? State::S1 : State::S0};
auto r = clk_to_mergeability.insert(std::make_pair(clk_and_pol, clk_to_mergeability.size()+1));
int mergeability = r.first->second;
log_assert(mergeability > 0);

46
backends/aiger2/aiger.cc
View File

@ -283,9 +283,9 @@ struct Index {
if (cell->type.in(REDUCE_OPS, LOGIC_OPS, CMP_OPS) && obit != 0) {
return CFALSE;
} else if (cell->type.in(CMP_OPS)) {
SigSpec aport = cell->getPort(ID::A);
SigSpec aport = cell->getPort(TW::A);
bool asigned = cell->getParam(ID::A_SIGNED).as_bool();
SigSpec bport = cell->getPort(ID::B);
SigSpec bport = cell->getPort(TW::B);
bool bsigned = cell->getParam(ID::B_SIGNED).as_bool();
int width = std::max(aport.size(), bport.size()) + 1;
@ -318,7 +318,7 @@ struct Index {
log_abort();
}
} else if (cell->type.in(REDUCE_OPS, ID($logic_not))) {
SigSpec inport = cell->getPort(ID::A);
SigSpec inport = cell->getPort(TW::A);
std::vector<Lit> lits;
for (int i = 0; i < inport.size(); i++) {
@ -339,8 +339,8 @@ struct Index {
else
return NOT(acc);
} else if (cell->type.in(ID($logic_and), ID($logic_or))) {
SigSpec aport = cell->getPort(ID::A);
SigSpec bport = cell->getPort(ID::B);
SigSpec aport = cell->getPort(TW::A);
SigSpec bport = cell->getPort(TW::B);
log_assert(aport.size() > 0 && bport.size() > 0); // TODO
@ -363,7 +363,7 @@ struct Index {
else
log_abort();
} else if (cell->type.in(BITWISE_OPS, GATE_OPS, ID($pos))) {
SigSpec aport = cell->getPort(ID::A);
SigSpec aport = cell->getPort(TW::A);
Lit a;
if (obit < aport.size()) {
a = visit(cursor, aport[obit]);
@ -379,7 +379,7 @@ struct Index {
} else if (cell->type.in(ID($not), ID($_NOT_))) {
return NOT(a);
} else {
SigSpec bport = cell->getPort(ID::B);
SigSpec bport = cell->getPort(TW::B);
Lit b;
if (obit < bport.size()) {
b = visit(cursor, bport[obit]);
@ -407,16 +407,16 @@ struct Index {
} else if (cell->type.in(ID($_ORNOT_))) {
return OR(a, NOT(b));
} else if (cell->type.in(ID($mux), ID($_MUX_))) {
Lit s = visit(cursor, cell->getPort(ID::S));
Lit s = visit(cursor, cell->getPort(TW::S));
return MUX(a, b, s);
} else if (cell->type.in(ID($bwmux))) {
Lit s = visit(cursor, cell->getPort(ID::S)[obit]);
Lit s = visit(cursor, cell->getPort(TW::S)[obit]);
return MUX(a, b, s);
} else if (cell->type.in(ID($_NMUX_))) {
Lit s = visit(cursor, cell->getPort(ID::S)[obit]);
Lit s = visit(cursor, cell->getPort(TW::S)[obit]);
return NOT(MUX(a, b, s));
} else if (cell->type.in(ID($fa))) {
Lit c = visit(cursor, cell->getPort(ID::C)[obit]);
Lit c = visit(cursor, cell->getPort(TW::C)[obit]);
Lit ab = XOR(a, b);
if (oport == ID::Y) {
return XOR(ab, c);
@ -428,9 +428,9 @@ struct Index {
} else if (cell->type.in(ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) {
Lit c, d;
c = visit(cursor, cell->getPort(ID::C)[obit]);
c = visit(cursor, cell->getPort(TW::C)[obit]);
if (/* 4 input types */ cell->type.in(ID($_AOI4_), ID($_OAI4_)))
d = visit(cursor, cell->getPort(ID::D)[obit]);
d = visit(cursor, cell->getPort(TW::D)[obit]);
else
d = cell->type == ID($_AOI3_) ? CTRUE : CFALSE;
@ -448,9 +448,9 @@ struct Index {
}
}
} else if (cell->type == ID($pmux)) {
SigSpec aport = cell->getPort(ID::A);
SigSpec bport = cell->getPort(ID::B);
SigSpec sport = cell->getPort(ID::S);
SigSpec aport = cell->getPort(TW::A);
SigSpec bport = cell->getPort(TW::B);
SigSpec sport = cell->getPort(TW::S);
int width = aport.size();
Lit a = visit(cursor, aport[obit]);
@ -469,8 +469,8 @@ struct Index {
return OR(reduce_sels_and_a, reduce_bar);
} else if (cell->type == ID($bmux)) {
SigSpec aport = cell->getPort(ID::A);
SigSpec sport = cell->getPort(ID::S);
SigSpec aport = cell->getPort(TW::A);
SigSpec sport = cell->getPort(TW::S);
int width = cell->getParam(ID::WIDTH).as_int();
std::vector<Lit> data;
@ -632,7 +632,7 @@ struct Index {
} else {
Module *def = cursor.enter(*this, driver);
{
IdString portname = bit.wire->driverPort();
TwineRef portname = bit.wire->driverPort();
Wire *w = def->wire(portname);
if (!w)
log_error("Output port %s on instance %s of %s doesn't exist\n",
@ -652,7 +652,7 @@ struct Index {
// step into the upper module
Cell *instance = cursor.exit(*this);
{
IdString portname = bit.wire->name;
TwineRef portname = bit.wire->name;
if (!instance->hasPort(portname))
log_error("Input port %s on instance %s of %s unconnected\n",
portname.unescape(), instance, instance->type);
@ -1134,7 +1134,7 @@ struct XAigerWriter : AigerWriter {
for (auto [cursor, box, def] : nonopaque_boxes) {
// use `def->name` not `box->type` as we want the derived type
Cell *holes_wb = holes_module->addCell(NEW_ID, def->name);
Cell *holes_wb = holes_module->addCell(NEW_TWINE, def->name);
int holes_pi_idx = 0;
if (map_file.is_open()) {
@ -1175,7 +1175,7 @@ struct XAigerWriter : AigerWriter {
SigSpec in_conn;
for (int i = 0; i < port->width; i++) {
while (holes_pi_idx >= (int) holes_pis.size()) {
Wire *w = holes_module->addWire(NEW_ID, 1);
Wire *w = holes_module->addWire(NEW_TWINE, 1);
w->port_input = true;
holes_module->ports.push_back(w->name);
holes_pis.push_back(w);
@ -1204,7 +1204,7 @@ struct XAigerWriter : AigerWriter {
boxes_ci_num += port->width;
// holes
Wire *w = holes_module->addWire(NEW_ID, port->width);
Wire *w = holes_module->addWire(NEW_TWINE, port->width);
w->port_output = true;
holes_module->ports.push_back(w->name);
holes_wb->setPort(port_id, w);

66
backends/blif/blif.cc
View File

@ -244,136 +244,136 @@ struct BlifDumper
if (!config->icells_mode && cell->type == ID($_NOT_)) {
f << stringf(".names %s %s\n0 1\n",
str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::Y)).c_str());
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_AND_)) {
f << stringf(".names %s %s %s\n11 1\n",
str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str());
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_OR_)) {
f << stringf(".names %s %s %s\n1- 1\n-1 1\n",
str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str());
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_XOR_)) {
f << stringf(".names %s %s %s\n10 1\n01 1\n",
str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str());
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_NAND_)) {
f << stringf(".names %s %s %s\n0- 1\n-0 1\n",
str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str());
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_NOR_)) {
f << stringf(".names %s %s %s\n00 1\n",
str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str());
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_XNOR_)) {
f << stringf(".names %s %s %s\n11 1\n00 1\n",
str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str());
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_ANDNOT_)) {
f << stringf(".names %s %s %s\n10 1\n",
str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str());
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_ORNOT_)) {
f << stringf(".names %s %s %s\n1- 1\n-0 1\n",
str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str());
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_AOI3_)) {
f << stringf(".names %s %s %s %s\n-00 1\n0-0 1\n",
str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::C)).c_str(), str(cell->getPort(ID::Y)).c_str());
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::C)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_OAI3_)) {
f << stringf(".names %s %s %s %s\n00- 1\n--0 1\n",
str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::C)).c_str(), str(cell->getPort(ID::Y)).c_str());
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::C)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_AOI4_)) {
f << stringf(".names %s %s %s %s %s\n-0-0 1\n-00- 1\n0--0 1\n0-0- 1\n",
str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(),
str(cell->getPort(ID::C)).c_str(), str(cell->getPort(ID::D)).c_str(), str(cell->getPort(ID::Y)).c_str());
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(),
str(cell->getPort(TW::C)).c_str(), str(cell->getPort(TW::D)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_OAI4_)) {
f << stringf(".names %s %s %s %s %s\n00-- 1\n--00 1\n",
str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(),
str(cell->getPort(ID::C)).c_str(), str(cell->getPort(ID::D)).c_str(), str(cell->getPort(ID::Y)).c_str());
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(),
str(cell->getPort(TW::C)).c_str(), str(cell->getPort(TW::D)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_MUX_)) {
f << stringf(".names %s %s %s %s\n1-0 1\n-11 1\n",
str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(),
str(cell->getPort(ID::S)).c_str(), str(cell->getPort(ID::Y)).c_str());
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(),
str(cell->getPort(TW::S)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_NMUX_)) {
f << stringf(".names %s %s %s %s\n0-0 1\n-01 1\n",
str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(),
str(cell->getPort(ID::S)).c_str(), str(cell->getPort(ID::Y)).c_str());
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(),
str(cell->getPort(TW::S)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_FF_)) {
f << stringf(".latch %s %s%s\n", str(cell->getPort(ID::D)), str(cell->getPort(ID::Q)),
str_init(cell->getPort(ID::Q)).c_str());
f << stringf(".latch %s %s%s\n", str(cell->getPort(TW::D)), str(cell->getPort(TW::Q)),
str_init(cell->getPort(TW::Q)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_DFF_N_)) {
f << stringf(".latch %s %s fe %s%s\n", str(cell->getPort(ID::D)), str(cell->getPort(ID::Q)),
str(cell->getPort(ID::C)).c_str(), str_init(cell->getPort(ID::Q)).c_str());
f << stringf(".latch %s %s fe %s%s\n", str(cell->getPort(TW::D)), str(cell->getPort(TW::Q)),
str(cell->getPort(TW::C)).c_str(), str_init(cell->getPort(TW::Q)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_DFF_P_)) {
f << stringf(".latch %s %s re %s%s\n", str(cell->getPort(ID::D)), str(cell->getPort(ID::Q)),
str(cell->getPort(ID::C)).c_str(), str_init(cell->getPort(ID::Q)).c_str());
f << stringf(".latch %s %s re %s%s\n", str(cell->getPort(TW::D)), str(cell->getPort(TW::Q)),
str(cell->getPort(TW::C)).c_str(), str_init(cell->getPort(TW::Q)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_DLATCH_N_)) {
f << stringf(".latch %s %s al %s%s\n", str(cell->getPort(ID::D)), str(cell->getPort(ID::Q)),
str(cell->getPort(ID::E)).c_str(), str_init(cell->getPort(ID::Q)).c_str());
f << stringf(".latch %s %s al %s%s\n", str(cell->getPort(TW::D)), str(cell->getPort(TW::Q)),
str(cell->getPort(TW::E)).c_str(), str_init(cell->getPort(TW::Q)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_DLATCH_P_)) {
f << stringf(".latch %s %s ah %s%s\n", str(cell->getPort(ID::D)), str(cell->getPort(ID::Q)),
str(cell->getPort(ID::E)).c_str(), str_init(cell->getPort(ID::Q)).c_str());
f << stringf(".latch %s %s ah %s%s\n", str(cell->getPort(TW::D)), str(cell->getPort(TW::Q)),
str(cell->getPort(TW::E)).c_str(), str_init(cell->getPort(TW::Q)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($lut)) {
f << stringf(".names");
auto &inputs = cell->getPort(ID::A);
auto &inputs = cell->getPort(TW::A);
auto width = cell->parameters.at(ID::WIDTH).as_int();
log_assert(inputs.size() == width);
for (int i = width-1; i >= 0; i--)
f << stringf(" %s", str(inputs.extract(i, 1)));
auto &output = cell->getPort(ID::Y);
auto &output = cell->getPort(TW::Y);
log_assert(output.size() == 1);
f << stringf(" %s", str(output));
f << stringf("\n");
@ -390,7 +390,7 @@ struct BlifDumper
if (!config->icells_mode && cell->type == ID($sop)) {
f << stringf(".names");
auto &inputs = cell->getPort(ID::A);
auto &inputs = cell->getPort(TW::A);
auto width = cell->parameters.at(ID::WIDTH).as_int();
auto depth = cell->parameters.at(ID::DEPTH).as_int();
vector<State> table = cell->parameters.at(ID::TABLE).to_bits();
@ -399,7 +399,7 @@ struct BlifDumper
log_assert(inputs.size() == width);
for (int i = 0; i < width; i++)
f << stringf(" %s", str(inputs.extract(i, 1)));
auto &output = cell->getPort(ID::Y);
auto &output = cell->getPort(TW::Y);
log_assert(output.size() == 1);
f << stringf(" %s", str(output));
f << stringf("\n");

118
backends/btor/btor.cc
View File

@ -271,8 +271,8 @@ struct BtorWorker
if (cell->type.in(ID($xnor), ID($_XNOR_))) btor_op = "xnor";
log_assert(!btor_op.empty());
int width_ay = std::max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::Y)));
int width = std::max(width_ay, GetSize(cell->getPort(ID::B)));
int width_ay = std::max(GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::Y)));
int width = std::max(width_ay, GetSize(cell->getPort(TW::B)));
bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false;
@ -292,17 +292,17 @@ struct BtorWorker
int nid_a;
if (cell->type.in(ID($shl), ID($shr), ID($shift), ID($shiftx)) && a_signed && width_ay < width) {
// sign-extend A up to the width of Y
int nid_a_padded = get_sig_nid(cell->getPort(ID::A), width_ay, a_signed);
int nid_a_padded = get_sig_nid(cell->getPort(TW::A), width_ay, a_signed);
// zero-extend the rest
int zeroes = get_sig_nid(Const(0, width-width_ay));
nid_a = next_nid++;
btorf("%d concat %d %d %d\n", nid_a, sid, zeroes, nid_a_padded);
} else {
nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
nid_a = get_sig_nid(cell->getPort(TW::A), width, a_signed);
}
int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed);
int nid_b = get_sig_nid(cell->getPort(TW::B), width, b_signed);
if (btor_op == "shift")
{
@ -329,7 +329,7 @@ struct BtorWorker
btorf("%d %s %d %d %d%s\n", nid, btor_op, sid, nid_a, nid_b, getinfo(cell));
}
SigSpec sig = sigmap(cell->getPort(ID::Y));
SigSpec sig = sigmap(cell->getPort(TW::Y));
if (GetSize(sig) < width) {
int sid = get_bv_sid(GetSize(sig));
@ -358,18 +358,18 @@ struct BtorWorker
}
log_assert(!btor_op.empty());
int width = GetSize(cell->getPort(ID::Y));
width = std::max(width, GetSize(cell->getPort(ID::A)));
width = std::max(width, GetSize(cell->getPort(ID::B)));
int width = GetSize(cell->getPort(TW::Y));
width = std::max(width, GetSize(cell->getPort(TW::A)));
width = std::max(width, GetSize(cell->getPort(TW::B)));
int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed);
int nid_a = get_sig_nid(cell->getPort(TW::A), width, a_signed);
int nid_b = get_sig_nid(cell->getPort(TW::B), width, b_signed);
int sid = get_bv_sid(width);
int nid = next_nid++;
btorf("%d %c%s %d %d %d%s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op, sid, nid_a, nid_b, getinfo(cell));
SigSpec sig = sigmap(cell->getPort(ID::Y));
SigSpec sig = sigmap(cell->getPort(TW::Y));
if (GetSize(sig) < width) {
int sid = get_bv_sid(GetSize(sig));
@ -385,8 +385,8 @@ struct BtorWorker
if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
{
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A));
int nid_b = get_sig_nid(cell->getPort(ID::B));
int nid_a = get_sig_nid(cell->getPort(TW::A));
int nid_b = get_sig_nid(cell->getPort(TW::B));
int nid1 = next_nid++;
int nid2 = next_nid++;
@ -401,7 +401,7 @@ struct BtorWorker
btorf("%d or %d %d %d%s\n", nid2, sid, nid_a, nid1, getinfo(cell));
}
SigSpec sig = sigmap(cell->getPort(ID::Y));
SigSpec sig = sigmap(cell->getPort(TW::Y));
add_nid_sig(nid2, sig);
goto okay;
}
@ -409,9 +409,9 @@ struct BtorWorker
if (cell->type.in(ID($_OAI3_), ID($_AOI3_)))
{
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A));
int nid_b = get_sig_nid(cell->getPort(ID::B));
int nid_c = get_sig_nid(cell->getPort(ID::C));
int nid_a = get_sig_nid(cell->getPort(TW::A));
int nid_b = get_sig_nid(cell->getPort(TW::B));
int nid_c = get_sig_nid(cell->getPort(TW::C));
int nid1 = next_nid++;
int nid2 = next_nid++;
@ -429,7 +429,7 @@ struct BtorWorker
btorf("%d not %d %d%s\n", nid3, sid, nid2, getinfo(cell));
}
SigSpec sig = sigmap(cell->getPort(ID::Y));
SigSpec sig = sigmap(cell->getPort(TW::Y));
add_nid_sig(nid3, sig);
goto okay;
}
@ -437,10 +437,10 @@ struct BtorWorker
if (cell->type.in(ID($_OAI4_), ID($_AOI4_)))
{
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A));
int nid_b = get_sig_nid(cell->getPort(ID::B));
int nid_c = get_sig_nid(cell->getPort(ID::C));
int nid_d = get_sig_nid(cell->getPort(ID::D));
int nid_a = get_sig_nid(cell->getPort(TW::A));
int nid_b = get_sig_nid(cell->getPort(TW::B));
int nid_c = get_sig_nid(cell->getPort(TW::C));
int nid_d = get_sig_nid(cell->getPort(TW::D));
int nid1 = next_nid++;
int nid2 = next_nid++;
@ -461,7 +461,7 @@ struct BtorWorker
btorf("%d not %d %d%s\n", nid4, sid, nid3, getinfo(cell));
}
SigSpec sig = sigmap(cell->getPort(ID::Y));
SigSpec sig = sigmap(cell->getPort(TW::Y));
add_nid_sig(nid4, sig);
goto okay;
}
@ -478,15 +478,15 @@ struct BtorWorker
log_assert(!btor_op.empty());
int width = 1;
width = std::max(width, GetSize(cell->getPort(ID::A)));
width = std::max(width, GetSize(cell->getPort(ID::B)));
width = std::max(width, GetSize(cell->getPort(TW::A)));
width = std::max(width, GetSize(cell->getPort(TW::B)));
bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false;
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed);
int nid_a = get_sig_nid(cell->getPort(TW::A), width, a_signed);
int nid_b = get_sig_nid(cell->getPort(TW::B), width, b_signed);
int nid = next_nid++;
if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt))) {
@ -495,7 +495,7 @@ struct BtorWorker
btorf("%d %s %d %d %d%s\n", nid, btor_op, sid, nid_a, nid_b, getinfo(cell));
}
SigSpec sig = sigmap(cell->getPort(ID::Y));
SigSpec sig = sigmap(cell->getPort(TW::Y));
if (GetSize(sig) > 1) {
int sid = get_bv_sid(GetSize(sig));
@ -514,11 +514,11 @@ struct BtorWorker
if (cell->type.in(ID($not), ID($_NOT_))) btor_op = "not";
if (cell->type == ID($neg)) btor_op = "neg";
int width = std::max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::Y)));
int width = std::max(GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::Y)));
bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
SigSpec sig = sigmap(cell->getPort(ID::Y));
int nid_a = get_sig_nid(cell->getPort(TW::A), width, a_signed);
SigSpec sig = sigmap(cell->getPort(TW::Y));
// the $pos/$buf cells just pass through, all other cells need an actual operation applied
int nid = nid_a;
@ -550,16 +550,16 @@ struct BtorWorker
log_assert(!btor_op.empty());
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A));
int nid_b = btor_op != "not" ? get_sig_nid(cell->getPort(ID::B)) : 0;
int nid_a = get_sig_nid(cell->getPort(TW::A));
int nid_b = btor_op != "not" ? get_sig_nid(cell->getPort(TW::B)) : 0;
if (GetSize(cell->getPort(ID::A)) > 1) {
if (GetSize(cell->getPort(TW::A)) > 1) {
int nid_red_a = next_nid++;
btorf("%d redor %d %d\n", nid_red_a, sid, nid_a);
nid_a = nid_red_a;
}
if (btor_op != "not" && GetSize(cell->getPort(ID::B)) > 1) {
if (btor_op != "not" && GetSize(cell->getPort(TW::B)) > 1) {
int nid_red_b = next_nid++;
btorf("%d redor %d %d\n", nid_red_b, sid, nid_b);
nid_b = nid_red_b;
@ -571,7 +571,7 @@ struct BtorWorker
else
btorf("%d %s %d %d%s\n", nid, btor_op, sid, nid_a, getinfo(cell));
SigSpec sig = sigmap(cell->getPort(ID::Y));
SigSpec sig = sigmap(cell->getPort(TW::Y));
if (GetSize(sig) > 1) {
int sid = get_bv_sid(GetSize(sig));
@ -594,7 +594,7 @@ struct BtorWorker
log_assert(!btor_op.empty());
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A));
int nid_a = get_sig_nid(cell->getPort(TW::A));
int nid = next_nid++;
@ -607,7 +607,7 @@ struct BtorWorker
btorf("%d %s %d %d%s\n", nid, btor_op, sid, nid_a, getinfo(cell));
}
SigSpec sig = sigmap(cell->getPort(ID::Y));
SigSpec sig = sigmap(cell->getPort(TW::Y));
if (GetSize(sig) > 1) {
int sid = get_bv_sid(GetSize(sig));
@ -623,10 +623,10 @@ struct BtorWorker
if (cell->type.in(ID($mux), ID($_MUX_), ID($_NMUX_)))
{
SigSpec sig_a = sigmap(cell->getPort(ID::A));
SigSpec sig_b = sigmap(cell->getPort(ID::B));
SigSpec sig_s = sigmap(cell->getPort(ID::S));
SigSpec sig_y = sigmap(cell->getPort(ID::Y));
SigSpec sig_a = sigmap(cell->getPort(TW::A));
SigSpec sig_b = sigmap(cell->getPort(TW::B));
SigSpec sig_s = sigmap(cell->getPort(TW::S));
SigSpec sig_y = sigmap(cell->getPort(TW::Y));
int nid_a = get_sig_nid(sig_a);
int nid_b = get_sig_nid(sig_b);
@ -650,10 +650,10 @@ struct BtorWorker
if (cell->type == ID($pmux))
{
SigSpec sig_a = sigmap(cell->getPort(ID::A));
SigSpec sig_b = sigmap(cell->getPort(ID::B));
SigSpec sig_s = sigmap(cell->getPort(ID::S));
SigSpec sig_y = sigmap(cell->getPort(ID::Y));
SigSpec sig_a = sigmap(cell->getPort(TW::A));
SigSpec sig_b = sigmap(cell->getPort(TW::B));
SigSpec sig_s = sigmap(cell->getPort(TW::S));
SigSpec sig_y = sigmap(cell->getPort(TW::Y));
int width = GetSize(sig_a);
int sid = get_bv_sid(width);
@ -676,8 +676,8 @@ struct BtorWorker
if (cell->type.in(ID($dff), ID($ff), ID($anyinit), ID($_DFF_P_), ID($_DFF_N), ID($_FF_)))
{
SigSpec sig_d = sigmap(cell->getPort(ID::D));
SigSpec sig_q = sigmap(cell->getPort(ID::Q));
SigSpec sig_d = sigmap(cell->getPort(TW::D));
SigSpec sig_q = sigmap(cell->getPort(TW::Q));
if ((!info_filename.empty() || ywmap_json.active()) && cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_)))
{
@ -730,7 +730,7 @@ struct BtorWorker
btorf("%d state %d %s\n", nid, sid, symbol.unescape());
if (cell->get_bool_attribute(ID(clk2fflogic)))
ywmap_state(cell->getPort(ID::D)); // For a clk2fflogic FF the named signal is the D input not the Q output
ywmap_state(cell->getPort(TW::D)); // For a clk2fflogic FF the named signal is the D input not the Q output
else
ywmap_state(sig_q);
@ -748,7 +748,7 @@ struct BtorWorker
if (cell->type.in(ID($anyconst), ID($anyseq)))
{
SigSpec sig_y = sigmap(cell->getPort(ID::Y));
SigSpec sig_y = sigmap(cell->getPort(TW::Y));
int sid = get_bv_sid(GetSize(sig_y));
int nid = next_nid++;
@ -768,7 +768,7 @@ struct BtorWorker
if (cell->type == ID($initstate))
{
SigSpec sig_y = sigmap(cell->getPort(ID::Y));
SigSpec sig_y = sigmap(cell->getPort(TW::Y));
if (initstate_nid < 0)
{
@ -1272,8 +1272,8 @@ struct BtorWorker
btorf_push(cell->name.unescape());
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A));
int nid_en = get_sig_nid(cell->getPort(ID::EN));
int nid_a = get_sig_nid(cell->getPort(TW::A));
int nid_en = get_sig_nid(cell->getPort(TW::EN));
int nid_not_en = next_nid++;
int nid_a_or_not_en = next_nid++;
int nid = next_nid++;
@ -1292,8 +1292,8 @@ struct BtorWorker
btorf_push(cell->name.unescape());
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A));
int nid_en = get_sig_nid(cell->getPort(ID::EN));
int nid_a = get_sig_nid(cell->getPort(TW::A));
int nid_en = get_sig_nid(cell->getPort(TW::EN));
int nid_not_a = next_nid++;
int nid_en_and_not_a = next_nid++;
@ -1321,8 +1321,8 @@ struct BtorWorker
btorf_push(cell->name.unescape());
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A));
int nid_en = get_sig_nid(cell->getPort(ID::EN));
int nid_a = get_sig_nid(cell->getPort(TW::A));
int nid_en = get_sig_nid(cell->getPort(TW::EN));
int nid_en_and_a = next_nid++;
btorf("%d and %d %d %d\n", nid_en_and_a, sid, nid_en, nid_a);
@ -1372,7 +1372,7 @@ struct BtorWorker
btorf_push(stringf("next %s", cell));
SigSpec sig = sigmap(cell->getPort(ID::D));
SigSpec sig = sigmap(cell->getPort(TW::D));
int nid_q = get_sig_nid(sig);
int sid = get_bv_sid(GetSize(sig));
btorf("%d next %d %d %d%s\n", next_nid++, sid, nid, nid_q, getinfo(cell));

116
backends/cxxrtl/cxxrtl_backend.cc
View File

@ -243,7 +243,7 @@ enum class CxxrtlPortType {
SYNC = 2,
};
CxxrtlPortType cxxrtl_port_type(RTLIL::Module *module, RTLIL::IdString port)
CxxrtlPortType cxxrtl_port_type(RTLIL::Module *module, TwineRef port)
{
RTLIL::Wire *output_wire = module->wire(port);
log_assert(output_wire != nullptr);
@ -259,7 +259,7 @@ CxxrtlPortType cxxrtl_port_type(RTLIL::Module *module, RTLIL::IdString port)
return CxxrtlPortType::UNKNOWN;
}
CxxrtlPortType cxxrtl_port_type(const RTLIL::Cell *cell, RTLIL::IdString port)
CxxrtlPortType cxxrtl_port_type(const RTLIL::Cell *cell, TwineRef port)
{
RTLIL::Module *cell_module = cell->module->design->module(cell->type);
if (cell_module == nullptr || !cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
@ -267,12 +267,12 @@ CxxrtlPortType cxxrtl_port_type(const RTLIL::Cell *cell, RTLIL::IdString port)
return cxxrtl_port_type(cell_module, port);
}
bool is_cxxrtl_comb_port(const RTLIL::Cell *cell, RTLIL::IdString port)
bool is_cxxrtl_comb_port(const RTLIL::Cell *cell, TwineRef port)
{
return cxxrtl_port_type(cell, port) == CxxrtlPortType::COMB;
}
bool is_cxxrtl_sync_port(const RTLIL::Cell *cell, RTLIL::IdString port)
bool is_cxxrtl_sync_port(const RTLIL::Cell *cell, TwineRef port)
{
return cxxrtl_port_type(cell, port) == CxxrtlPortType::SYNC;
}
@ -1139,7 +1139,7 @@ struct CxxrtlWorker {
if (is_extending_cell(cell->type))
f << '_' << (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u');
f << "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">(";
dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
dump_sigspec_rhs(cell->getPort(TW::A), for_debug);
f << ")";
// Binary cells
} else if (is_binary_cell(cell->type)) {
@ -1148,18 +1148,18 @@ struct CxxrtlWorker {
f << '_' << (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u') <<
(cell->getParam(ID::B_SIGNED).as_bool() ? 's' : 'u');
f << "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">(";
dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
dump_sigspec_rhs(cell->getPort(TW::A), for_debug);
f << ", ";
dump_sigspec_rhs(cell->getPort(ID::B), for_debug);
dump_sigspec_rhs(cell->getPort(TW::B), for_debug);
f << ")";
// Muxes
} else if (cell->type == ID($mux)) {
f << "(";
dump_sigspec_rhs(cell->getPort(ID::S), for_debug);
dump_sigspec_rhs(cell->getPort(TW::S), for_debug);
f << " ? ";
dump_sigspec_rhs(cell->getPort(ID::B), for_debug);
dump_sigspec_rhs(cell->getPort(TW::B), for_debug);
f << " : ";
dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
dump_sigspec_rhs(cell->getPort(TW::A), for_debug);
f << ")";
// Parallel (one-hot) muxes
} else if (cell->type == ID($pmux)) {
@ -1167,48 +1167,48 @@ struct CxxrtlWorker {
int s_width = cell->getParam(ID::S_WIDTH).as_int();
for (int part = 0; part < s_width; part++) {
f << "(";
dump_sigspec_rhs(cell->getPort(ID::S).extract(part), for_debug);
dump_sigspec_rhs(cell->getPort(TW::S).extract(part), for_debug);
f << " ? ";
dump_sigspec_rhs(cell->getPort(ID::B).extract(part * width, width), for_debug);
dump_sigspec_rhs(cell->getPort(TW::B).extract(part * width, width), for_debug);
f << " : ";
}
dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
dump_sigspec_rhs(cell->getPort(TW::A), for_debug);
for (int part = 0; part < s_width; part++) {
f << ")";
}
// Big muxes
} else if (cell->type == ID($bmux)) {
dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
dump_sigspec_rhs(cell->getPort(TW::A), for_debug);
f << ".bmux<";
f << cell->getParam(ID::WIDTH).as_int();
f << ">(";
dump_sigspec_rhs(cell->getPort(ID::S), for_debug);
dump_sigspec_rhs(cell->getPort(TW::S), for_debug);
f << ").val()";
// Bitwise muxes
} else if (cell->type == ID($bwmux)) {
dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
dump_sigspec_rhs(cell->getPort(TW::A), for_debug);
f << ".bwmux(";
dump_sigspec_rhs(cell->getPort(ID::B), for_debug);
dump_sigspec_rhs(cell->getPort(TW::B), for_debug);
f << ",";
dump_sigspec_rhs(cell->getPort(ID::S), for_debug);
dump_sigspec_rhs(cell->getPort(TW::S), for_debug);
f << ").val()";
// Demuxes
} else if (cell->type == ID($demux)) {
dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
dump_sigspec_rhs(cell->getPort(TW::A), for_debug);
f << ".demux<";
f << GetSize(cell->getPort(ID::Y));
f << GetSize(cell->getPort(TW::Y));
f << ">(";
dump_sigspec_rhs(cell->getPort(ID::S), for_debug);
dump_sigspec_rhs(cell->getPort(TW::S), for_debug);
f << ").val()";
// Concats
} else if (cell->type == ID($concat)) {
dump_sigspec_rhs(cell->getPort(ID::B), for_debug);
dump_sigspec_rhs(cell->getPort(TW::B), for_debug);
f << ".concat(";
dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
dump_sigspec_rhs(cell->getPort(TW::A), for_debug);
f << ").val()";
// Slices
} else if (cell->type == ID($slice)) {
dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
dump_sigspec_rhs(cell->getPort(TW::A), for_debug);
f << ".slice<";
f << cell->getParam(ID::OFFSET).as_int() + cell->getParam(ID::Y_WIDTH).as_int() - 1;
f << ",";
@ -1225,7 +1225,7 @@ struct CxxrtlWorker {
fmt.parse_rtlil(cell);
f << indent << "if (";
dump_sigspec_rhs(cell->getPort(ID::EN));
dump_sigspec_rhs(cell->getPort(TW::EN));
f << " == value<1>{1u}) {\n";
inc_indent();
dict<std::string, RTLIL::SigSpec> fmt_args;
@ -1277,7 +1277,7 @@ struct CxxrtlWorker {
fmt.parse_rtlil(cell);
f << indent << "if (";
dump_sigspec_rhs(cell->getPort(ID::EN));
dump_sigspec_rhs(cell->getPort(TW::EN));
f << ") {\n";
inc_indent();
dict<std::string, RTLIL::SigSpec> fmt_args;
@ -1309,7 +1309,7 @@ struct CxxrtlWorker {
}
if (cell->hasPort(ID::A)) {
f << indent << "bool condition = (bool)";
dump_sigspec_rhs(cell->getPort(ID::A));
dump_sigspec_rhs(cell->getPort(TW::A));
f << ";\n";
}
f << indent << "if (performer) {\n";
@ -1366,7 +1366,7 @@ struct CxxrtlWorker {
// Elidable cells
if (is_inlinable_cell(cell->type)) {
f << indent;
dump_sigspec_lhs(cell->getPort(ID::Y), for_debug);
dump_sigspec_lhs(cell->getPort(TW::Y), for_debug);
f << " = ";
dump_cell_expr(cell, for_debug);
f << ";\n";
@ -1379,12 +1379,12 @@ struct CxxrtlWorker {
if (!cell->getParam(ID::TRG_ENABLE).as_bool()) { // async effectful cell
f << indent << "auto " << mangle(cell) << "_next = ";
dump_sigspec_rhs(cell->getPort(ID::EN));
dump_sigspec_rhs(cell->getPort(TW::EN));
f << ".concat(";
if (cell->type == ID($print))
dump_sigspec_rhs(cell->getPort(ID::ARGS));
dump_sigspec_rhs(cell->getPort(TW::ARGS));
else if (cell->type == ID($check))
dump_sigspec_rhs(cell->getPort(ID::A));
dump_sigspec_rhs(cell->getPort(TW::A));
else log_assert(false);
f << ").val();\n";
@ -1406,9 +1406,9 @@ struct CxxrtlWorker {
} else if (is_ff_cell(cell->type)) {
log_assert(!for_debug);
// Clocks might be slices of larger signals but should only ever be single bit
if (cell->hasPort(ID::CLK) && is_valid_clock(cell->getPort(ID::CLK))) {
if (cell->hasPort(ID::CLK) && is_valid_clock(cell->getPort(TW::CLK))) {
// Edge-sensitive logic
RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0];
RTLIL::SigBit clk_bit = cell->getPort(TW::CLK)[0];
clk_bit = sigmaps[clk_bit.wire->module](clk_bit);
if (clk_bit.wire) {
f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
@ -1419,14 +1419,14 @@ struct CxxrtlWorker {
inc_indent();
if (cell->hasPort(ID::EN)) {
f << indent << "if (";
dump_sigspec_rhs(cell->getPort(ID::EN));
dump_sigspec_rhs(cell->getPort(TW::EN));
f << " == value<1> {" << cell->getParam(ID::EN_POLARITY).as_bool() << "u}) {\n";
inc_indent();
}
f << indent;
dump_sigspec_lhs(cell->getPort(ID::Q));
dump_sigspec_lhs(cell->getPort(TW::Q));
f << " = ";
dump_sigspec_rhs(cell->getPort(ID::D));
dump_sigspec_rhs(cell->getPort(TW::D));
f << ";\n";
if (cell->hasPort(ID::EN) && cell->type != ID($sdffce)) {
dec_indent();
@ -1434,11 +1434,11 @@ struct CxxrtlWorker {
}
if (cell->hasPort(ID::SRST)) {
f << indent << "if (";
dump_sigspec_rhs(cell->getPort(ID::SRST));
dump_sigspec_rhs(cell->getPort(TW::SRST));
f << " == value<1> {" << cell->getParam(ID::SRST_POLARITY).as_bool() << "u}) {\n";
inc_indent();
f << indent;
dump_sigspec_lhs(cell->getPort(ID::Q));
dump_sigspec_lhs(cell->getPort(TW::Q));
f << " = ";
dump_const(cell->getParam(ID::SRST_VALUE));
f << ";\n";
@ -1454,13 +1454,13 @@ struct CxxrtlWorker {
} else if (cell->hasPort(ID::EN)) {
// Level-sensitive logic
f << indent << "if (";
dump_sigspec_rhs(cell->getPort(ID::EN));
dump_sigspec_rhs(cell->getPort(TW::EN));
f << " == value<1> {" << cell->getParam(ID::EN_POLARITY).as_bool() << "u}) {\n";
inc_indent();
f << indent;
dump_sigspec_lhs(cell->getPort(ID::Q));
dump_sigspec_lhs(cell->getPort(TW::Q));
f << " = ";
dump_sigspec_rhs(cell->getPort(ID::D));
dump_sigspec_rhs(cell->getPort(TW::D));
f << ";\n";
dec_indent();
f << indent << "}\n";
@ -1468,11 +1468,11 @@ struct CxxrtlWorker {
if (cell->hasPort(ID::ARST)) {
// Asynchronous reset (entire coarse cell at once)
f << indent << "if (";
dump_sigspec_rhs(cell->getPort(ID::ARST));
dump_sigspec_rhs(cell->getPort(TW::ARST));
f << " == value<1> {" << cell->getParam(ID::ARST_POLARITY).as_bool() << "u}) {\n";
inc_indent();
f << indent;
dump_sigspec_lhs(cell->getPort(ID::Q));
dump_sigspec_lhs(cell->getPort(TW::Q));
f << " = ";
dump_const(cell->getParam(ID::ARST_VALUE));
f << ";\n";
@ -1482,13 +1482,13 @@ struct CxxrtlWorker {
if (cell->hasPort(ID::ALOAD)) {
// Asynchronous load
f << indent << "if (";
dump_sigspec_rhs(cell->getPort(ID::ALOAD));
dump_sigspec_rhs(cell->getPort(TW::ALOAD));
f << " == value<1> {" << cell->getParam(ID::ALOAD_POLARITY).as_bool() << "u}) {\n";
inc_indent();
f << indent;
dump_sigspec_lhs(cell->getPort(ID::Q));
dump_sigspec_lhs(cell->getPort(TW::Q));
f << " = ";
dump_sigspec_rhs(cell->getPort(ID::AD));
dump_sigspec_rhs(cell->getPort(TW::AD));
f << ";\n";
dec_indent();
f << indent << "}\n";
@ -1496,25 +1496,25 @@ struct CxxrtlWorker {
if (cell->hasPort(ID::SET)) {
// Asynchronous set (for individual bits)
f << indent;
dump_sigspec_lhs(cell->getPort(ID::Q));
dump_sigspec_lhs(cell->getPort(TW::Q));
f << " = ";
dump_sigspec_rhs(cell->getPort(ID::Q));
dump_sigspec_rhs(cell->getPort(TW::Q));
f << ".update(";
dump_const(RTLIL::Const(RTLIL::S1, cell->getParam(ID::WIDTH).as_int()));
f << ", ";
dump_sigspec_rhs(cell->getPort(ID::SET));
dump_sigspec_rhs(cell->getPort(TW::SET));
f << (cell->getParam(ID::SET_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n";
}
if (cell->hasPort(ID::CLR)) {
// Asynchronous clear (for individual bits; priority over set)
f << indent;
dump_sigspec_lhs(cell->getPort(ID::Q));
dump_sigspec_lhs(cell->getPort(TW::Q));
f << " = ";
dump_sigspec_rhs(cell->getPort(ID::Q));
dump_sigspec_rhs(cell->getPort(TW::Q));
f << ".update(";
dump_const(RTLIL::Const(RTLIL::S0, cell->getParam(ID::WIDTH).as_int()));
f << ", ";
dump_sigspec_rhs(cell->getPort(ID::CLR));
dump_sigspec_rhs(cell->getPort(TW::CLR));
f << (cell->getParam(ID::CLR_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n";
}
// Internal cells
@ -1788,7 +1788,7 @@ struct CxxrtlWorker {
void dump_cell_effect_sync(std::vector<const RTLIL::Cell*> &cells)
{
log_assert(!cells.empty());
const auto &trg = cells[0]->getPort(ID::TRG);
const auto &trg = cells[0]->getPort(TW::TRG);
const auto &trg_polarity = cells[0]->getParam(ID::TRG_POLARITY);
f << indent << "if (";
@ -1813,7 +1813,7 @@ struct CxxrtlWorker {
});
for (auto cell : cells) {
log_assert(cell->getParam(ID::TRG_ENABLE).as_bool());
log_assert(cell->getPort(ID::TRG) == trg);
log_assert(cell->getPort(TW::TRG) == trg);
log_assert(cell->getParam(ID::TRG_POLARITY) == trg_polarity);
std::vector<const RTLIL::Cell*> inlined_cells;
@ -2999,15 +2999,15 @@ struct CxxrtlWorker {
// Various DFF cells are treated like posedge/negedge processes, see above for details.
if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($dffsr), ID($dffsre), ID($sdff), ID($sdffe), ID($sdffce))) {
if (is_valid_clock(cell->getPort(ID::CLK)))
register_edge_signal(sigmap, cell->getPort(ID::CLK),
if (is_valid_clock(cell->getPort(TW::CLK)))
register_edge_signal(sigmap, cell->getPort(TW::CLK),
cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);
}
// Effectful cells may be triggered on posedge/negedge events.
if (is_effectful_cell(cell->type) && cell->getParam(ID::TRG_ENABLE).as_bool()) {
for (size_t i = 0; i < (size_t)cell->getParam(ID::TRG_WIDTH).as_int(); i++) {
RTLIL::SigBit trg = cell->getPort(ID::TRG).extract(i, 1);
RTLIL::SigBit trg = cell->getPort(TW::TRG).extract(i, 1);
if (is_valid_clock(trg))
register_edge_signal(sigmap, trg,
cell->parameters[ID::TRG_POLARITY][i] == RTLIL::S1 ? RTLIL::STp : RTLIL::STn);
@ -3216,7 +3216,7 @@ struct CxxrtlWorker {
is_effectful_cell(node->cell->type) &&
node->cell->getParam(ID::TRG_ENABLE).as_bool() &&
node->cell->getParam(ID::TRG_WIDTH).as_int() != 0)
effect_sync_cells[make_pair(node->cell->getPort(ID::TRG), node->cell->getParam(ID::TRG_POLARITY))].push_back(node->cell);
effect_sync_cells[make_pair(node->cell->getPort(TW::TRG), node->cell->getParam(ID::TRG_POLARITY))].push_back(node->cell);
else
schedule[module].push_back(*node);
}

48
backends/firrtl/firrtl.cc
View File

@ -601,7 +601,7 @@ struct FirrtlWorker
if (cell->type.in(ID($not), ID($logic_not), ID($_NOT_), ID($neg), ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_bool), ID($reduce_xnor)))
{
string a_expr = make_expr(cell->getPort(ID::A));
string a_expr = make_expr(cell->getPort(TW::A));
wire_decls.push_back(stringf("%swire %s: UInt<%d> %s\n", indent, y_id, y_width, cellFileinfo));
if (a_signed) {
@ -643,7 +643,7 @@ struct FirrtlWorker
expr = stringf("asUInt(%s)", expr);
cell_exprs.push_back(stringf("%s%s <= %s %s\n", indent, y_id, expr, cellFileinfo));
register_reverse_wire_map(y_id, cell->getPort(ID::Y));
register_reverse_wire_map(y_id, cell->getPort(TW::Y));
continue;
}
@ -651,8 +651,8 @@ struct FirrtlWorker
ID($gt), ID($ge), ID($lt), ID($le), ID($ne), ID($nex), ID($shr), ID($sshr), ID($sshl), ID($shl),
ID($logic_and), ID($logic_or), ID($pow)))
{
string a_expr = make_expr(cell->getPort(ID::A));
string b_expr = make_expr(cell->getPort(ID::B));
string a_expr = make_expr(cell->getPort(TW::A));
string b_expr = make_expr(cell->getPort(TW::B));
std::string cellFileinfo = getFileinfo(cell);
wire_decls.push_back(stringf("%swire %s: UInt<%d> %s\n", indent, y_id, y_width, cellFileinfo));
@ -690,7 +690,7 @@ struct FirrtlWorker
}
// Assume the FIRRTL width is the width of "A"
firrtl_width = a_width;
auto a_sig = cell->getPort(ID::A);
auto a_sig = cell->getPort(TW::A);
if (cell->type == ID($add)) {
primop = "add";
@ -769,7 +769,7 @@ struct FirrtlWorker
// We'll need to offset this by extracting the un-widened portion as Verilog would do.
extract_y_bits = true;
// Is the shift amount constant?
auto b_sig = cell->getPort(ID::B);
auto b_sig = cell->getPort(TW::B);
if (b_sig.is_fully_const()) {
primop = "shl";
int shift_amount = b_sig.as_int();
@ -786,7 +786,7 @@ struct FirrtlWorker
// We don't need to extract a specific range of bits.
extract_y_bits = false;
// Is the shift amount constant?
auto b_sig = cell->getPort(ID::B);
auto b_sig = cell->getPort(TW::B);
if (b_sig.is_fully_const()) {
primop = "shr";
int shift_amount = b_sig.as_int();
@ -828,7 +828,7 @@ struct FirrtlWorker
a_expr = firrtl_is_signed ? "SInt(1)" : "UInt(1)";
extract_y_bits = true;
// Is the shift amount constant?
auto b_sig = cell->getPort(ID::B);
auto b_sig = cell->getPort(TW::B);
if (b_sig.is_fully_const()) {
primop = "shl";
int shiftAmount = b_sig.as_int();
@ -873,7 +873,7 @@ struct FirrtlWorker
expr = stringf("asUInt(%s)", expr);
cell_exprs.push_back(stringf("%s%s <= %s %s\n", indent, y_id, expr, cellFileinfo));
register_reverse_wire_map(y_id, cell->getPort(ID::Y));
register_reverse_wire_map(y_id, cell->getPort(TW::Y));
continue;
}
@ -882,15 +882,15 @@ struct FirrtlWorker
{
auto it = cell->parameters.find(ID::WIDTH);
int width = it == cell->parameters.end()? 1 : it->second.as_int();
string a_expr = make_expr(cell->getPort(ID::A));
string b_expr = make_expr(cell->getPort(ID::B));
string s_expr = make_expr(cell->getPort(ID::S));
string a_expr = make_expr(cell->getPort(TW::A));
string b_expr = make_expr(cell->getPort(TW::B));
string s_expr = make_expr(cell->getPort(TW::S));
wire_decls.push_back(stringf("%swire %s: UInt<%d> %s\n", indent, y_id, width, cellFileinfo));
string expr = stringf("mux(%s, %s, %s)", s_expr, b_expr, a_expr);
cell_exprs.push_back(stringf("%s%s <= %s %s\n", indent, y_id, expr, cellFileinfo));
register_reverse_wire_map(y_id, cell->getPort(ID::Y));
register_reverse_wire_map(y_id, cell->getPort(TW::Y));
continue;
}
@ -908,13 +908,13 @@ struct FirrtlWorker
log_error("Negative edge clock on FF %s.%s.\n", module, cell);
int width = cell->parameters.at(ID::WIDTH).as_int();
string expr = make_expr(cell->getPort(ID::D));
string clk_expr = "asClock(" + make_expr(cell->getPort(ID::CLK)) + ")";
string expr = make_expr(cell->getPort(TW::D));
string clk_expr = "asClock(" + make_expr(cell->getPort(TW::CLK)) + ")";
wire_decls.push_back(stringf("%sreg %s: UInt<%d>, %s %s\n", indent, y_id, width, clk_expr, cellFileinfo));
cell_exprs.push_back(stringf("%s%s <= %s %s\n", indent, y_id, expr, cellFileinfo));
register_reverse_wire_map(y_id, cell->getPort(ID::Q));
register_reverse_wire_map(y_id, cell->getPort(TW::Q));
continue;
}
@ -923,9 +923,9 @@ struct FirrtlWorker
// assign y = a[b +: y_width];
// We'll extract the correct bits as part of the primop.
string a_expr = make_expr(cell->getPort(ID::A));
string a_expr = make_expr(cell->getPort(TW::A));
// Get the initial bit selector
string b_expr = make_expr(cell->getPort(ID::B));
string b_expr = make_expr(cell->getPort(TW::B));
wire_decls.push_back(stringf("%swire %s: UInt<%d>\n", indent, y_id, y_width));
if (cell->getParam(ID::B_SIGNED).as_bool()) {
@ -937,15 +937,15 @@ struct FirrtlWorker
string expr = stringf("dshr(%s, %s)", a_expr, b_expr);
cell_exprs.push_back(stringf("%s%s <= %s\n", indent, y_id, expr));
register_reverse_wire_map(y_id, cell->getPort(ID::Y));
register_reverse_wire_map(y_id, cell->getPort(TW::Y));
continue;
}
if (cell->type == ID($shift)) {
// assign y = a >> b;
// where b may be negative
string a_expr = make_expr(cell->getPort(ID::A));
string b_expr = make_expr(cell->getPort(ID::B));
string a_expr = make_expr(cell->getPort(TW::A));
string b_expr = make_expr(cell->getPort(TW::B));
auto b_string = b_expr.c_str();
string expr;
wire_decls.push_back(stringf("%swire %s: UInt<%d>\n", indent, y_id, y_width));
@ -963,13 +963,13 @@ struct FirrtlWorker
expr = stringf("dshr(%s, %s)", a_expr, b_string);
}
cell_exprs.push_back(stringf("%s%s <= %s\n", indent, y_id, expr));
register_reverse_wire_map(y_id, cell->getPort(ID::Y));
register_reverse_wire_map(y_id, cell->getPort(TW::Y));
continue;
}
if (cell->type == ID($pos)) {
// assign y = a;
// printCell(cell);
string a_expr = make_expr(cell->getPort(ID::A));
string a_expr = make_expr(cell->getPort(TW::A));
// Verilog appears to treat the result as signed, so if the result is wider than "A",
// we need to pad.
if (a_width < y_width) {
@ -977,7 +977,7 @@ struct FirrtlWorker
}
wire_decls.push_back(stringf("%swire %s: UInt<%d>\n", indent, y_id, y_width));
cell_exprs.push_back(stringf("%s%s <= %s\n", indent, y_id, a_expr));
register_reverse_wire_map(y_id, cell->getPort(ID::Y));
register_reverse_wire_map(y_id, cell->getPort(TW::Y));
continue;
}

36
backends/simplec/simplec.cc
View File

@ -380,8 +380,8 @@ struct SimplecWorker
{
if (cell->type.in(ID($_BUF_), ID($_NOT_)))
{
SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A));
SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y));
SigBit a = sigmaps.at(work->module)(cell->getPort(TW::A));
SigBit y = sigmaps.at(work->module)(cell->getPort(TW::Y));
string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
string expr;
@ -399,9 +399,9 @@ struct SimplecWorker
if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)))
{
SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A));
SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B));
SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y));
SigBit a = sigmaps.at(work->module)(cell->getPort(TW::A));
SigBit b = sigmaps.at(work->module)(cell->getPort(TW::B));
SigBit y = sigmaps.at(work->module)(cell->getPort(TW::Y));
string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0";
@ -426,10 +426,10 @@ struct SimplecWorker
if (cell->type.in(ID($_AOI3_), ID($_OAI3_)))
{
SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A));
SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B));
SigBit c = sigmaps.at(work->module)(cell->getPort(ID::C));
SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y));
SigBit a = sigmaps.at(work->module)(cell->getPort(TW::A));
SigBit b = sigmaps.at(work->module)(cell->getPort(TW::B));
SigBit c = sigmaps.at(work->module)(cell->getPort(TW::C));
SigBit y = sigmaps.at(work->module)(cell->getPort(TW::Y));
string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0";
@ -449,11 +449,11 @@ struct SimplecWorker
if (cell->type.in(ID($_AOI4_), ID($_OAI4_)))
{
SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A));
SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B));
SigBit c = sigmaps.at(work->module)(cell->getPort(ID::C));
SigBit d = sigmaps.at(work->module)(cell->getPort(ID::D));
SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y));
SigBit a = sigmaps.at(work->module)(cell->getPort(TW::A));
SigBit b = sigmaps.at(work->module)(cell->getPort(TW::B));
SigBit c = sigmaps.at(work->module)(cell->getPort(TW::C));
SigBit d = sigmaps.at(work->module)(cell->getPort(TW::D));
SigBit y = sigmaps.at(work->module)(cell->getPort(TW::Y));
string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0";
@ -474,10 +474,10 @@ struct SimplecWorker
if (cell->type.in(ID($_MUX_), ID($_NMUX_)))
{
SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A));
SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B));
SigBit s = sigmaps.at(work->module)(cell->getPort(ID::S));
SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y));
SigBit a = sigmaps.at(work->module)(cell->getPort(TW::A));
SigBit b = sigmaps.at(work->module)(cell->getPort(TW::B));
SigBit s = sigmaps.at(work->module)(cell->getPort(TW::S));
SigBit y = sigmaps.at(work->module)(cell->getPort(TW::Y));
string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0";

94
backends/smt2/smt2.cc
View File

@ -435,15 +435,15 @@ struct Smt2Worker
void export_gate(RTLIL::Cell *cell, std::string expr)
{
RTLIL::SigBit bit = sigmap(cell->getPort(ID::Y).as_bit());
RTLIL::SigBit bit = sigmap(cell->getPort(TW::Y).as_bit());
std::string processed_expr;
for (char ch : expr) {
if (ch == 'A') processed_expr += get_bool(cell->getPort(ID::A));
else if (ch == 'B') processed_expr += get_bool(cell->getPort(ID::B));
else if (ch == 'C') processed_expr += get_bool(cell->getPort(ID::C));
else if (ch == 'D') processed_expr += get_bool(cell->getPort(ID::D));
else if (ch == 'S') processed_expr += get_bool(cell->getPort(ID::S));
if (ch == 'A') processed_expr += get_bool(cell->getPort(TW::A));
else if (ch == 'B') processed_expr += get_bool(cell->getPort(TW::B));
else if (ch == 'C') processed_expr += get_bool(cell->getPort(TW::C));
else if (ch == 'D') processed_expr += get_bool(cell->getPort(TW::D));
else if (ch == 'S') processed_expr += get_bool(cell->getPort(TW::S));
else processed_expr += ch;
}
@ -459,26 +459,26 @@ struct Smt2Worker
void export_bvop(RTLIL::Cell *cell, std::string expr, char type = 0)
{
RTLIL::SigSpec sig_a, sig_b;
RTLIL::SigSpec sig_y = sigmap(cell->getPort(ID::Y));
RTLIL::SigSpec sig_y = sigmap(cell->getPort(TW::Y));
bool is_signed = type == 'U' ? false : cell->getParam(ID::A_SIGNED).as_bool();
int width = GetSize(sig_y);
if (type == 's' || type == 'S' || type == 'd' || type == 'b') {
if (type == 'b')
width = GetSize(cell->getPort(ID::A));
width = GetSize(cell->getPort(TW::A));
else
width = max(width, GetSize(cell->getPort(ID::A)));
width = max(width, GetSize(cell->getPort(TW::A)));
if (cell->hasPort(ID::B))
width = max(width, GetSize(cell->getPort(ID::B)));
width = max(width, GetSize(cell->getPort(TW::B)));
}
if (cell->hasPort(ID::A)) {
sig_a = cell->getPort(ID::A);
sig_a = cell->getPort(TW::A);
sig_a.extend_u0(width, is_signed);
}
if (cell->hasPort(ID::B)) {
sig_b = cell->getPort(ID::B);
sig_b = cell->getPort(TW::B);
sig_b.extend_u0(width, (type == 'S') || (is_signed && !(type == 's')));
}
@ -487,8 +487,8 @@ struct Smt2Worker
for (char ch : expr) {
if (ch == 'A') processed_expr += get_bv(sig_a);
else if (ch == 'B') processed_expr += get_bv(sig_b);
else if (ch == 'P') processed_expr += get_bv(cell->getPort(ID::B));
else if (ch == 'S') processed_expr += get_bv(cell->getPort(ID::S));
else if (ch == 'P') processed_expr += get_bv(cell->getPort(TW::B));
else if (ch == 'S') processed_expr += get_bv(cell->getPort(TW::S));
else if (ch == 'L') processed_expr += is_signed ? "a" : "l";
else if (ch == 'U') processed_expr += is_signed ? "s" : "u";
else processed_expr += ch;
@ -515,7 +515,7 @@ struct Smt2Worker
void export_reduce(RTLIL::Cell *cell, std::string expr, bool identity_val)
{
RTLIL::SigSpec sig_y = sigmap(cell->getPort(ID::Y));
RTLIL::SigSpec sig_y = sigmap(cell->getPort(TW::Y));
std::string processed_expr;
for (char ch : expr)
@ -554,7 +554,7 @@ struct Smt2Worker
if (cell->type == ID($initstate))
{
SigBit bit = sigmap(cell->getPort(ID::Y).as_bit());
SigBit bit = sigmap(cell->getPort(TW::Y).as_bit());
decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) Bool (|%s_is| state)) ; %s\n",
get_id(module), idcounter, get_id(module), get_id(module), log_signal(bit)));
register_bool(bit, idcounter++);
@ -565,11 +565,11 @@ struct Smt2Worker
if (cell->type.in(ID($_FF_), ID($_DFF_P_), ID($_DFF_N_)))
{
registers.insert(cell);
SigBit q_bit = cell->getPort(ID::Q);
SigBit q_bit = cell->getPort(TW::Q);
if (q_bit.is_wire())
decls.push_back(witness_signal("reg", 1, 0, "", idcounter, q_bit.wire));
makebits(stringf("%s#%d", get_id(module), idcounter), 0, log_signal(cell->getPort(ID::Q)));
register_bool(cell->getPort(ID::Q), idcounter++);
makebits(stringf("%s#%d", get_id(module), idcounter), 0, log_signal(cell->getPort(TW::Q)));
register_bool(cell->getPort(TW::Q), idcounter++);
recursive_cells.erase(cell);
return;
}
@ -599,13 +599,13 @@ struct Smt2Worker
{
registers.insert(cell);
int smtoffset = 0;
for (auto chunk : cell->getPort(ID::Q).chunks()) {
for (auto chunk : cell->getPort(TW::Q).chunks()) {
if (chunk.is_wire())
decls.push_back(witness_signal("reg", chunk.width, chunk.offset, "", idcounter, chunk.wire, smtoffset));
smtoffset += chunk.width;
}
makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort(ID::Q)), log_signal(cell->getPort(ID::Q)));
register_bv(cell->getPort(ID::Q), idcounter++);
makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort(TW::Q)), log_signal(cell->getPort(TW::Q)));
register_bv(cell->getPort(TW::Q), idcounter++);
recursive_cells.erase(cell);
return;
}
@ -667,7 +667,7 @@ struct Smt2Worker
if (cell->getParam(ID::B_SIGNED).as_bool()) {
return export_bvop(cell, stringf("(ite (bvsge P #b%0*d) "
"(bvlshr A B) (bvshl A (bvneg B)))",
GetSize(cell->getPort(ID::B)), 0), 'S'); // type 'S' sign extends B
GetSize(cell->getPort(TW::B)), 0), 'S'); // type 'S' sign extends B
} else {
return export_bvop(cell, "(bvlshr A B)", 's');
}
@ -706,8 +706,8 @@ struct Smt2Worker
if (cell->type == ID($divfloor)) {
if (cell->getParam(ID::A_SIGNED).as_bool()) {
// bvsdiv is truncating division, so we can't use it here.
int width = max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::B)));
width = max(width, GetSize(cell->getPort(ID::Y)));
int width = max(GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::B)));
width = max(width, GetSize(cell->getPort(TW::Y)));
auto expr = stringf("(let ("
"(a_neg (bvslt A #b%0*d)) "
"(b_neg (bvslt B #b%0*d))) "
@ -725,9 +725,9 @@ struct Smt2Worker
}
if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool)) &&
2*GetSize(cell->getPort(ID::A).chunks()) < GetSize(cell->getPort(ID::A))) {
2*GetSize(cell->getPort(TW::A).chunks()) < GetSize(cell->getPort(TW::A))) {
bool is_and = cell->type == ID($reduce_and);
string bits(GetSize(cell->getPort(ID::A)), is_and ? '1' : '0');
string bits(GetSize(cell->getPort(TW::A)), is_and ? '1' : '0');
return export_bvop(cell, stringf("(%s A #b%s)", is_and ? "=" : "distinct", bits), 'b');
}
@ -743,11 +743,11 @@ struct Smt2Worker
if (cell->type.in(ID($mux), ID($pmux)))
{
int width = GetSize(cell->getPort(ID::Y));
std::string processed_expr = get_bv(cell->getPort(ID::A));
int width = GetSize(cell->getPort(TW::Y));
std::string processed_expr = get_bv(cell->getPort(TW::A));
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_s = cell->getPort(ID::S);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
RTLIL::SigSpec sig_s = cell->getPort(TW::S);
get_bv(sig_b);
get_bv(sig_s);
@ -758,7 +758,7 @@ struct Smt2Worker
if (verbose)
log("%*s-> import cell: %s\n", 2+2*GetSize(recursive_cells), "", cell);
RTLIL::SigSpec sig = sigmap(cell->getPort(ID::Y));
RTLIL::SigSpec sig = sigmap(cell->getPort(TW::Y));
decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
get_id(module), idcounter, get_id(module), width, processed_expr.c_str(), log_signal(sig)));
register_bv(sig, idcounter++);
@ -971,7 +971,7 @@ struct Smt2Worker
for (auto cell : module->cells())
if (cell->type.in(ID($ff), ID($dff), ID($_FF_), ID($_DFF_P_), ID($_DFF_N_), ID($anyinit))) {
// not using sigmap -- we want the net directly at the dff output
for (auto bit : cell->getPort(ID::Q))
for (auto bit : cell->getPort(TW::Q))
reg_bits.insert(bit);
}
@ -1123,8 +1123,8 @@ struct Smt2Worker
cell->type == ID($assume) ? 'u' :
cell->type == ID($cover) ? 'c' : 0;
string name_a = get_bool(cell->getPort(ID::A));
string name_en = get_bool(cell->getPort(ID::EN));
string name_a = get_bool(cell->getPort(TW::A));
string name_en = get_bool(cell->getPort(TW::EN));
bool private_name = cell->name[0] == '$';
if (!private_name && cell->has_attribute(ID::hdlname)) {
@ -1211,27 +1211,27 @@ struct Smt2Worker
{
if (cell->type.in(ID($_FF_), ID($_DFF_P_), ID($_DFF_N_)))
{
std::string expr_d = get_bool(cell->getPort(ID::D));
std::string expr_q = get_bool(cell->getPort(ID::Q), "next_state");
trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d, expr_q, get_id(cell), log_signal(cell->getPort(ID::Q))));
ex_state_eq.push_back(stringf("(= %s %s)", get_bool(cell->getPort(ID::Q)), get_bool(cell->getPort(ID::Q), "other_state")));
std::string expr_d = get_bool(cell->getPort(TW::D));
std::string expr_q = get_bool(cell->getPort(TW::Q), "next_state");
trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d, expr_q, get_id(cell), log_signal(cell->getPort(TW::Q))));
ex_state_eq.push_back(stringf("(= %s %s)", get_bool(cell->getPort(TW::Q)), get_bool(cell->getPort(TW::Q), "other_state")));
}
if (cell->type.in(ID($ff), ID($dff), ID($anyinit)))
{
std::string expr_d = get_bv(cell->getPort(ID::D));
std::string expr_q = get_bv(cell->getPort(ID::Q), "next_state");
trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d, expr_q, get_id(cell), log_signal(cell->getPort(ID::Q))));
ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort(ID::Q)), get_bv(cell->getPort(ID::Q), "other_state")));
std::string expr_d = get_bv(cell->getPort(TW::D));
std::string expr_q = get_bv(cell->getPort(TW::Q), "next_state");
trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d, expr_q, get_id(cell), log_signal(cell->getPort(TW::Q))));
ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort(TW::Q)), get_bv(cell->getPort(TW::Q), "other_state")));
}
if (cell->type.in(ID($anyconst), ID($allconst)))
{
std::string expr_d = get_bv(cell->getPort(ID::Y));
std::string expr_q = get_bv(cell->getPort(ID::Y), "next_state");
trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d, expr_q, get_id(cell), log_signal(cell->getPort(ID::Y))));
std::string expr_d = get_bv(cell->getPort(TW::Y));
std::string expr_q = get_bv(cell->getPort(TW::Y), "next_state");
trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d, expr_q, get_id(cell), log_signal(cell->getPort(TW::Y))));
if (cell->type == ID($anyconst))
ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort(ID::Y)), get_bv(cell->getPort(ID::Y), "other_state")));
ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort(TW::Y)), get_bv(cell->getPort(TW::Y), "other_state")));
}
}

146
backends/smv/smv.cc
View File

@ -229,8 +229,8 @@ struct SmvWorker
if (cell->type.in(ID($assert)))
{
SigSpec sig_a = cell->getPort(ID::A);
SigSpec sig_en = cell->getPort(ID::EN);
SigSpec sig_a = cell->getPort(TW::A);
SigSpec sig_en = cell->getPort(TW::EN);
invarspecs.push_back(stringf("!bool(%s) | bool(%s);", rvalue(sig_en), rvalue(sig_a)));
@ -239,10 +239,10 @@ struct SmvWorker
if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)))
{
SigSpec sig_a = cell->getPort(ID::A);
SigSpec sig_b = cell->getPort(ID::B);
SigSpec sig_a = cell->getPort(TW::A);
SigSpec sig_b = cell->getPort(TW::B);
int width_y = GetSize(cell->getPort(ID::Y));
int width_y = GetSize(cell->getPort(TW::Y));
int shift_b_width = GetSize(sig_b);
int width_ay = max(GetSize(sig_a), width_y);
int width = width_ay;
@ -303,14 +303,14 @@ struct SmvWorker
GetSize(sig_b)-shift_b_width, width_y, expr.c_str());
}
definitions.push_back(stringf("%s := %s;", lvalue(cell->getPort(ID::Y)), expr));
definitions.push_back(stringf("%s := %s;", lvalue(cell->getPort(TW::Y)), expr));
continue;
}
if (cell->type.in(ID($not), ID($pos), ID($neg)))
{
int width = GetSize(cell->getPort(ID::Y));
int width = GetSize(cell->getPort(TW::Y));
string expr_a, op;
if (cell->type == ID($not)) op = "!";
@ -319,13 +319,13 @@ struct SmvWorker
if (cell->getParam(ID::A_SIGNED).as_bool())
{
definitions.push_back(stringf("%s := unsigned(%s%s);", lvalue(cell->getPort(ID::Y)),
op.c_str(), rvalue_s(cell->getPort(ID::A), width)));
definitions.push_back(stringf("%s := unsigned(%s%s);", lvalue(cell->getPort(TW::Y)),
op.c_str(), rvalue_s(cell->getPort(TW::A), width)));
}
else
{
definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort(ID::Y)),
op.c_str(), rvalue_u(cell->getPort(ID::A), width)));
definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort(TW::Y)),
op.c_str(), rvalue_u(cell->getPort(TW::A), width)));
}
continue;
@ -333,7 +333,7 @@ struct SmvWorker
if (cell->type.in(ID($add), ID($sub), ID($mul), ID($and), ID($or), ID($xor), ID($xnor)))
{
int width = GetSize(cell->getPort(ID::Y));
int width = GetSize(cell->getPort(TW::Y));
string expr_a, expr_b, op;
if (cell->type == ID($add)) op = "+";
@ -346,13 +346,13 @@ struct SmvWorker
if (cell->getParam(ID::A_SIGNED).as_bool())
{
definitions.push_back(stringf("%s := unsigned(%s %s %s);", lvalue(cell->getPort(ID::Y)),
rvalue_s(cell->getPort(ID::A), width), op.c_str(), rvalue_s(cell->getPort(ID::B), width)));
definitions.push_back(stringf("%s := unsigned(%s %s %s);", lvalue(cell->getPort(TW::Y)),
rvalue_s(cell->getPort(TW::A), width), op.c_str(), rvalue_s(cell->getPort(TW::B), width)));
}
else
{
definitions.push_back(stringf("%s := %s %s %s;", lvalue(cell->getPort(ID::Y)),
rvalue_u(cell->getPort(ID::A), width), op.c_str(), rvalue_u(cell->getPort(ID::B), width)));
definitions.push_back(stringf("%s := %s %s %s;", lvalue(cell->getPort(TW::Y)),
rvalue_u(cell->getPort(TW::A), width), op.c_str(), rvalue_u(cell->getPort(TW::B), width)));
}
continue;
@ -361,9 +361,9 @@ struct SmvWorker
// SMV has a "mod" operator, but its semantics don't seem to be well-defined - to be safe, don't generate it at all
if (cell->type.in(ID($div)/*, ID($mod), ID($modfloor)*/))
{
int width_y = GetSize(cell->getPort(ID::Y));
int width = max(width_y, GetSize(cell->getPort(ID::A)));
width = max(width, GetSize(cell->getPort(ID::B)));
int width_y = GetSize(cell->getPort(TW::Y));
int width = max(width_y, GetSize(cell->getPort(TW::A)));
width = max(width, GetSize(cell->getPort(TW::B)));
string expr_a, expr_b, op;
if (cell->type == ID($div)) op = "/";
@ -371,13 +371,13 @@ struct SmvWorker
if (cell->getParam(ID::A_SIGNED).as_bool())
{
definitions.push_back(stringf("%s := resize(unsigned(%s %s %s), %d);", lvalue(cell->getPort(ID::Y)),
rvalue_s(cell->getPort(ID::A), width), op.c_str(), rvalue_s(cell->getPort(ID::B), width), width_y));
definitions.push_back(stringf("%s := resize(unsigned(%s %s %s), %d);", lvalue(cell->getPort(TW::Y)),
rvalue_s(cell->getPort(TW::A), width), op.c_str(), rvalue_s(cell->getPort(TW::B), width), width_y));
}
else
{
definitions.push_back(stringf("%s := resize(%s %s %s, %d);", lvalue(cell->getPort(ID::Y)),
rvalue_u(cell->getPort(ID::A), width), op.c_str(), rvalue_u(cell->getPort(ID::B), width), width_y));
definitions.push_back(stringf("%s := resize(%s %s %s, %d);", lvalue(cell->getPort(TW::Y)),
rvalue_u(cell->getPort(TW::A), width), op.c_str(), rvalue_u(cell->getPort(TW::B), width), width_y));
}
continue;
@ -385,7 +385,7 @@ struct SmvWorker
if (cell->type.in(ID($eq), ID($ne), ID($eqx), ID($nex), ID($lt), ID($le), ID($ge), ID($gt)))
{
int width = max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::B)));
int width = max(GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::B)));
string expr_a, expr_b, op;
if (cell->type == ID($eq)) op = "=";
@ -399,27 +399,27 @@ struct SmvWorker
if (cell->getParam(ID::A_SIGNED).as_bool())
{
expr_a = stringf("resize(signed(%s), %d)", rvalue(cell->getPort(ID::A)), width);
expr_b = stringf("resize(signed(%s), %d)", rvalue(cell->getPort(ID::B)), width);
expr_a = stringf("resize(signed(%s), %d)", rvalue(cell->getPort(TW::A)), width);
expr_b = stringf("resize(signed(%s), %d)", rvalue(cell->getPort(TW::B)), width);
}
else
{
expr_a = stringf("resize(%s, %d)", rvalue(cell->getPort(ID::A)), width);
expr_b = stringf("resize(%s, %d)", rvalue(cell->getPort(ID::B)), width);
expr_a = stringf("resize(%s, %d)", rvalue(cell->getPort(TW::A)), width);
expr_b = stringf("resize(%s, %d)", rvalue(cell->getPort(TW::B)), width);
}
definitions.push_back(stringf("%s := resize(word1(%s %s %s), %d);", lvalue(cell->getPort(ID::Y)),
expr_a.c_str(), op.c_str(), expr_b.c_str(), GetSize(cell->getPort(ID::Y))));
definitions.push_back(stringf("%s := resize(word1(%s %s %s), %d);", lvalue(cell->getPort(TW::Y)),
expr_a.c_str(), op.c_str(), expr_b.c_str(), GetSize(cell->getPort(TW::Y))));
continue;
}
if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool)))
{
int width_a = GetSize(cell->getPort(ID::A));
int width_y = GetSize(cell->getPort(ID::Y));
const char *expr_a = rvalue(cell->getPort(ID::A));
const char *expr_y = lvalue(cell->getPort(ID::Y));
int width_a = GetSize(cell->getPort(TW::A));
int width_y = GetSize(cell->getPort(TW::Y));
const char *expr_a = rvalue(cell->getPort(TW::A));
const char *expr_y = lvalue(cell->getPort(TW::Y));
string expr;
if (cell->type == ID($reduce_and)) expr = stringf("%s = !0ub%d_0", expr_a, width_a);
@ -432,11 +432,11 @@ struct SmvWorker
if (cell->type.in(ID($reduce_xor), ID($reduce_xnor)))
{
int width_y = GetSize(cell->getPort(ID::Y));
const char *expr_y = lvalue(cell->getPort(ID::Y));
int width_y = GetSize(cell->getPort(TW::Y));
const char *expr_y = lvalue(cell->getPort(TW::Y));
string expr;
for (auto bit : cell->getPort(ID::A)) {
for (auto bit : cell->getPort(TW::A)) {
if (!expr.empty())
expr += " xor ";
expr += rvalue(bit);
@ -451,13 +451,13 @@ struct SmvWorker
if (cell->type.in(ID($logic_and), ID($logic_or)))
{
int width_a = GetSize(cell->getPort(ID::A));
int width_b = GetSize(cell->getPort(ID::B));
int width_y = GetSize(cell->getPort(ID::Y));
int width_a = GetSize(cell->getPort(TW::A));
int width_b = GetSize(cell->getPort(TW::B));
int width_y = GetSize(cell->getPort(TW::Y));
string expr_a = stringf("(%s != 0ub%d_0)", rvalue(cell->getPort(ID::A)), width_a);
string expr_b = stringf("(%s != 0ub%d_0)", rvalue(cell->getPort(ID::B)), width_b);
const char *expr_y = lvalue(cell->getPort(ID::Y));
string expr_a = stringf("(%s != 0ub%d_0)", rvalue(cell->getPort(TW::A)), width_a);
string expr_b = stringf("(%s != 0ub%d_0)", rvalue(cell->getPort(TW::B)), width_b);
const char *expr_y = lvalue(cell->getPort(TW::Y));
string expr;
if (cell->type == ID($logic_and)) expr = expr_a + " & " + expr_b;
@ -469,11 +469,11 @@ struct SmvWorker
if (cell->type.in(ID($logic_not)))
{
int width_a = GetSize(cell->getPort(ID::A));
int width_y = GetSize(cell->getPort(ID::Y));
int width_a = GetSize(cell->getPort(TW::A));
int width_y = GetSize(cell->getPort(TW::Y));
string expr_a = stringf("(%s = 0ub%d_0)", rvalue(cell->getPort(ID::A)), width_a);
const char *expr_y = lvalue(cell->getPort(ID::Y));
string expr_a = stringf("(%s = 0ub%d_0)", rvalue(cell->getPort(TW::A)), width_a);
const char *expr_y = lvalue(cell->getPort(TW::Y));
definitions.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr_a, width_y));
continue;
@ -481,31 +481,31 @@ struct SmvWorker
if (cell->type.in(ID($mux), ID($pmux)))
{
int width = GetSize(cell->getPort(ID::Y));
SigSpec sig_a = cell->getPort(ID::A);
SigSpec sig_b = cell->getPort(ID::B);
SigSpec sig_s = cell->getPort(ID::S);
int width = GetSize(cell->getPort(TW::Y));
SigSpec sig_a = cell->getPort(TW::A);
SigSpec sig_b = cell->getPort(TW::B);
SigSpec sig_s = cell->getPort(TW::S);
string expr;
for (int i = 0; i < GetSize(sig_s); i++)
expr += stringf("bool(%s) ? %s : ", rvalue(sig_s[i]), rvalue(sig_b.extract(i*width, width)));
expr += rvalue(sig_a);
definitions.push_back(stringf("%s := %s;", lvalue(cell->getPort(ID::Y)), expr));
definitions.push_back(stringf("%s := %s;", lvalue(cell->getPort(TW::Y)), expr));
continue;
}
if (cell->type == ID($dff))
{
vars.push_back(stringf("%s : unsigned word[%d]; -- %s", lvalue(cell->getPort(ID::Q)), GetSize(cell->getPort(ID::Q)), log_signal(cell->getPort(ID::Q))));
assignments.push_back(stringf("next(%s) := %s;", lvalue(cell->getPort(ID::Q)), rvalue(cell->getPort(ID::D))));
vars.push_back(stringf("%s : unsigned word[%d]; -- %s", lvalue(cell->getPort(TW::Q)), GetSize(cell->getPort(TW::Q)), log_signal(cell->getPort(TW::Q))));
assignments.push_back(stringf("next(%s) := %s;", lvalue(cell->getPort(TW::Q)), rvalue(cell->getPort(TW::D))));
continue;
}
if (cell->type.in(ID($_BUF_), ID($_NOT_)))
{
string op = cell->type == ID($_NOT_) ? "!" : "";
definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort(ID::Y)), op, rvalue(cell->getPort(ID::A))));
definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort(TW::Y)), op, rvalue(cell->getPort(TW::A))));
continue;
}
@ -519,57 +519,57 @@ struct SmvWorker
if (cell->type.in(ID($_XNOR_))) op = "xnor";
if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
definitions.push_back(stringf("%s := %s %s (!%s);", lvalue(cell->getPort(ID::Y)),
rvalue(cell->getPort(ID::A)), op.c_str(), rvalue(cell->getPort(ID::B))));
definitions.push_back(stringf("%s := %s %s (!%s);", lvalue(cell->getPort(TW::Y)),
rvalue(cell->getPort(TW::A)), op.c_str(), rvalue(cell->getPort(TW::B))));
else
if (cell->type.in(ID($_NAND_), ID($_NOR_)))
definitions.push_back(stringf("%s := !(%s %s %s);", lvalue(cell->getPort(ID::Y)),
rvalue(cell->getPort(ID::A)), op.c_str(), rvalue(cell->getPort(ID::B))));
definitions.push_back(stringf("%s := !(%s %s %s);", lvalue(cell->getPort(TW::Y)),
rvalue(cell->getPort(TW::A)), op.c_str(), rvalue(cell->getPort(TW::B))));
else
definitions.push_back(stringf("%s := %s %s %s;", lvalue(cell->getPort(ID::Y)),
rvalue(cell->getPort(ID::A)), op.c_str(), rvalue(cell->getPort(ID::B))));
definitions.push_back(stringf("%s := %s %s %s;", lvalue(cell->getPort(TW::Y)),
rvalue(cell->getPort(TW::A)), op.c_str(), rvalue(cell->getPort(TW::B))));
continue;
}
if (cell->type == ID($_MUX_))
{
definitions.push_back(stringf("%s := bool(%s) ? %s : %s;", lvalue(cell->getPort(ID::Y)),
rvalue(cell->getPort(ID::S)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::A))));
definitions.push_back(stringf("%s := bool(%s) ? %s : %s;", lvalue(cell->getPort(TW::Y)),
rvalue(cell->getPort(TW::S)), rvalue(cell->getPort(TW::B)), rvalue(cell->getPort(TW::A))));
continue;
}
if (cell->type == ID($_NMUX_))
{
definitions.push_back(stringf("%s := !(bool(%s) ? %s : %s);", lvalue(cell->getPort(ID::Y)),
rvalue(cell->getPort(ID::S)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::A))));
definitions.push_back(stringf("%s := !(bool(%s) ? %s : %s);", lvalue(cell->getPort(TW::Y)),
rvalue(cell->getPort(TW::S)), rvalue(cell->getPort(TW::B)), rvalue(cell->getPort(TW::A))));
continue;
}
if (cell->type == ID($_AOI3_))
{
definitions.push_back(stringf("%s := !((%s & %s) | %s);", lvalue(cell->getPort(ID::Y)),
rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::C))));
definitions.push_back(stringf("%s := !((%s & %s) | %s);", lvalue(cell->getPort(TW::Y)),
rvalue(cell->getPort(TW::A)), rvalue(cell->getPort(TW::B)), rvalue(cell->getPort(TW::C))));
continue;
}
if (cell->type == ID($_OAI3_))
{
definitions.push_back(stringf("%s := !((%s | %s) & %s);", lvalue(cell->getPort(ID::Y)),
rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::C))));
definitions.push_back(stringf("%s := !((%s | %s) & %s);", lvalue(cell->getPort(TW::Y)),
rvalue(cell->getPort(TW::A)), rvalue(cell->getPort(TW::B)), rvalue(cell->getPort(TW::C))));
continue;
}
if (cell->type == ID($_AOI4_))
{
definitions.push_back(stringf("%s := !((%s & %s) | (%s & %s));", lvalue(cell->getPort(ID::Y)),
rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::C)), rvalue(cell->getPort(ID::D))));
definitions.push_back(stringf("%s := !((%s & %s) | (%s & %s));", lvalue(cell->getPort(TW::Y)),
rvalue(cell->getPort(TW::A)), rvalue(cell->getPort(TW::B)), rvalue(cell->getPort(TW::C)), rvalue(cell->getPort(TW::D))));
continue;
}
if (cell->type == ID($_OAI4_))
{
definitions.push_back(stringf("%s := !((%s | %s) & (%s | %s));", lvalue(cell->getPort(ID::Y)),
rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::C)), rvalue(cell->getPort(ID::D))));
definitions.push_back(stringf("%s := !((%s | %s) & (%s | %s));", lvalue(cell->getPort(TW::Y)),
rvalue(cell->getPort(TW::A)), rvalue(cell->getPort(TW::B)), rvalue(cell->getPort(TW::C)), rvalue(cell->getPort(TW::D))));
continue;
}

150
backends/verilog/verilog_backend.cc
View File

@ -991,7 +991,7 @@ std::string cellname(RTLIL::Cell *cell)
{
if (!norename && cell->name[0] == '$' && cell->is_builtin_ff() && cell->hasPort(ID::Q) && !cell->type.in(ID($ff), ID($_FF_)))
{
RTLIL::SigSpec sig = cell->getPort(ID::Q);
RTLIL::SigSpec sig = cell->getPort(TW::Q);
if (GetSize(sig) != 1 || sig.is_fully_const())
goto no_special_reg_name;
@ -1026,7 +1026,7 @@ no_special_reg_name:
void dump_cell_expr_uniop(std::ostream &f, std::string indent, RTLIL::Cell *cell, std::string op)
{
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = %s ", op);
dump_attributes(f, "", cell->attributes, " ");
dump_cell_expr_port(f, cell, "A", true);
@ -1036,7 +1036,7 @@ void dump_cell_expr_uniop(std::ostream &f, std::string indent, RTLIL::Cell *cell
void dump_cell_expr_binop(std::ostream &f, std::string indent, RTLIL::Cell *cell, std::string op)
{
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = ");
dump_cell_expr_port(f, cell, "A", true);
f << stringf(" %s ", op);
@ -1100,7 +1100,7 @@ void dump_cell_expr_check(std::ostream &f, std::string indent, const RTLIL::Cell
f << stringf("%s" "%s" "cover (", indent, label);
else
log_abort();
dump_sigspec(f, cell->getPort(ID::A));
dump_sigspec(f, cell->getPort(TW::A));
f << stringf(");\n");
}
@ -1108,7 +1108,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
{
if (cell->type == ID($_NOT_)) {
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = ");
f << stringf("~");
dump_attributes(f, "", cell->attributes, " ");
@ -1118,9 +1118,9 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
}
if (cell->type.in(ID($_BUF_), ID($buf))) {
if (cell->type == ID($buf) && cell->getPort(ID::A).has_const(State::Sz)) {
RTLIL::SigSpec a = cell->getPort(ID::A);
RTLIL::SigSpec y = cell->getPort(ID::Y);
if (cell->type == ID($buf) && cell->getPort(TW::A).has_const(State::Sz)) {
RTLIL::SigSpec a = cell->getPort(TW::A);
RTLIL::SigSpec y = cell->getPort(TW::Y);
a.extend_u0(GetSize(y));
if (a.has_const(State::Sz)) {
@ -1146,7 +1146,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true;
}
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = ");
dump_cell_expr_port(f, cell, "A", false);
f << stringf(";\n");
@ -1155,7 +1155,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_))) {
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = ");
if (cell->type.in(ID($_NAND_), ID($_NOR_), ID($_XNOR_)))
f << stringf("~(");
@ -1180,7 +1180,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type == ID($_MUX_)) {
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = ");
dump_cell_expr_port(f, cell, "S", false);
f << stringf(" ? ");
@ -1194,7 +1194,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type == ID($_NMUX_)) {
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = !(");
dump_cell_expr_port(f, cell, "S", false);
f << stringf(" ? ");
@ -1208,7 +1208,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type.in(ID($_AOI3_), ID($_OAI3_))) {
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = ~((");
dump_cell_expr_port(f, cell, "A", false);
f << (cell->type == ID($_AOI3_) ? " & " : " | ");
@ -1223,7 +1223,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type.in(ID($_AOI4_), ID($_OAI4_))) {
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = ~((");
dump_cell_expr_port(f, cell, "A", false);
f << (cell->type == ID($_AOI4_) ? " & " : " | ");
@ -1295,15 +1295,15 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
// assign Y = $signed(_2_) / $signed(_1_);
if (cell->getParam(ID::A_SIGNED).as_bool() && cell->getParam(ID::B_SIGNED).as_bool()) {
SigSpec sig_a = cell->getPort(ID::A);
SigSpec sig_b = cell->getPort(ID::B);
SigSpec sig_a = cell->getPort(TW::A);
SigSpec sig_b = cell->getPort(TW::B);
std::string buf_a = next_auto_id();
std::string buf_b = next_auto_id();
std::string buf_num = next_auto_id();
int size_a = GetSize(sig_a);
int size_b = GetSize(sig_b);
int size_y = GetSize(cell->getPort(ID::Y));
int size_y = GetSize(cell->getPort(TW::Y));
int size_max = std::max(size_a, std::max(size_b, size_y));
// intentionally one wider than maximum width
@ -1329,7 +1329,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = $signed(%s) / ", buf_num);
dump_attributes(f, "", cell->attributes, " ");
f << stringf("$signed(%s);\n", buf_b);
@ -1347,11 +1347,11 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
// assign Y = (A[-1] == B[-1]) || truncated == 0 ? $signed(truncated) : $signed(B) + $signed(truncated);
if (cell->getParam(ID::A_SIGNED).as_bool() && cell->getParam(ID::B_SIGNED).as_bool()) {
SigSpec sig_a = cell->getPort(ID::A);
SigSpec sig_b = cell->getPort(ID::B);
SigSpec sig_a = cell->getPort(TW::A);
SigSpec sig_b = cell->getPort(TW::B);
std::string temp_id = next_auto_id();
f << stringf("%s" "wire [%d:0] %s = ", indent, GetSize(cell->getPort(ID::A))-1, temp_id);
f << stringf("%s" "wire [%d:0] %s = ", indent, GetSize(cell->getPort(TW::A))-1, temp_id);
dump_cell_expr_port(f, cell, "A", true);
f << stringf(" %% ");
dump_attributes(f, "", cell->attributes, " ");
@ -1359,7 +1359,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
f << stringf(";\n");
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = (");
dump_sigspec(f, sig_a.extract(sig_a.size()-1));
f << stringf(" == ");
@ -1378,7 +1378,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type == ID($shift))
{
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = ");
if (cell->getParam(ID::B_SIGNED).as_bool())
{
@ -1386,17 +1386,17 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
f << stringf(" < 0 ? ");
dump_cell_expr_port(f, cell, "A", true);
f << stringf(" << - ");
dump_sigspec(f, cell->getPort(ID::B));
dump_sigspec(f, cell->getPort(TW::B));
f << stringf(" : ");
dump_cell_expr_port(f, cell, "A", true);
f << stringf(" >> ");
dump_sigspec(f, cell->getPort(ID::B));
dump_sigspec(f, cell->getPort(TW::B));
}
else
{
dump_cell_expr_port(f, cell, "A", true);
f << stringf(" >> ");
dump_sigspec(f, cell->getPort(ID::B));
dump_sigspec(f, cell->getPort(TW::B));
}
f << stringf(";\n");
return true;
@ -1405,16 +1405,16 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type == ID($shiftx))
{
std::string temp_id = next_auto_id();
f << stringf("%s" "wire [%d:0] %s = ", indent, GetSize(cell->getPort(ID::A))-1, temp_id);
dump_sigspec(f, cell->getPort(ID::A));
f << stringf("%s" "wire [%d:0] %s = ", indent, GetSize(cell->getPort(TW::A))-1, temp_id);
dump_sigspec(f, cell->getPort(TW::A));
f << stringf(";\n");
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = %s[", temp_id);
if (cell->getParam(ID::B_SIGNED).as_bool())
f << stringf("$signed(");
dump_sigspec(f, cell->getPort(ID::B));
dump_sigspec(f, cell->getPort(TW::B));
if (cell->getParam(ID::B_SIGNED).as_bool())
f << stringf(")");
f << stringf(" +: %d", cell->getParam(ID::Y_WIDTH).as_int());
@ -1425,14 +1425,14 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type == ID($mux))
{
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = ");
dump_sigspec(f, cell->getPort(ID::S));
dump_sigspec(f, cell->getPort(TW::S));
f << stringf(" ? ");
dump_attributes(f, "", cell->attributes, " ");
dump_sigspec(f, cell->getPort(ID::B));
dump_sigspec(f, cell->getPort(TW::B));
f << stringf(" : ");
dump_sigspec(f, cell->getPort(ID::A));
dump_sigspec(f, cell->getPort(TW::A));
f << stringf(";\n");
return true;
}
@ -1440,7 +1440,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type == ID($pmux))
{
int width = cell->parameters[ID::WIDTH].as_int();
int s_width = cell->getPort(ID::S).size();
int s_width = cell->getPort(TW::S).size();
std::string func_name = cellname(cell);
f << stringf("%s" "function [%d:0] %s;\n", indent, width-1, func_name);
@ -1486,13 +1486,13 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
f << stringf("%s" "endfunction\n", indent);
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = %s(", func_name);
dump_sigspec(f, cell->getPort(ID::A));
dump_sigspec(f, cell->getPort(TW::A));
f << stringf(", ");
dump_sigspec(f, cell->getPort(ID::B));
dump_sigspec(f, cell->getPort(TW::B));
f << stringf(", ");
dump_sigspec(f, cell->getPort(ID::S));
dump_sigspec(f, cell->getPort(TW::S));
f << stringf(");\n");
return true;
}
@ -1500,11 +1500,11 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type == ID($tribuf))
{
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = ");
dump_sigspec(f, cell->getPort(ID::EN));
dump_sigspec(f, cell->getPort(TW::EN));
f << stringf(" ? ");
dump_sigspec(f, cell->getPort(ID::A));
dump_sigspec(f, cell->getPort(TW::A));
f << stringf(" : %d'bz;\n", cell->parameters.at(ID::WIDTH).as_int());
return true;
}
@ -1512,9 +1512,9 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type == ID($slice))
{
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = ");
dump_sigspec(f, cell->getPort(ID::A));
dump_sigspec(f, cell->getPort(TW::A));
f << stringf(" >> %d;\n", cell->parameters.at(ID::OFFSET).as_int());
return true;
}
@ -1522,11 +1522,11 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type == ID($concat))
{
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = { ");
dump_sigspec(f, cell->getPort(ID::B));
dump_sigspec(f, cell->getPort(TW::B));
f << stringf(" , ");
dump_sigspec(f, cell->getPort(ID::A));
dump_sigspec(f, cell->getPort(TW::A));
f << stringf(" };\n");
return true;
}
@ -1534,12 +1534,12 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type == ID($lut))
{
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = ");
dump_const(f, cell->parameters.at(ID::LUT));
f << stringf(" >> ");
dump_attributes(f, "", cell->attributes, " ");
dump_sigspec(f, cell->getPort(ID::A));
dump_sigspec(f, cell->getPort(TW::A));
f << stringf(";\n");
return true;
}
@ -1552,16 +1552,16 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
int width = cell->getParam(ID::WIDTH).as_int() ;
if (width == 1) {
f << stringf("%s" "tran(", indent);
dump_sigspec(f, cell->getPort(ID::A));
dump_sigspec(f, cell->getPort(TW::A));
f << stringf(", ");
dump_sigspec(f, cell->getPort(ID::B));
dump_sigspec(f, cell->getPort(TW::B));
f << stringf(");\n");
} else {
auto tran_id = next_auto_id();
f << stringf("%s" "tran %s[%d:0](", indent, tran_id, width - 1);
dump_sigspec(f, cell->getPort(ID::A));
dump_sigspec(f, cell->getPort(TW::A));
f << stringf(", ");
dump_sigspec(f, cell->getPort(ID::B));
dump_sigspec(f, cell->getPort(TW::B));
f << stringf(");\n");
}
return true;
@ -1794,9 +1794,9 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type.in(ID($assert), ID($assume), ID($cover)))
{
f << stringf("%s" "always%s if (", indent, systemverilog ? "_comb" : " @*");
dump_sigspec(f, cell->getPort(ID::EN));
dump_sigspec(f, cell->getPort(TW::EN));
f << stringf(") %s(", cell->type.c_str()+1);
dump_sigspec(f, cell->getPort(ID::A));
dump_sigspec(f, cell->getPort(TW::A));
f << stringf(");\n");
return true;
}
@ -1805,10 +1805,10 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
{
f << stringf("%s" "specify\n%s ", indent, indent);
SigSpec en = cell->getPort(ID::EN);
SigSpec en = cell->getPort(TW::EN);
if (en != State::S1) {
f << stringf("if (");
dump_sigspec(f, cell->getPort(ID::EN));
dump_sigspec(f, cell->getPort(TW::EN));
f << stringf(") ");
}
@ -1816,7 +1816,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type == ID($specify3) && cell->getParam(ID::EDGE_EN).as_bool())
f << (cell->getParam(ID::EDGE_POL).as_bool() ? "posedge ": "negedge ");
dump_sigspec(f, cell->getPort(ID::SRC));
dump_sigspec(f, cell->getPort(TW::SRC));
f << " ";
if (cell->getParam(ID::SRC_DST_PEN).as_bool())
@ -1825,15 +1825,15 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type == ID($specify3)) {
f << "(";
dump_sigspec(f, cell->getPort(ID::DST));
dump_sigspec(f, cell->getPort(TW::DST));
f << " ";
if (cell->getParam(ID::DAT_DST_PEN).as_bool())
f << (cell->getParam(ID::DAT_DST_POL).as_bool() ? "+": "-");
f << ": ";
dump_sigspec(f, cell->getPort(ID::DAT));
dump_sigspec(f, cell->getPort(TW::DAT));
f << ")";
} else {
dump_sigspec(f, cell->getPort(ID::DST));
dump_sigspec(f, cell->getPort(TW::DST));
}
bool bak_decimal = decimal;
@ -1868,21 +1868,21 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->getParam(ID::SRC_PEN).as_bool())
f << (cell->getParam(ID::SRC_POL).as_bool() ? "posedge ": "negedge ");
dump_sigspec(f, cell->getPort(ID::SRC));
dump_sigspec(f, cell->getPort(TW::SRC));
if (cell->getPort(ID::SRC_EN) != State::S1) {
if (cell->getPort(TW::SRC_EN) != State::S1) {
f << " &&& ";
dump_sigspec(f, cell->getPort(ID::SRC_EN));
dump_sigspec(f, cell->getPort(TW::SRC_EN));
}
f << ", ";
if (cell->getParam(ID::DST_PEN).as_bool())
f << (cell->getParam(ID::DST_POL).as_bool() ? "posedge ": "negedge ");
dump_sigspec(f, cell->getPort(ID::DST));
dump_sigspec(f, cell->getPort(TW::DST));
if (cell->getPort(ID::DST_EN) != State::S1) {
if (cell->getPort(TW::DST_EN) != State::S1) {
f << " &&& ";
dump_sigspec(f, cell->getPort(ID::DST_EN));
dump_sigspec(f, cell->getPort(TW::DST_EN));
}
bool bak_decimal = decimal;
@ -1920,7 +1920,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
f << stringf("%s" "always @*\n", indent);
f << stringf("%s" " if (", indent);
dump_sigspec(f, cell->getPort(ID::EN));
dump_sigspec(f, cell->getPort(TW::EN));
f << stringf(")\n");
dump_cell_expr_print(f, indent + " ", cell);
@ -1936,7 +1936,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
f << stringf("%s" "always @*\n", indent);
f << stringf("%s" " if (", indent);
dump_sigspec(f, cell->getPort(ID::EN));
dump_sigspec(f, cell->getPort(TW::EN));
f << stringf(") begin\n");
std::string flavor = cell->getParam(ID::FLAVOR).decode_string();
@ -1945,7 +1945,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
fmt.parse_rtlil(cell);
if (!fmt.parts.empty()) {
f << stringf("%s" " if (!", indent);
dump_sigspec(f, cell->getPort(ID::A));
dump_sigspec(f, cell->getPort(TW::A));
f << stringf(")\n");
dump_cell_expr_print(f, indent + " ", cell);
}
@ -2047,7 +2047,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (siminit && cell->is_builtin_ff() && cell->hasPort(ID::Q) && !cell->type.in(ID($ff), ID($_FF_))) {
std::stringstream ss;
dump_reg_init(ss, cell->getPort(ID::Q));
dump_reg_init(ss, cell->getPort(TW::Q));
if (!ss.str().empty()) {
f << stringf("%sinitial %s.Q", indent, cell_name);
f << ss.str();
@ -2079,7 +2079,7 @@ void dump_sync_effect(std::ostream &f, std::string indent, const RTLIL::SigSpec
});
for (auto cell : cells) {
f << stringf("%s" " if (", indent);
dump_sigspec(f, cell->getPort(ID::EN));
dump_sigspec(f, cell->getPort(TW::EN));
f << stringf(") begin\n");
if (cell->type == ID($print)) {
@ -2091,7 +2091,7 @@ void dump_sync_effect(std::ostream &f, std::string indent, const RTLIL::SigSpec
fmt.parse_rtlil(cell);
if (!fmt.parts.empty()) {
f << stringf("%s" " if (!", indent);
dump_sigspec(f, cell->getPort(ID::A));
dump_sigspec(f, cell->getPort(TW::A));
f << stringf(")\n");
dump_cell_expr_print(f, indent + " ", cell);
}
@ -2402,14 +2402,14 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
for (auto cell : module->cells())
{
if (cell->type.in(ID($print), ID($check)) && cell->getParam(ID::TRG_ENABLE).as_bool()) {
sync_effect_cells[make_pair(cell->getPort(ID::TRG), cell->getParam(ID::TRG_POLARITY))].push_back(cell);
sync_effect_cells[make_pair(cell->getPort(TW::TRG), cell->getParam(ID::TRG_POLARITY))].push_back(cell);
continue;
}
if (!cell->is_builtin_ff() || !cell->hasPort(ID::Q) || cell->type.in(ID($ff), ID($_FF_)))
continue;
RTLIL::SigSpec sig = cell->getPort(ID::Q);
RTLIL::SigSpec sig = cell->getPort(TW::Q);
if (sig.is_chunk()) {
RTLIL::SigChunk chunk = sig.as_chunk();

2
docs/source/code_examples/extensions/my_cmd.cc
View File

@ -38,7 +38,7 @@ struct Test1Pass : public Pass {
y->port_output = true;
y->port_id = 2;
RTLIL::Wire *a_inv = module->addWire(NEW_ID, 4);
RTLIL::Wire *a_inv = module->addWire(NEW_TWINE, 4);
module->addNeg(NEW_ID, a, a_inv, true);
module->addMux(NEW_ID, a, a_inv, RTLIL::SigSpec(a, 3), y);

12
frontends/aiger/aigerparse.cc
View File

@ -130,7 +130,7 @@ struct ConstEvalAig
sig2deps[output].insert(output);
RTLIL::Cell *cell = sig2driver.at(output);
RTLIL::SigBit sig_a = cell->getPort(ID::A);
RTLIL::SigBit sig_a = cell->getPort(TW::A);
sig2deps[sig_a].reserve(sig2deps[sig_a].size() + sig2deps[output].size()); // Reserve so that any invalidation
// that may occur does so here, and
// not mid insertion (below)
@ -139,7 +139,7 @@ struct ConstEvalAig
compute_deps(sig_a, inputs);
if (cell->type == ID($_AND_)) {
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
sig2deps[sig_b].reserve(sig2deps[sig_b].size() + sig2deps[output].size()); // Reserve so that any invalidation
// that may occur does so here, and
// not mid insertion (below)
@ -155,11 +155,11 @@ struct ConstEvalAig
bool eval(RTLIL::Cell *cell)
{
RTLIL::SigBit sig_y = cell->getPort(ID::Y);
RTLIL::SigBit sig_y = cell->getPort(TW::Y);
if (values_map.count(sig_y))
return true;
RTLIL::SigBit sig_a = cell->getPort(ID::A);
RTLIL::SigBit sig_a = cell->getPort(TW::A);
if (!eval(sig_a))
return false;
@ -175,7 +175,7 @@ struct ConstEvalAig
}
{
RTLIL::SigBit sig_b = cell->getPort(ID::B);
RTLIL::SigBit sig_b = cell->getPort(TW::B);
if (!eval(sig_b))
return false;
if (sig_b == State::S0) {
@ -978,7 +978,7 @@ void AigerReader::post_process()
for (auto cell : module->cells().to_vector()) {
if (cell->type != ID($lut)) continue;
auto y_port = cell->getPort(ID::Y).as_bit();
auto y_port = cell->getPort(TW::Y).as_bit();
if (y_port.wire->width == 1)
module->rename(cell, stringf("$lut%s", y_port.wire->name));
else

68
frontends/ast/genrtlil.cc
View File

@ -62,10 +62,10 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, IdString type, int result_width
cell->parameters[ID::A_SIGNED] = RTLIL::Const(that->children[0]->is_signed);
cell->parameters[ID::A_WIDTH] = RTLIL::Const(arg.size());
cell->setPort(ID::A, arg);
cell->setPort(TW::A, arg);
cell->parameters[ID::Y_WIDTH] = result_width;
cell->setPort(ID::Y, wire);
cell->setPort(TW::Y, wire);
return wire;
}
@ -94,10 +94,10 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
cell->parameters[ID::A_SIGNED] = RTLIL::Const(is_signed);
cell->parameters[ID::A_WIDTH] = RTLIL::Const(sig.size());
cell->setPort(ID::A, sig);
cell->setPort(TW::A, sig);
cell->parameters[ID::Y_WIDTH] = width;
cell->setPort(ID::Y, wire);
cell->setPort(TW::Y, wire);
sig = wire;
}
@ -124,11 +124,11 @@ static RTLIL::SigSpec binop2rtlil(AstNode *that, IdString type, int result_width
cell->parameters[ID::A_WIDTH] = RTLIL::Const(left.size());
cell->parameters[ID::B_WIDTH] = RTLIL::Const(right.size());
cell->setPort(ID::A, left);
cell->setPort(ID::B, right);
cell->setPort(TW::A, left);
cell->setPort(TW::B, right);
cell->parameters[ID::Y_WIDTH] = result_width;
cell->setPort(ID::Y, wire);
cell->setPort(TW::Y, wire);
return wire;
}
@ -155,10 +155,10 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
cell->parameters[ID::WIDTH] = RTLIL::Const(left.size());
cell->setPort(ID::A, right);
cell->setPort(ID::B, left);
cell->setPort(ID::S, cond);
cell->setPort(ID::Y, wire);
cell->setPort(TW::A, right);
cell->setPort(TW::B, left);
cell->setPort(TW::S, cond);
cell->setPort(TW::Y, wire);
return wire;
}
@ -842,8 +842,8 @@ struct AST_INTERNAL::ProcessGenerator
cell->setParam(ID::TRG_ENABLE, (always->type == AST_INITIAL) || !triggers.empty());
cell->setParam(ID::TRG_POLARITY, polarity);
cell->setParam(ID::PRIORITY, --last_effect_priority);
cell->setPort(ID::TRG, triggers);
cell->setPort(ID::EN, en);
cell->setPort(TW::TRG, triggers);
cell->setPort(TW::EN, en);
int default_base = 10;
if (ast->str.back() == 'b')
@ -947,9 +947,9 @@ struct AST_INTERNAL::ProcessGenerator
cell->setParam(ID::TRG_ENABLE, (always->type == AST_INITIAL) || !triggers.empty());
cell->setParam(ID::TRG_POLARITY, polarity);
cell->setParam(ID::PRIORITY, --last_effect_priority);
cell->setPort(ID::TRG, triggers);
cell->setPort(ID::EN, en);
cell->setPort(ID::A, check);
cell->setPort(TW::TRG, triggers);
cell->setPort(TW::EN, en);
cell->setPort(TW::A, check);
// No message is emitted to ensure Verilog code roundtrips correctly.
Fmt fmt;
@ -2058,10 +2058,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
RTLIL::SigSpec addr_sig = children[0]->genRTLIL();
cell->setPort(ID::CLK, RTLIL::SigSpec(RTLIL::State::Sx, 1));
cell->setPort(ID::EN, RTLIL::SigSpec(RTLIL::State::Sx, 1));
cell->setPort(ID::ADDR, addr_sig);
cell->setPort(ID::DATA, RTLIL::SigSpec(wire));
cell->setPort(TW::CLK, RTLIL::SigSpec(RTLIL::State::Sx, 1));
cell->setPort(TW::EN, RTLIL::SigSpec(RTLIL::State::Sx, 1));
cell->setPort(TW::ADDR, addr_sig);
cell->setPort(TW::DATA, RTLIL::SigSpec(wire));
cell->parameters[ID::MEMID] = RTLIL::Const(str);
cell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr_sig));
@ -2098,9 +2098,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
SigSpec addr_sig = children[0]->genRTLIL();
cell->setPort(ID::ADDR, addr_sig);
cell->setPort(ID::DATA, children[1]->genWidthRTLIL(current_module->memories[str]->width * num_words, true));
cell->setPort(ID::EN, en_sig);
cell->setPort(TW::ADDR, addr_sig);
cell->setPort(TW::DATA, children[1]->genWidthRTLIL(current_module->memories[str]->width * num_words, true));
cell->setPort(TW::EN, en_sig);
cell->parameters[ID::MEMID] = RTLIL::Const(str);
cell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr_sig));
@ -2147,9 +2147,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
cell->parameters[ID::TRG_ENABLE] = 0;
cell->parameters[ID::TRG_POLARITY] = 0;
cell->parameters[ID::PRIORITY] = 0;
cell->setPort(ID::TRG, RTLIL::SigSpec());
cell->setPort(ID::EN, RTLIL::S1);
cell->setPort(ID::A, check);
cell->setPort(TW::TRG, RTLIL::SigSpec());
cell->setPort(TW::EN, RTLIL::S1);
cell->setPort(TW::A, check);
// No message is emitted to ensure Verilog code roundtrips correctly.
Fmt fmt;
@ -2262,8 +2262,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
cell->attributes[attr.first] = attr.second->asAttrConst();
}
if (cell->type == ID($specify2)) {
int src_width = GetSize(cell->getPort(ID::SRC));
int dst_width = GetSize(cell->getPort(ID::DST));
int src_width = GetSize(cell->getPort(TW::SRC));
int dst_width = GetSize(cell->getPort(TW::DST));
bool full = cell->getParam(ID::FULL).as_bool();
if (!full && src_width != dst_width)
input_error("Parallel specify SRC width does not match DST width.\n");
@ -2271,17 +2271,17 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
cell->setParam(ID::DST_WIDTH, Const(dst_width));
}
else if (cell->type == ID($specify3)) {
int dat_width = GetSize(cell->getPort(ID::DAT));
int dst_width = GetSize(cell->getPort(ID::DST));
int dat_width = GetSize(cell->getPort(TW::DAT));
int dst_width = GetSize(cell->getPort(TW::DST));
if (dat_width != dst_width)
input_error("Specify DAT width does not match DST width.\n");
int src_width = GetSize(cell->getPort(ID::SRC));
int src_width = GetSize(cell->getPort(TW::SRC));
cell->setParam(ID::SRC_WIDTH, Const(src_width));
cell->setParam(ID::DST_WIDTH, Const(dst_width));
}
else if (cell->type == ID($specrule)) {
int src_width = GetSize(cell->getPort(ID::SRC));
int dst_width = GetSize(cell->getPort(ID::DST));
int src_width = GetSize(cell->getPort(TW::SRC));
int dst_width = GetSize(cell->getPort(TW::DST));
cell->setParam(ID::SRC_WIDTH, Const(src_width));
cell->setParam(ID::DST_WIDTH, Const(dst_width));
}
@ -2370,7 +2370,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
Wire *wire = current_module->addWire(myid + "_wire", width);
set_src_attr(wire, this);
cell->setPort(ID::Y, wire);
cell->setPort(TW::Y, wire);
is_signed = sign_hint;
return SigSpec(wire);

2
frontends/ast/simplify.cc
View File

@ -1479,7 +1479,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
continue;
// determine the full name of port this argument is connected to
RTLIL::IdString port_name;
TwineRef port_name;
if (child->str.size())
port_name = child->str;
else {

30
frontends/blif/blifparse.cc
View File

@ -226,7 +226,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
for (auto cell : module->cells())
if (cell->type == ID($lut) && cell->getParam(ID::LUT) == buffer_lut) {
module->connect(cell->getPort(ID::Y), cell->getPort(ID::A));
module->connect(cell->getPort(TW::Y), cell->getPort(TW::A));
remove_cells.push_back(cell);
}
@ -376,9 +376,9 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
if (dff_name.empty()) {
cell = module->addFfGate(NEW_ID, blif_wire(d), blif_wire(q));
} else {
cell = module->addCell(NEW_ID, dff_name);
cell->setPort(ID::D, blif_wire(d));
cell->setPort(ID::Q, blif_wire(q));
cell = module->addCell(NEW_TWINE, dff_name);
cell->setPort(TW::D, blif_wire(d));
cell->setPort(TW::Q, blif_wire(q));
}
}
@ -395,7 +395,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
goto error;
IdString celltype = RTLIL::escape_id(p);
RTLIL::Cell *cell = module->addCell(NEW_ID, celltype);
RTLIL::Cell *cell = module->addCell(NEW_TWINE, celltype);
RTLIL::Module *cell_mod = design->module(celltype);
dict<RTLIL::IdString, dict<int, SigBit>> cell_wideports_cache;
@ -442,7 +442,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
if (it.second.count(idx))
sig.append(it.second.at(idx));
else
sig.append(module->addWire(NEW_ID));
sig.append(module->addWire(NEW_TWINE));
}
cell->setPort(it.first, sig);
@ -539,12 +539,12 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
if (sop_mode)
{
sopcell = module->addCell(NEW_ID, ID($sop));
sopcell = module->addCell(NEW_TWINE, ID($sop));
sopcell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size());
sopcell->parameters[ID::DEPTH] = 0;
sopcell->parameters[ID::TABLE] = RTLIL::Const();
sopcell->setPort(ID::A, input_sig);
sopcell->setPort(ID::Y, output_sig);
sopcell->setPort(TW::A, input_sig);
sopcell->setPort(TW::Y, output_sig);
sopmode = -1;
lastcell = sopcell;
}
@ -555,11 +555,11 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
}
else
{
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($lut));
RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($lut));
cell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size());
cell->parameters[ID::LUT] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size());
cell->setPort(ID::A, input_sig);
cell->setPort(ID::Y, output_sig);
cell->setPort(TW::A, input_sig);
cell->setPort(TW::Y, output_sig);
lutptr = &cell->parameters.at(ID::LUT);
lut_default_state = RTLIL::State::Sx;
lastcell = cell;
@ -607,10 +607,10 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
if (sopmode == -1) {
sopmode = (*output == '1');
if (!sopmode) {
SigSpec outnet = sopcell->getPort(ID::Y);
SigSpec tempnet = module->addWire(NEW_ID);
SigSpec outnet = sopcell->getPort(TW::Y);
SigSpec tempnet = module->addWire(NEW_TWINE);
module->addNotGate(NEW_ID, tempnet, outnet);
sopcell->setPort(ID::Y, tempnet);
sopcell->setPort(TW::Y, tempnet);
}
} else
log_assert(sopmode == (*output == '1'));

2
frontends/json/jsonparse.cc
View File

@ -572,7 +572,7 @@ void json_import(Design *design, string &modname, JsonNode *node)
if (bitval_node->type == 'N') {
int bitidx = bitval_node->data_number;
if (signal_bits.count(bitidx) == 0)
signal_bits[bitidx] = module->addWire(NEW_ID);
signal_bits[bitidx] = module->addWire(NEW_TWINE);
sig.append(signal_bits.at(bitidx));
} else
log_error("JSON cells node '%s' connection '%s' has invalid bit value on bit %d.\n",

126
frontends/liberty/liberty.cc
View File

@ -185,12 +185,12 @@ static RTLIL::SigSpec create_tristate(RTLIL::Module *module, RTLIL::SigSpec func
{
RTLIL::SigSpec three_state = parse_func_expr(module, three_state_expr);
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($tribuf));
RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($tribuf));
cell->setParam(ID::WIDTH, GetSize(func));
cell->setPort(ID::A, func);
cell->setPort(ID::EN, module->NotGate(NEW_ID, three_state));
cell->setPort(ID::Y, module->addWire(NEW_ID));
return cell->getPort(ID::Y);
cell->setPort(TW::A, func);
cell->setPort(TW::EN, module->NotGate(NEW_ID, three_state));
cell->setPort(TW::Y, module->addWire(NEW_TWINE));
return cell->getPort(TW::Y);
}
static void create_latch_ff_wires(RTLIL::Module *module, const LibertyAst *node)
@ -243,18 +243,18 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node)
rerun_invert_rollback = false;
for (auto &it : module->cells_) {
if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == clk_sig) {
clk_sig = it.second->getPort(ID::A);
if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == clk_sig) {
clk_sig = it.second->getPort(TW::A);
clk_polarity = !clk_polarity;
rerun_invert_rollback = true;
}
if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == clear_sig) {
clear_sig = it.second->getPort(ID::A);
if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == clear_sig) {
clear_sig = it.second->getPort(TW::A);
clear_polarity = !clear_polarity;
rerun_invert_rollback = true;
}
if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == preset_sig) {
preset_sig = it.second->getPort(ID::A);
if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == preset_sig) {
preset_sig = it.second->getPort(TW::A);
preset_polarity = !preset_polarity;
rerun_invert_rollback = true;
}
@ -264,14 +264,14 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node)
for (auto& [out_sig, cp_var, neg] : {tuple{iq_sig, clear_preset_var1, false}, {iqn_sig, clear_preset_var2, true}}) {
SigSpec q_sig = out_sig;
if (neg) {
q_sig = module->addWire(NEW_ID, out_sig.as_wire());
q_sig = module->addWire(NEW_TWINE, out_sig.as_wire());
module->addNotGate(NEW_ID, q_sig, out_sig);
}
RTLIL::Cell* cell = module->addCell(NEW_ID, "");
cell->setPort(ID::D, data_sig);
cell->setPort(ID::Q, q_sig);
cell->setPort(ID::C, clk_sig);
RTLIL::Cell* cell = module->addCell(NEW_TWINE, "");
cell->setPort(TW::D, data_sig);
cell->setPort(TW::Q, q_sig);
cell->setPort(TW::C, clk_sig);
if (clear_sig.size() == 0 && preset_sig.size() == 0) {
cell->type = stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N');
@ -279,12 +279,12 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node)
if (clear_sig.size() == 1 && preset_sig.size() == 0) {
cell->type = stringf("$_DFF_%c%c0_", clk_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N');
cell->setPort(ID::R, clear_sig);
cell->setPort(TW::R, clear_sig);
}
if (clear_sig.size() == 0 && preset_sig.size() == 1) {
cell->type = stringf("$_DFF_%c%c1_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N');
cell->setPort(ID::R, preset_sig);
cell->setPort(TW::R, preset_sig);
}
if (clear_sig.size() == 1 && preset_sig.size() == 1) {
@ -313,8 +313,8 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node)
log_debug("cell %s variable %d undef c&p behavior\n", name, (int)neg + 1);
}
cell->setPort(ID::S, s_sig);
cell->setPort(ID::R, r_sig);
cell->setPort(TW::S, s_sig);
cell->setPort(TW::R, r_sig);
}
log_assert(!cell->type.empty());
@ -352,27 +352,27 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
rerun_invert_rollback = false;
for (auto &it : module->cells_) {
if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == enable_sig) {
enable_sig = it.second->getPort(ID::A);
if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == enable_sig) {
enable_sig = it.second->getPort(TW::A);
enable_polarity = !enable_polarity;
rerun_invert_rollback = true;
}
if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == clear_sig) {
clear_sig = it.second->getPort(ID::A);
if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == clear_sig) {
clear_sig = it.second->getPort(TW::A);
clear_polarity = !clear_polarity;
rerun_invert_rollback = true;
}
if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == preset_sig) {
preset_sig = it.second->getPort(ID::A);
if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == preset_sig) {
preset_sig = it.second->getPort(TW::A);
preset_polarity = !preset_polarity;
rerun_invert_rollback = true;
}
}
}
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_NOT_));
cell->setPort(ID::A, iq_sig);
cell->setPort(ID::Y, iqn_sig);
RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($_NOT_));
cell->setPort(TW::A, iq_sig);
cell->setPort(TW::Y, iqn_sig);
if (clear_sig.size() == 1)
{
@ -381,25 +381,25 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
if (clear_polarity == true || clear_polarity != enable_polarity)
{
RTLIL::Cell *inv = module->addCell(NEW_ID, ID($_NOT_));
inv->setPort(ID::A, clear_sig);
inv->setPort(ID::Y, module->addWire(NEW_ID));
RTLIL::Cell *inv = module->addCell(NEW_TWINE, ID($_NOT_));
inv->setPort(TW::A, clear_sig);
inv->setPort(TW::Y, module->addWire(NEW_TWINE));
if (clear_polarity == true)
clear_negative = inv->getPort(ID::Y);
clear_negative = inv->getPort(TW::Y);
if (clear_polarity != enable_polarity)
clear_enable = inv->getPort(ID::Y);
clear_enable = inv->getPort(TW::Y);
}
RTLIL::Cell *data_gate = module->addCell(NEW_ID, ID($_AND_));
data_gate->setPort(ID::A, data_sig);
data_gate->setPort(ID::B, clear_negative);
data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
RTLIL::Cell *data_gate = module->addCell(NEW_TWINE, ID($_AND_));
data_gate->setPort(TW::A, data_sig);
data_gate->setPort(TW::B, clear_negative);
data_gate->setPort(TW::Y, data_sig = module->addWire(NEW_TWINE));
RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? ID($_OR_) : ID($_AND_));
enable_gate->setPort(ID::A, enable_sig);
enable_gate->setPort(ID::B, clear_enable);
enable_gate->setPort(ID::Y, enable_sig = module->addWire(NEW_ID));
RTLIL::Cell *enable_gate = module->addCell(NEW_TWINE, enable_polarity ? ID($_OR_) : ID($_AND_));
enable_gate->setPort(TW::A, enable_sig);
enable_gate->setPort(TW::B, clear_enable);
enable_gate->setPort(TW::Y, enable_sig = module->addWire(NEW_TWINE));
}
if (preset_sig.size() == 1)
@ -409,31 +409,31 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
if (preset_polarity == false || preset_polarity != enable_polarity)
{
RTLIL::Cell *inv = module->addCell(NEW_ID, ID($_NOT_));
inv->setPort(ID::A, preset_sig);
inv->setPort(ID::Y, module->addWire(NEW_ID));
RTLIL::Cell *inv = module->addCell(NEW_TWINE, ID($_NOT_));
inv->setPort(TW::A, preset_sig);
inv->setPort(TW::Y, module->addWire(NEW_TWINE));
if (preset_polarity == false)
preset_positive = inv->getPort(ID::Y);
preset_positive = inv->getPort(TW::Y);
if (preset_polarity != enable_polarity)
preset_enable = inv->getPort(ID::Y);
preset_enable = inv->getPort(TW::Y);
}
RTLIL::Cell *data_gate = module->addCell(NEW_ID, ID($_OR_));
data_gate->setPort(ID::A, data_sig);
data_gate->setPort(ID::B, preset_positive);
data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
RTLIL::Cell *data_gate = module->addCell(NEW_TWINE, ID($_OR_));
data_gate->setPort(TW::A, data_sig);
data_gate->setPort(TW::B, preset_positive);
data_gate->setPort(TW::Y, data_sig = module->addWire(NEW_TWINE));
RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? ID($_OR_) : ID($_AND_));
enable_gate->setPort(ID::A, enable_sig);
enable_gate->setPort(ID::B, preset_enable);
enable_gate->setPort(ID::Y, enable_sig = module->addWire(NEW_ID));
RTLIL::Cell *enable_gate = module->addCell(NEW_TWINE, enable_polarity ? ID($_OR_) : ID($_AND_));
enable_gate->setPort(TW::A, enable_sig);
enable_gate->setPort(TW::B, preset_enable);
enable_gate->setPort(TW::Y, enable_sig = module->addWire(NEW_TWINE));
}
cell = module->addCell(NEW_ID, stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N'));
cell->setPort(ID::D, data_sig);
cell->setPort(ID::Q, iq_sig);
cell->setPort(ID::E, enable_sig);
cell = module->addCell(NEW_TWINE, stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N'));
cell->setPort(TW::D, data_sig);
cell->setPort(TW::Q, iq_sig);
cell->setPort(TW::E, enable_sig);
return true;
}
@ -793,7 +793,7 @@ struct LibertyFrontend : public Frontend {
if (wi->port_input) {
for (auto wo : module->wires())
if (wo->port_output) {
RTLIL::Cell *spec = module->addCell(NEW_ID, ID($specify2));
RTLIL::Cell *spec = module->addCell(NEW_TWINE, ID($specify2));
spec->setParam(ID::SRC_WIDTH, wi->width);
spec->setParam(ID::DST_WIDTH, wo->width);
spec->setParam(ID::T_FALL_MAX, 1000);
@ -805,9 +805,9 @@ struct LibertyFrontend : public Frontend {
spec->setParam(ID::SRC_DST_POL, false);
spec->setParam(ID::SRC_DST_PEN, false);
spec->setParam(ID::FULL, true);
spec->setPort(ID::EN, Const(1, 1));
spec->setPort(ID::SRC, wi);
spec->setPort(ID::DST, wo);
spec->setPort(TW::EN, Const(1, 1));
spec->setPort(TW::SRC, wi);
spec->setPort(TW::DST, wo);
}
}
}

6
frontends/rtlil/rtlil_frontend.cc
View File

@ -445,7 +445,7 @@ struct RTLILFrontendWorker {
current_module = new RTLIL::Module;
current_module->design = design;
current_module->meta_->name_id = module_name;
current_module->meta_->name = module_name;
if (delete_current_module) {
// Module is about to be discarded — drop its src attribute
// rather than push it into a pool we'll never reach.
@ -706,7 +706,7 @@ struct RTLILFrontendWorker {
expect_eol();
}
void legalize_width_parameter(RTLIL::Cell *cell, RTLIL::IdString port_name)
void legalize_width_parameter(RTLIL::Cell *cell, TwineRef port_name)
{
std::string width_param_name = port_name.str() + "_WIDTH";
if (cell->parameters.count(width_param_name) == 0)
@ -763,7 +763,7 @@ struct RTLILFrontendWorker {
cell->parameters.insert({std::move(param_name), std::move(val)});
expect_eol();
} else if (try_parse_keyword("connect")) {
RTLIL::IdString port_name = parse_id();
TwineRef port_name = parse_id();
if (cell->hasPort(port_name)) {
if (flag_legalize)
log("Legalizing redefinition of cell port %s.", port_name);

4
guidelines/GettingStarted
View File

@ -98,8 +98,8 @@ single signal bit can have multiple valid names. The SigMap object can be used
to map SigSpecs or SigBits to unique SigSpecs and SigBits that consistently
only use one wire from such a group of connected wires. For example:
SigBit a = module->addWire(NEW_ID);
SigBit b = module->addWire(NEW_ID);
SigBit a = module->addWire(NEW_TWINE);
SigBit b = module->addWire(NEW_TWINE);
module->connect(a, b);
log("%d\n", a == b); // will print 0

38
kernel/cellaigs.cc
View File

@ -91,7 +91,7 @@ struct AigMaker
return node2index(node);
}
int inport(IdString portname, int portbit = 0, bool inverter = false)
int inport(TwineRef portname, int portbit = 0, bool inverter = false)
{
if (portbit >= GetSize(cell->getPort(portname))) {
if (cell->parameters.count(portname.str() + "_SIGNED") && cell->getParam(portname.str() + "_SIGNED").as_bool())
@ -106,7 +106,7 @@ struct AigMaker
return node2index(node);
}
vector<int> inport_vec(IdString portname, int width)
vector<int> inport_vec(TwineRef portname, int width)
{
vector<int> vec;
for (int i = 0; i < width; i++)
@ -114,7 +114,7 @@ struct AigMaker
return vec;
}
int not_inport(IdString portname, int portbit = 0)
int not_inport(TwineRef portname, int portbit = 0)
{
return inport(portname, portbit, true);
}
@ -244,20 +244,20 @@ struct AigMaker
return Y;
}
void outport(int node, IdString portname, int portbit = 0)
void outport(int node, TwineRef portname, int portbit = 0)
{
if (portbit < GetSize(cell->getPort(portname)))
aig->nodes.at(node).outports.push_back(pair<IdString, int>(portname, portbit));
}
void outport_bool(int node, IdString portname)
void outport_bool(int node, TwineRef portname)
{
outport(node, portname);
for (int i = 1; i < GetSize(cell->getPort(portname)); i++)
outport(bool_node(false), portname, i);
}
void outport_vec(const vector<int> &vec, IdString portname)
void outport_vec(const vector<int> &vec, TwineRef portname)
{
for (int i = 0; i < GetSize(vec); i++)
outport(vec.at(i), portname, i);
@ -304,7 +304,7 @@ Aig::Aig(Cell *cell)
if (cell->type.in(ID($not), ID($_NOT_), ID($pos), ID($buf), ID($_BUF_)))
{
for (int i = 0; i < GetSize(cell->getPort(ID::Y)); i++) {
for (int i = 0; i < GetSize(cell->getPort(TW::Y)); i++) {
int A = mk.inport(ID::A, i);
int Y = cell->type.in(ID($not), ID($_NOT_)) ? mk.not_gate(A) : A;
mk.outport(Y, ID::Y, i);
@ -314,7 +314,7 @@ Aig::Aig(Cell *cell)
if (cell->type.in(ID($and), ID($_AND_), ID($_NAND_), ID($or), ID($_OR_), ID($_NOR_), ID($xor), ID($xnor), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)))
{
for (int i = 0; i < GetSize(cell->getPort(ID::Y)); i++) {
for (int i = 0; i < GetSize(cell->getPort(TW::Y)); i++) {
int A = mk.inport(ID::A, i);
int B = mk.inport(ID::B, i);
int Y = cell->type.in(ID($and), ID($_AND_)) ? mk.and_gate(A, B) :
@ -333,7 +333,7 @@ Aig::Aig(Cell *cell)
if (cell->type.in(ID($mux), ID($_MUX_), ID($_NMUX_)))
{
int S = mk.inport(ID::S);
for (int i = 0; i < GetSize(cell->getPort(ID::Y)); i++) {
for (int i = 0; i < GetSize(cell->getPort(TW::Y)); i++) {
int A = mk.inport(ID::A, i);
int B = mk.inport(ID::B, i);
int Y = mk.mux_gate(A, B, S);
@ -347,7 +347,7 @@ Aig::Aig(Cell *cell)
if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool)))
{
int Y = mk.inport(ID::A, 0);
for (int i = 1; i < GetSize(cell->getPort(ID::A)); i++) {
for (int i = 1; i < GetSize(cell->getPort(TW::A)); i++) {
int A = mk.inport(ID::A, i);
if (cell->type == ID($reduce_and)) Y = mk.and_gate(A, Y);
if (cell->type == ID($reduce_or)) Y = mk.or_gate(A, Y);
@ -358,7 +358,7 @@ Aig::Aig(Cell *cell)
if (cell->type == ID($reduce_xnor))
Y = mk.not_gate(Y);
mk.outport(Y, ID::Y, 0);
for (int i = 1; i < GetSize(cell->getPort(ID::Y)); i++)
for (int i = 1; i < GetSize(cell->getPort(TW::Y)); i++)
mk.outport(mk.bool_node(false), ID::Y, i);
goto optimize;
}
@ -366,11 +366,11 @@ Aig::Aig(Cell *cell)
if (cell->type.in(ID($logic_not), ID($logic_and), ID($logic_or)))
{
int A = mk.inport(ID::A, 0), Y = -1;
for (int i = 1; i < GetSize(cell->getPort(ID::A)); i++)
for (int i = 1; i < GetSize(cell->getPort(TW::A)); i++)
A = mk.or_gate(mk.inport(ID::A, i), A);
if (cell->type.in(ID($logic_and), ID($logic_or))) {
int B = mk.inport(ID::B, 0);
for (int i = 1; i < GetSize(cell->getPort(ID::B)); i++)
for (int i = 1; i < GetSize(cell->getPort(TW::B)); i++)
B = mk.or_gate(mk.inport(ID::B, i), B);
if (cell->type == ID($logic_and)) Y = mk.and_gate(A, B);
if (cell->type == ID($logic_or)) Y = mk.or_gate(A, B);
@ -383,7 +383,7 @@ Aig::Aig(Cell *cell)
if (cell->type.in(ID($add), ID($sub)))
{
int width = GetSize(cell->getPort(ID::Y));
int width = GetSize(cell->getPort(TW::Y));
vector<int> A = mk.inport_vec(ID::A, width);
vector<int> B = mk.inport_vec(ID::B, width);
int carry = mk.bool_node(false);
@ -399,8 +399,8 @@ Aig::Aig(Cell *cell)
if (cell->type.in(ID($lt), ID($gt), ID($le), ID($ge)))
{
int width = std::max(GetSize(cell->getPort(ID::A)),
GetSize(cell->getPort(ID::B))) + 1;
int width = std::max(GetSize(cell->getPort(TW::A)),
GetSize(cell->getPort(TW::B))) + 1;
vector<int> A = mk.inport_vec(ID::A, width);
vector<int> B = mk.inport_vec(ID::B, width);
@ -412,14 +412,14 @@ Aig::Aig(Cell *cell)
n = mk.not_gate(n);
vector<int> Y = mk.adder(A, B, carry);
mk.outport(Y.back(), ID::Y);
for (int i = 1; i < GetSize(cell->getPort(ID::Y)); i++)
for (int i = 1; i < GetSize(cell->getPort(TW::Y)); i++)
mk.outport(mk.bool_node(false), ID::Y, i);
goto optimize;
}
if (cell->type == ID($alu))
{
int width = GetSize(cell->getPort(ID::Y));
int width = GetSize(cell->getPort(TW::Y));
vector<int> A = mk.inport_vec(ID::A, width);
vector<int> B = mk.inport_vec(ID::B, width);
int carry = mk.inport(ID::CI);
@ -438,7 +438,7 @@ Aig::Aig(Cell *cell)
if (cell->type.in(ID($eq), ID($ne)))
{
int width = max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::B)));
int width = max(GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::B)));
vector<int> A = mk.inport_vec(ID::A, width);
vector<int> B = mk.inport_vec(ID::B, width);
int Y = mk.bool_node(false);

2
kernel/cellaigs.h
View File

@ -26,7 +26,7 @@ YOSYS_NAMESPACE_BEGIN
struct AigNode
{
IdString portname;
TwineRef portname;
int portbit;
bool inverter;
int left_parent, right_parent;

80
kernel/celledges.cc
View File

@ -25,8 +25,8 @@ PRIVATE_NAMESPACE_BEGIN
void bitwise_unary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
bool is_signed = (cell->type != ID($buf)) && cell->getParam(ID::A_SIGNED).as_bool();
int a_width = GetSize(cell->getPort(ID::A));
int y_width = GetSize(cell->getPort(ID::Y));
int a_width = GetSize(cell->getPort(TW::A));
int y_width = GetSize(cell->getPort(TW::Y));
for (int i = 0; i < y_width; i++)
{
@ -40,9 +40,9 @@ void bitwise_unary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
void bitwise_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
int a_width = GetSize(cell->getPort(ID::A));
int b_width = GetSize(cell->getPort(ID::B));
int y_width = GetSize(cell->getPort(ID::Y));
int a_width = GetSize(cell->getPort(TW::A));
int b_width = GetSize(cell->getPort(TW::B));
int y_width = GetSize(cell->getPort(TW::Y));
if (cell->type == ID($and) && !is_signed) {
if (a_width > b_width)
@ -68,8 +68,8 @@ void bitwise_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
void arith_neg_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
int a_width = GetSize(cell->getPort(ID::A));
int y_width = GetSize(cell->getPort(ID::Y));
int a_width = GetSize(cell->getPort(TW::A));
int y_width = GetSize(cell->getPort(TW::Y));
if (is_signed && a_width == 1)
y_width = std::min(y_width, 1);
@ -82,9 +82,9 @@ void arith_neg_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
void arith_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
int a_width = GetSize(cell->getPort(ID::A));
int b_width = GetSize(cell->getPort(ID::B));
int y_width = GetSize(cell->getPort(ID::Y));
int a_width = GetSize(cell->getPort(TW::A));
int b_width = GetSize(cell->getPort(TW::B));
int y_width = GetSize(cell->getPort(TW::Y));
if (!is_signed && cell->type != ID($sub)) {
int ab_width = std::max(a_width, b_width);
@ -106,7 +106,7 @@ void arith_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
void reduce_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
int a_width = GetSize(cell->getPort(ID::A));
int a_width = GetSize(cell->getPort(TW::A));
for (int i = 0; i < a_width; i++)
db->add_edge(cell, ID::A, i, ID::Y, 0, -1);
@ -114,8 +114,8 @@ void reduce_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
void logic_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
int a_width = GetSize(cell->getPort(ID::A));
int b_width = GetSize(cell->getPort(ID::B));
int a_width = GetSize(cell->getPort(TW::A));
int b_width = GetSize(cell->getPort(TW::B));
for (int i = 0; i < a_width; i++)
db->add_edge(cell, ID::A, i, ID::Y, 0, -1);
@ -125,8 +125,8 @@ void logic_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
void concat_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
int a_width = GetSize(cell->getPort(ID::A));
int b_width = GetSize(cell->getPort(ID::B));
int a_width = GetSize(cell->getPort(TW::A));
int b_width = GetSize(cell->getPort(TW::B));
for (int i = 0; i < a_width; i++)
db->add_edge(cell, ID::A, i, ID::Y, i, -1);
@ -137,8 +137,8 @@ void concat_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
void slice_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
int offset = cell->getParam(ID::OFFSET).as_int();
int a_width = GetSize(cell->getPort(ID::A));
int y_width = GetSize(cell->getPort(ID::Y));
int a_width = GetSize(cell->getPort(TW::A));
int y_width = GetSize(cell->getPort(TW::Y));
for (int i = 0; i < y_width; i++) {
int a_bit = offset + i;
@ -149,8 +149,8 @@ void slice_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
void compare_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
int a_width = GetSize(cell->getPort(ID::A));
int b_width = GetSize(cell->getPort(ID::B));
int a_width = GetSize(cell->getPort(TW::A));
int b_width = GetSize(cell->getPort(TW::B));
for (int i = 0; i < a_width; i++)
db->add_edge(cell, ID::A, i, ID::Y, 0, -1);
@ -161,9 +161,9 @@ void compare_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
void mux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
int a_width = GetSize(cell->getPort(ID::A));
int b_width = GetSize(cell->getPort(ID::B));
int s_width = GetSize(cell->getPort(ID::S));
int a_width = GetSize(cell->getPort(TW::A));
int b_width = GetSize(cell->getPort(TW::B));
int s_width = GetSize(cell->getPort(TW::S));
for (int i = 0; i < a_width; i++)
{
@ -179,9 +179,9 @@ void mux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
void bmux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
int width = GetSize(cell->getPort(ID::Y));
int a_width = GetSize(cell->getPort(ID::A));
int s_width = GetSize(cell->getPort(ID::S));
int width = GetSize(cell->getPort(TW::Y));
int a_width = GetSize(cell->getPort(TW::A));
int s_width = GetSize(cell->getPort(TW::S));
for (int i = 0; i < width; i++)
{
@ -195,9 +195,9 @@ void bmux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
void demux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
int width = GetSize(cell->getPort(ID::Y));
int a_width = GetSize(cell->getPort(ID::A));
int s_width = GetSize(cell->getPort(ID::S));
int width = GetSize(cell->getPort(TW::Y));
int a_width = GetSize(cell->getPort(TW::A));
int s_width = GetSize(cell->getPort(TW::S));
for (int i = 0; i < width; i++)
{
@ -211,9 +211,9 @@ void shift_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
bool is_b_signed = cell->getParam(ID::B_SIGNED).as_bool();
int a_width = GetSize(cell->getPort(ID::A));
int b_width = GetSize(cell->getPort(ID::B));
int y_width = GetSize(cell->getPort(ID::Y));
int a_width = GetSize(cell->getPort(TW::A));
int b_width = GetSize(cell->getPort(TW::B));
int y_width = GetSize(cell->getPort(TW::Y));
// Behavior of the different shift cells:
//
@ -397,7 +397,7 @@ void mem_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
void ff_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
int width = cell->getPort(ID::Q).size();
int width = cell->getPort(TW::Q).size();
if (cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr))) {
for (int k = 0; k < width; k++) {
@ -430,7 +430,7 @@ void full_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
for (auto &conn : cell->connections())
{
RTLIL::IdString port = conn.first;
TwineRef port = conn.first;
RTLIL::PortDir dir = cell->port_dir(port);
if (cell->input(port) || dir == RTLIL::PortDir::PD_INOUT)
input_ports.push_back(port);
@ -455,9 +455,9 @@ void full_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
void bweqx_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
int width = GetSize(cell->getPort(ID::Y));
int a_width = GetSize(cell->getPort(ID::A));
int b_width = GetSize(cell->getPort(ID::B));
int width = GetSize(cell->getPort(TW::Y));
int a_width = GetSize(cell->getPort(TW::A));
int b_width = GetSize(cell->getPort(TW::B));
int max_width = std::min(width, std::min(a_width, b_width));
for (int i = 0; i < max_width; i++) {
@ -468,10 +468,10 @@ void bweqx_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
void bwmux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
int width = GetSize(cell->getPort(ID::Y));
int a_width = GetSize(cell->getPort(ID::A));
int b_width = GetSize(cell->getPort(ID::B));
int s_width = GetSize(cell->getPort(ID::S));
int width = GetSize(cell->getPort(TW::Y));
int a_width = GetSize(cell->getPort(TW::A));
int b_width = GetSize(cell->getPort(TW::B));
int s_width = GetSize(cell->getPort(TW::S));
int max_width = std::min(width, std::min(a_width, std::min(b_width, s_width)));
for (int i = 0; i < max_width; i++) {

208
kernel/celltypes.h
View File

@ -28,7 +28,7 @@ YOSYS_NAMESPACE_BEGIN
struct CellType
{
RTLIL::IdString type;
pool<RTLIL::IdString> inputs, outputs;
pool<TwineRef> inputs, outputs;
bool is_evaluable;
bool is_combinatorial;
bool is_synthesizable;
@ -59,7 +59,7 @@ struct CellTypes
setup_stdcells_mem();
}
void setup_type(RTLIL::IdString type, const pool<RTLIL::IdString> &inputs, const pool<RTLIL::IdString> &outputs, bool is_evaluable = false, bool is_combinatorial = false, bool is_synthesizable = false)
void setup_type(RTLIL::IdString type, const pool<TwineRef> &inputs, const pool<TwineRef> &outputs, bool is_evaluable = false, bool is_combinatorial = false, bool is_synthesizable = false)
{
CellType ct = {type, inputs, outputs, is_evaluable, is_combinatorial, is_synthesizable};
cell_types[ct.type] = ct;
@ -67,13 +67,13 @@ struct CellTypes
void setup_module(RTLIL::Module *module)
{
pool<RTLIL::IdString> inputs, outputs;
pool<TwineRef> inputs, outputs;
for (auto wire_name : module->ports) {
RTLIL::Wire *wire = module->wire(wire_name);
if (wire->port_input)
inputs.insert(wire->name);
inputs.insert(wire->meta_->name);
if (wire->port_output)
outputs.insert(wire->name);
outputs.insert(wire->meta_->name);
}
setup_type(module->name, inputs, outputs);
}
@ -88,34 +88,34 @@ struct CellTypes
{
setup_internals_eval();
setup_type(ID($tribuf), {ID::A, ID::EN}, {ID::Y});
setup_type(ID($tribuf), {TW::A, TW::EN}, {TW::Y});
setup_type(ID($assert), {ID::A, ID::EN}, pool<RTLIL::IdString>());
setup_type(ID($assume), {ID::A, ID::EN}, pool<RTLIL::IdString>());
setup_type(ID($live), {ID::A, ID::EN}, pool<RTLIL::IdString>());
setup_type(ID($fair), {ID::A, ID::EN}, pool<RTLIL::IdString>());
setup_type(ID($cover), {ID::A, ID::EN}, pool<RTLIL::IdString>());
setup_type(ID($initstate), pool<RTLIL::IdString>(), {ID::Y});
setup_type(ID($anyconst), pool<RTLIL::IdString>(), {ID::Y});
setup_type(ID($anyseq), pool<RTLIL::IdString>(), {ID::Y});
setup_type(ID($allconst), pool<RTLIL::IdString>(), {ID::Y});
setup_type(ID($allseq), pool<RTLIL::IdString>(), {ID::Y});
setup_type(ID($equiv), {ID::A, ID::B}, {ID::Y});
setup_type(ID($specify2), {ID::EN, ID::SRC, ID::DST}, pool<RTLIL::IdString>());
setup_type(ID($specify3), {ID::EN, ID::SRC, ID::DST, ID::DAT}, pool<RTLIL::IdString>());
setup_type(ID($specrule), {ID::SRC_EN, ID::DST_EN, ID::SRC, ID::DST}, pool<RTLIL::IdString>());
setup_type(ID($print), {ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());
setup_type(ID($check), {ID::A, ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());
setup_type(ID($set_tag), {ID::A, ID::SET, ID::CLR}, {ID::Y});
setup_type(ID($get_tag), {ID::A}, {ID::Y});
setup_type(ID($overwrite_tag), {ID::A, ID::SET, ID::CLR}, pool<RTLIL::IdString>());
setup_type(ID($original_tag), {ID::A}, {ID::Y});
setup_type(ID($future_ff), {ID::A}, {ID::Y});
setup_type(ID($assert), {TW::A, TW::EN}, pool<TwineRef>());
setup_type(ID($assume), {TW::A, TW::EN}, pool<TwineRef>());
setup_type(ID($live), {TW::A, TW::EN}, pool<TwineRef>());
setup_type(ID($fair), {TW::A, TW::EN}, pool<TwineRef>());
setup_type(ID($cover), {TW::A, TW::EN}, pool<TwineRef>());
setup_type(ID($initstate), pool<TwineRef>(), {TW::Y});
setup_type(ID($anyconst), pool<TwineRef>(), {TW::Y});
setup_type(ID($anyseq), pool<TwineRef>(), {TW::Y});
setup_type(ID($allconst), pool<TwineRef>(), {TW::Y});
setup_type(ID($allseq), pool<TwineRef>(), {TW::Y});
setup_type(ID($equiv), {TW::A, TW::B}, {TW::Y});
setup_type(ID($specify2), {TW::EN, TW::SRC, TW::DST}, pool<TwineRef>());
setup_type(ID($specify3), {TW::EN, TW::SRC, TW::DST, TW::DAT}, pool<TwineRef>());
setup_type(ID($specrule), {TW::SRC_EN, TW::DST_EN, TW::SRC, TW::DST}, pool<TwineRef>());
setup_type(ID($print), {TW::EN, TW::ARGS, TW::TRG}, pool<TwineRef>());
setup_type(ID($check), {TW::A, TW::EN, TW::ARGS, TW::TRG}, pool<TwineRef>());
setup_type(ID($set_tag), {TW::A, TW::SET, TW::CLR}, {TW::Y});
setup_type(ID($get_tag), {TW::A}, {TW::Y});
setup_type(ID($overwrite_tag), {TW::A, TW::SET, TW::CLR}, pool<TwineRef>());
setup_type(ID($original_tag), {TW::A}, {TW::Y});
setup_type(ID($future_ff), {TW::A}, {TW::Y});
setup_type(ID($scopeinfo), {}, {});
setup_type(ID($input_port), {}, {ID::Y});
setup_type(ID($output_port), {ID::A}, {});
setup_type(ID($public), {ID::A}, {});
setup_type(ID($connect), {ID::A, ID::B}, {});
setup_type(ID($input_port), {}, {TW::Y});
setup_type(ID($output_port), {TW::A}, {});
setup_type(ID($public), {TW::A}, {});
setup_type(ID($connect), {TW::A, TW::B}, {});
}
void setup_internals_eval()
@ -136,92 +136,92 @@ struct CellTypes
};
for (auto type : unary_ops)
setup_type(type, {ID::A}, {ID::Y}, true);
setup_type(type, {TW::A}, {TW::Y}, true);
for (auto type : binary_ops)
setup_type(type, {ID::A, ID::B}, {ID::Y}, true);
setup_type(type, {TW::A, TW::B}, {TW::Y}, true);
for (auto type : std::vector<RTLIL::IdString>({ID($mux), ID($pmux), ID($bwmux)}))
setup_type(type, {ID::A, ID::B, ID::S}, {ID::Y}, true);
setup_type(type, {TW::A, TW::B, TW::S}, {TW::Y}, true);
for (auto type : std::vector<RTLIL::IdString>({ID($bmux), ID($demux)}))
setup_type(type, {ID::A, ID::S}, {ID::Y}, true);
setup_type(type, {TW::A, TW::S}, {TW::Y}, true);
setup_type(ID($lcu), {ID::P, ID::G, ID::CI}, {ID::CO}, true);
setup_type(ID($alu), {ID::A, ID::B, ID::CI, ID::BI}, {ID::X, ID::Y, ID::CO}, true);
setup_type(ID($macc_v2), {ID::A, ID::B, ID::C}, {ID::Y}, true);
setup_type(ID($fa), {ID::A, ID::B, ID::C}, {ID::X, ID::Y}, true);
setup_type(ID($lcu), {TW::P, TW::G, TW::CI}, {TW::CO}, true);
setup_type(ID($alu), {TW::A, TW::B, TW::CI, TW::BI}, {TW::X, TW::Y, TW::CO}, true);
setup_type(ID($macc_v2), {TW::A, TW::B, TW::C}, {TW::Y}, true);
setup_type(ID($fa), {TW::A, TW::B, TW::C}, {TW::X, TW::Y}, true);
}
void setup_internals_ff()
{
setup_type(ID($sr), {ID::SET, ID::CLR}, {ID::Q});
setup_type(ID($ff), {ID::D}, {ID::Q});
setup_type(ID($dff), {ID::CLK, ID::D}, {ID::Q});
setup_type(ID($dffe), {ID::CLK, ID::EN, ID::D}, {ID::Q});
setup_type(ID($dffsr), {ID::CLK, ID::SET, ID::CLR, ID::D}, {ID::Q});
setup_type(ID($dffsre), {ID::CLK, ID::SET, ID::CLR, ID::D, ID::EN}, {ID::Q});
setup_type(ID($adff), {ID::CLK, ID::ARST, ID::D}, {ID::Q});
setup_type(ID($adffe), {ID::CLK, ID::ARST, ID::D, ID::EN}, {ID::Q});
setup_type(ID($aldff), {ID::CLK, ID::ALOAD, ID::AD, ID::D}, {ID::Q});
setup_type(ID($aldffe), {ID::CLK, ID::ALOAD, ID::AD, ID::D, ID::EN}, {ID::Q});
setup_type(ID($sdff), {ID::CLK, ID::SRST, ID::D}, {ID::Q});
setup_type(ID($sdffe), {ID::CLK, ID::SRST, ID::D, ID::EN}, {ID::Q});
setup_type(ID($sdffce), {ID::CLK, ID::SRST, ID::D, ID::EN}, {ID::Q});
setup_type(ID($dlatch), {ID::EN, ID::D}, {ID::Q});
setup_type(ID($adlatch), {ID::EN, ID::D, ID::ARST}, {ID::Q});
setup_type(ID($dlatchsr), {ID::EN, ID::SET, ID::CLR, ID::D}, {ID::Q});
setup_type(ID($sr), {TW::SET, TW::CLR}, {TW::Q});
setup_type(ID($ff), {TW::D}, {TW::Q});
setup_type(ID($dff), {TW::CLK, TW::D}, {TW::Q});
setup_type(ID($dffe), {TW::CLK, TW::EN, TW::D}, {TW::Q});
setup_type(ID($dffsr), {TW::CLK, TW::SET, TW::CLR, TW::D}, {TW::Q});
setup_type(ID($dffsre), {TW::CLK, TW::SET, TW::CLR, TW::D, TW::EN}, {TW::Q});
setup_type(ID($adff), {TW::CLK, TW::ARST, TW::D}, {TW::Q});
setup_type(ID($adffe), {TW::CLK, TW::ARST, TW::D, TW::EN}, {TW::Q});
setup_type(ID($aldff), {TW::CLK, TW::ALOAD, TW::AD, TW::D}, {TW::Q});
setup_type(ID($aldffe), {TW::CLK, TW::ALOAD, TW::AD, TW::D, TW::EN}, {TW::Q});
setup_type(ID($sdff), {TW::CLK, TW::SRST, TW::D}, {TW::Q});
setup_type(ID($sdffe), {TW::CLK, TW::SRST, TW::D, TW::EN}, {TW::Q});
setup_type(ID($sdffce), {TW::CLK, TW::SRST, TW::D, TW::EN}, {TW::Q});
setup_type(ID($dlatch), {TW::EN, TW::D}, {TW::Q});
setup_type(ID($adlatch), {TW::EN, TW::D, TW::ARST}, {TW::Q});
setup_type(ID($dlatchsr), {TW::EN, TW::SET, TW::CLR, TW::D}, {TW::Q});
}
void setup_internals_anyinit()
{
setup_type(ID($anyinit), {ID::D}, {ID::Q});
setup_type(ID($anyinit), {TW::D}, {TW::Q});
}
void setup_internals_mem()
{
setup_internals_ff();
setup_type(ID($memrd), {ID::CLK, ID::EN, ID::ADDR}, {ID::DATA});
setup_type(ID($memrd_v2), {ID::CLK, ID::EN, ID::ARST, ID::SRST, ID::ADDR}, {ID::DATA});
setup_type(ID($memwr), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());
setup_type(ID($memwr_v2), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());
setup_type(ID($meminit), {ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());
setup_type(ID($meminit_v2), {ID::ADDR, ID::DATA, ID::EN}, pool<RTLIL::IdString>());
setup_type(ID($mem), {ID::RD_CLK, ID::RD_EN, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA});
setup_type(ID($mem_v2), {ID::RD_CLK, ID::RD_EN, ID::RD_ARST, ID::RD_SRST, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA});
setup_type(ID($memrd), {TW::CLK, TW::EN, TW::ADDR}, {TW::DATA});
setup_type(ID($memrd_v2), {TW::CLK, TW::EN, TW::ARST, TW::SRST, TW::ADDR}, {TW::DATA});
setup_type(ID($memwr), {TW::CLK, TW::EN, TW::ADDR, TW::DATA}, pool<TwineRef>());
setup_type(ID($memwr_v2), {TW::CLK, TW::EN, TW::ADDR, TW::DATA}, pool<TwineRef>());
setup_type(ID($meminit), {TW::ADDR, TW::DATA}, pool<TwineRef>());
setup_type(ID($meminit_v2), {TW::ADDR, TW::DATA, TW::EN}, pool<TwineRef>());
setup_type(ID($mem), {TW::RD_CLK, TW::RD_EN, TW::RD_ADDR, TW::WR_CLK, TW::WR_EN, TW::WR_ADDR, TW::WR_DATA}, {TW::RD_DATA});
setup_type(ID($mem_v2), {TW::RD_CLK, TW::RD_EN, TW::RD_ARST, TW::RD_SRST, TW::RD_ADDR, TW::WR_CLK, TW::WR_EN, TW::WR_ADDR, TW::WR_DATA}, {TW::RD_DATA});
setup_type(ID($fsm), {ID::CLK, ID::ARST, ID::CTRL_IN}, {ID::CTRL_OUT});
setup_type(ID($fsm), {TW::CLK, TW::ARST, TW::CTRL_IN}, {TW::CTRL_OUT});
}
void setup_stdcells()
{
setup_stdcells_eval();
setup_type(ID($_TBUF_), {ID::A, ID::E}, {ID::Y});
setup_type(ID($_TBUF_), {TW::A, TW::E}, {TW::Y});
}
void setup_stdcells_eval()
{
setup_type(ID($_BUF_), {ID::A}, {ID::Y}, true);
setup_type(ID($_NOT_), {ID::A}, {ID::Y}, true);
setup_type(ID($_AND_), {ID::A, ID::B}, {ID::Y}, true);
setup_type(ID($_NAND_), {ID::A, ID::B}, {ID::Y}, true);
setup_type(ID($_OR_), {ID::A, ID::B}, {ID::Y}, true);
setup_type(ID($_NOR_), {ID::A, ID::B}, {ID::Y}, true);
setup_type(ID($_XOR_), {ID::A, ID::B}, {ID::Y}, true);
setup_type(ID($_XNOR_), {ID::A, ID::B}, {ID::Y}, true);
setup_type(ID($_ANDNOT_), {ID::A, ID::B}, {ID::Y}, true);
setup_type(ID($_ORNOT_), {ID::A, ID::B}, {ID::Y}, true);
setup_type(ID($_MUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true);
setup_type(ID($_NMUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true);
setup_type(ID($_MUX4_), {ID::A, ID::B, ID::C, ID::D, ID::S, ID::T}, {ID::Y}, true);
setup_type(ID($_MUX8_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::S, ID::T, ID::U}, {ID::Y}, true);
setup_type(ID($_MUX16_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::I, ID::J, ID::K, ID::L, ID::M, ID::N, ID::O, ID::P, ID::S, ID::T, ID::U, ID::V}, {ID::Y}, true);
setup_type(ID($_AOI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true);
setup_type(ID($_OAI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true);
setup_type(ID($_AOI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true);
setup_type(ID($_OAI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true);
setup_type(ID($_BUF_), {TW::A}, {TW::Y}, true);
setup_type(ID($_NOT_), {TW::A}, {TW::Y}, true);
setup_type(ID($_AND_), {TW::A, TW::B}, {TW::Y}, true);
setup_type(ID($_NAND_), {TW::A, TW::B}, {TW::Y}, true);
setup_type(ID($_OR_), {TW::A, TW::B}, {TW::Y}, true);
setup_type(ID($_NOR_), {TW::A, TW::B}, {TW::Y}, true);
setup_type(ID($_XOR_), {TW::A, TW::B}, {TW::Y}, true);
setup_type(ID($_XNOR_), {TW::A, TW::B}, {TW::Y}, true);
setup_type(ID($_ANDNOT_), {TW::A, TW::B}, {TW::Y}, true);
setup_type(ID($_ORNOT_), {TW::A, TW::B}, {TW::Y}, true);
setup_type(ID($_MUX_), {TW::A, TW::B, TW::S}, {TW::Y}, true);
setup_type(ID($_NMUX_), {TW::A, TW::B, TW::S}, {TW::Y}, true);
setup_type(ID($_MUX4_), {TW::A, TW::B, TW::C, TW::D, TW::S, TW::T}, {TW::Y}, true);
setup_type(ID($_MUX8_), {TW::A, TW::B, TW::C, TW::D, TW::E, TW::F, TW::G, TW::H, TW::S, TW::T, TW::U}, {TW::Y}, true);
setup_type(ID($_MUX16_), {TW::A, TW::B, TW::C, TW::D, TW::E, TW::F, TW::G, TW::H, TW::I, TW::J, TW::K, TW::L, TW::M, TW::N, TW::O, TW::P, TW::S, TW::T, TW::U, TW::V}, {TW::Y}, true);
setup_type(ID($_AOI3_), {TW::A, TW::B, TW::C}, {TW::Y}, true);
setup_type(ID($_OAI3_), {TW::A, TW::B, TW::C}, {TW::Y}, true);
setup_type(ID($_AOI4_), {TW::A, TW::B, TW::C, TW::D}, {TW::Y}, true);
setup_type(ID($_OAI4_), {TW::A, TW::B, TW::C, TW::D}, {TW::Y}, true);
}
void setup_stdcells_mem()
@ -230,77 +230,77 @@ struct CellTypes
for (auto c1 : list_np)
for (auto c2 : list_np)
setup_type(stringf("$_SR_%c%c_", c1, c2), {ID::S, ID::R}, {ID::Q});
setup_type(stringf("$_SR_%c%c_", c1, c2), {TW::S, TW::R}, {TW::Q});
setup_type(ID($_FF_), {ID::D}, {ID::Q});
setup_type(ID($_FF_), {TW::D}, {TW::Q});
for (auto c1 : list_np)
setup_type(stringf("$_DFF_%c_", c1), {ID::C, ID::D}, {ID::Q});
setup_type(stringf("$_DFF_%c_", c1), {TW::C, TW::D}, {TW::Q});
for (auto c1 : list_np)
for (auto c2 : list_np)
setup_type(stringf("$_DFFE_%c%c_", c1, c2), {ID::C, ID::D, ID::E}, {ID::Q});
setup_type(stringf("$_DFFE_%c%c_", c1, c2), {TW::C, TW::D, TW::E}, {TW::Q});
for (auto c1 : list_np)
for (auto c2 : list_np)
for (auto c3 : list_01)
setup_type(stringf("$_DFF_%c%c%c_", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q});
setup_type(stringf("$_DFF_%c%c%c_", c1, c2, c3), {TW::C, TW::R, TW::D}, {TW::Q});
for (auto c1 : list_np)
for (auto c2 : list_np)
for (auto c3 : list_01)
for (auto c4 : list_np)
setup_type(stringf("$_DFFE_%c%c%c%c_", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});
setup_type(stringf("$_DFFE_%c%c%c%c_", c1, c2, c3, c4), {TW::C, TW::R, TW::D, TW::E}, {TW::Q});
for (auto c1 : list_np)
for (auto c2 : list_np)
setup_type(stringf("$_ALDFF_%c%c_", c1, c2), {ID::C, ID::L, ID::AD, ID::D}, {ID::Q});
setup_type(stringf("$_ALDFF_%c%c_", c1, c2), {TW::C, TW::L, TW::AD, TW::D}, {TW::Q});
for (auto c1 : list_np)
for (auto c2 : list_np)
for (auto c3 : list_np)
setup_type(stringf("$_ALDFFE_%c%c%c_", c1, c2, c3), {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q});
setup_type(stringf("$_ALDFFE_%c%c%c_", c1, c2, c3), {TW::C, TW::L, TW::AD, TW::D, TW::E}, {TW::Q});
for (auto c1 : list_np)
for (auto c2 : list_np)
for (auto c3 : list_np)
setup_type(stringf("$_DFFSR_%c%c%c_", c1, c2, c3), {ID::C, ID::S, ID::R, ID::D}, {ID::Q});
setup_type(stringf("$_DFFSR_%c%c%c_", c1, c2, c3), {TW::C, TW::S, TW::R, TW::D}, {TW::Q});
for (auto c1 : list_np)
for (auto c2 : list_np)
for (auto c3 : list_np)
for (auto c4 : list_np)
setup_type(stringf("$_DFFSRE_%c%c%c%c_", c1, c2, c3, c4), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q});
setup_type(stringf("$_DFFSRE_%c%c%c%c_", c1, c2, c3, c4), {TW::C, TW::S, TW::R, TW::D, TW::E}, {TW::Q});
for (auto c1 : list_np)
for (auto c2 : list_np)
for (auto c3 : list_01)
setup_type(stringf("$_SDFF_%c%c%c_", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q});
setup_type(stringf("$_SDFF_%c%c%c_", c1, c2, c3), {TW::C, TW::R, TW::D}, {TW::Q});
for (auto c1 : list_np)
for (auto c2 : list_np)
for (auto c3 : list_01)
for (auto c4 : list_np)
setup_type(stringf("$_SDFFE_%c%c%c%c_", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});
setup_type(stringf("$_SDFFE_%c%c%c%c_", c1, c2, c3, c4), {TW::C, TW::R, TW::D, TW::E}, {TW::Q});
for (auto c1 : list_np)
for (auto c2 : list_np)
for (auto c3 : list_01)
for (auto c4 : list_np)
setup_type(stringf("$_SDFFCE_%c%c%c%c_", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});
setup_type(stringf("$_SDFFCE_%c%c%c%c_", c1, c2, c3, c4), {TW::C, TW::R, TW::D, TW::E}, {TW::Q});
for (auto c1 : list_np)
setup_type(stringf("$_DLATCH_%c_", c1), {ID::E, ID::D}, {ID::Q});
setup_type(stringf("$_DLATCH_%c_", c1), {TW::E, TW::D}, {TW::Q});
for (auto c1 : list_np)
for (auto c2 : list_np)
for (auto c3 : list_01)
setup_type(stringf("$_DLATCH_%c%c%c_", c1, c2, c3), {ID::E, ID::R, ID::D}, {ID::Q});
setup_type(stringf("$_DLATCH_%c%c%c_", c1, c2, c3), {TW::E, TW::R, TW::D}, {TW::Q});
for (auto c1 : list_np)
for (auto c2 : list_np)
for (auto c3 : list_np)
setup_type(stringf("$_DLATCHSR_%c%c%c_", c1, c2, c3), {ID::E, ID::S, ID::R, ID::D}, {ID::Q});
setup_type(stringf("$_DLATCHSR_%c%c%c_", c1, c2, c3), {TW::E, TW::S, TW::R, TW::D}, {TW::Q});
}
void clear()
@ -313,19 +313,19 @@ struct CellTypes
return cell_types.count(type) != 0;
}
bool cell_output(RTLIL::IdString type, RTLIL::IdString port) const
bool cell_output(RTLIL::IdString type, TwineRef port) const
{
auto it = cell_types.find(type);
return it != cell_types.end() && it->second.outputs.count(port) != 0;
}
bool cell_input(RTLIL::IdString type, RTLIL::IdString port) const
bool cell_input(RTLIL::IdString type, TwineRef port) const
{
auto it = cell_types.find(type);
return it != cell_types.end() && it->second.inputs.count(port) != 0;
}
RTLIL::PortDir cell_port_dir(RTLIL::IdString type, RTLIL::IdString port) const
RTLIL::PortDir cell_port_dir(RTLIL::IdString type, TwineRef port) const
{
auto it = cell_types.find(type);
if (it == cell_types.end())

36
kernel/consteval.h
View File

@ -95,10 +95,10 @@ struct ConstEval
{
if (cell->type == ID($lcu))
{
RTLIL::SigSpec sig_p = cell->getPort(ID::P);
RTLIL::SigSpec sig_g = cell->getPort(ID::G);
RTLIL::SigSpec sig_ci = cell->getPort(ID::CI);
RTLIL::SigSpec sig_co = values_map(assign_map(cell->getPort(ID::CO)));
RTLIL::SigSpec sig_p = cell->getPort(TW::P);
RTLIL::SigSpec sig_g = cell->getPort(TW::G);
RTLIL::SigSpec sig_ci = cell->getPort(TW::CI);
RTLIL::SigSpec sig_co = values_map(assign_map(cell->getPort(TW::CO)));
if (sig_co.is_fully_const())
return true;
@ -133,19 +133,19 @@ struct ConstEval
RTLIL::SigSpec sig_a, sig_b, sig_s, sig_y;
log_assert(cell->hasPort(ID::Y));
sig_y = values_map(assign_map(cell->getPort(ID::Y)));
sig_y = values_map(assign_map(cell->getPort(TW::Y)));
if (sig_y.is_fully_const())
return true;
if (cell->hasPort(ID::S)) {
sig_s = cell->getPort(ID::S);
sig_s = cell->getPort(TW::S);
}
if (cell->hasPort(ID::A))
sig_a = cell->getPort(ID::A);
sig_a = cell->getPort(TW::A);
if (cell->hasPort(ID::B))
sig_b = cell->getPort(ID::B);
sig_b = cell->getPort(TW::B);
if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_), ID($_NMUX_)))
{
@ -231,8 +231,8 @@ struct ConstEval
}
else if (cell->type == ID($fa))
{
RTLIL::SigSpec sig_c = cell->getPort(ID::C);
RTLIL::SigSpec sig_x = cell->getPort(ID::X);
RTLIL::SigSpec sig_c = cell->getPort(TW::C);
RTLIL::SigSpec sig_x = cell->getPort(TW::X);
int width = GetSize(sig_c);
if (!eval(sig_a, undef, cell))
@ -263,8 +263,8 @@ struct ConstEval
bool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();
bool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool();
RTLIL::SigSpec sig_ci = cell->getPort(ID::CI);
RTLIL::SigSpec sig_bi = cell->getPort(ID::BI);
RTLIL::SigSpec sig_ci = cell->getPort(TW::CI);
RTLIL::SigSpec sig_bi = cell->getPort(TW::BI);
if (!eval(sig_a, undef, cell))
return false;
@ -278,8 +278,8 @@ struct ConstEval
if (!eval(sig_bi, undef, cell))
return false;
RTLIL::SigSpec sig_x = cell->getPort(ID::X);
RTLIL::SigSpec sig_co = cell->getPort(ID::CO);
RTLIL::SigSpec sig_x = cell->getPort(TW::X);
RTLIL::SigSpec sig_co = cell->getPort(TW::CO);
bool any_input_undef = !(sig_a.is_fully_def() && sig_b.is_fully_def() && sig_ci.is_fully_def() && sig_bi.is_fully_def());
sig_a.extend_u0(GetSize(sig_y), signed_a);
@ -326,11 +326,11 @@ struct ConstEval
return false;
}
RTLIL::Const result(0, GetSize(cell->getPort(ID::Y)));
RTLIL::Const result(0, GetSize(cell->getPort(TW::Y)));
if (!macc.eval(result))
log_abort();
set(cell->getPort(ID::Y), result);
set(cell->getPort(TW::Y), result);
}
else
{
@ -338,9 +338,9 @@ struct ConstEval
if (cell->type.in(ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) {
if (cell->hasPort(ID::C))
sig_c = cell->getPort(ID::C);
sig_c = cell->getPort(TW::C);
if (cell->hasPort(ID::D))
sig_d = cell->getPort(ID::D);
sig_d = cell->getPort(TW::D);
}
if (sig_a.size() > 0 && !eval(sig_a, undef, cell))

2
kernel/cost.cc
View File

@ -124,7 +124,7 @@ unsigned int max_inp_width(RTLIL::Cell *cell)
unsigned int port_width_sum(RTLIL::Cell *cell)
{
unsigned int sum = 0;
RTLIL::IdString port_width_params[] = {
TwineRef port_width_params[] = {
ID::WIDTH, ID::A_WIDTH, ID::B_WIDTH, ID::S_WIDTH, ID::Y_WIDTH,
};

136
kernel/ff.cc
View File

@ -36,7 +36,7 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
type = flop->type;
}
if constexpr (have_cell) {
info.sig_q = cell->getPort(ID::Q);
info.sig_q = cell->getPort(TW::Q);
info.width = GetSize(info.sig_q);
info.attributes = cell->attributes;
// Carry src across construction → emit() as an owning Twine
@ -58,7 +58,7 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
if (type.in(ID($anyinit), ID($ff))) {
info.has_gclk = true;
if constexpr (have_cell)
info.sig_d = cell->getPort(ID::D);
info.sig_d = cell->getPort(TW::D);
if (type == ID($anyinit)) {
info.is_anyinit = true;
if constexpr (have_cell)
@ -69,30 +69,30 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
} else if (type.in(ID($dlatch), ID($adlatch), ID($dlatchsr))) {
info.has_aload = true;
if constexpr (have_cell) {
info.sig_aload = cell->getPort(ID::EN);
info.sig_aload = cell->getPort(TW::EN);
info.pol_aload = cell->getParam(ID::EN_POLARITY).as_bool();
info.sig_ad = cell->getPort(ID::D);
info.sig_ad = cell->getPort(TW::D);
}
} else {
info.has_clk = true;
if constexpr (have_cell) {
info.sig_clk = cell->getPort(ID::CLK);
info.sig_clk = cell->getPort(TW::CLK);
info.pol_clk = cell->getParam(ID::CLK_POLARITY).as_bool();
info.sig_d = cell->getPort(ID::D);
info.sig_d = cell->getPort(TW::D);
}
}
if (type.in(ID($dffe), ID($dffsre), ID($adffe), ID($aldffe), ID($sdffe), ID($sdffce))) {
info.has_ce = true;
if constexpr (have_cell) {
info.sig_ce = cell->getPort(ID::EN);
info.sig_ce = cell->getPort(TW::EN);
info.pol_ce = cell->getParam(ID::EN_POLARITY).as_bool();
}
}
if (type.in(ID($dffsr), ID($dffsre), ID($dlatchsr), ID($sr))) {
info.has_sr = true;
if constexpr (have_cell) {
info.sig_clr = cell->getPort(ID::CLR);
info.sig_set = cell->getPort(ID::SET);
info.sig_clr = cell->getPort(TW::CLR);
info.sig_set = cell->getPort(TW::SET);
info.pol_clr = cell->getParam(ID::CLR_POLARITY).as_bool();
info.pol_set = cell->getParam(ID::SET_POLARITY).as_bool();
}
@ -100,15 +100,15 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
if (type.in(ID($aldff), ID($aldffe))) {
info.has_aload = true;
if constexpr (have_cell) {
info.sig_aload = cell->getPort(ID::ALOAD);
info.sig_aload = cell->getPort(TW::ALOAD);
info.pol_aload = cell->getParam(ID::ALOAD_POLARITY).as_bool();
info.sig_ad = cell->getPort(ID::AD);
info.sig_ad = cell->getPort(TW::AD);
}
}
if (type.in(ID($adff), ID($adffe), ID($adlatch))) {
info.has_arst = true;
if constexpr (have_cell) {
info.sig_arst = cell->getPort(ID::ARST);
info.sig_arst = cell->getPort(TW::ARST);
info.pol_arst = cell->getParam(ID::ARST_POLARITY).as_bool();
info.val_arst = cell->getParam(ID::ARST_VALUE);
}
@ -116,7 +116,7 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
if (type.in(ID($sdff), ID($sdffe), ID($sdffce))) {
info.has_srst = true;
if constexpr (have_cell) {
info.sig_srst = cell->getPort(ID::SRST);
info.sig_srst = cell->getPort(TW::SRST);
info.pol_srst = cell->getParam(ID::SRST_POLARITY).as_bool();
info.val_srst = cell->getParam(ID::SRST_VALUE);
}
@ -126,23 +126,23 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
info.is_fine = true;
info.has_gclk = true;
if constexpr (have_cell)
info.sig_d = cell->getPort(ID::D);
info.sig_d = cell->getPort(TW::D);
} else if (type_str.substr(0, 5) == "$_SR_") {
info.is_fine = true;
info.has_sr = true;
info.pol_set = type_str[5] == 'P';
info.pol_clr = type_str[6] == 'P';
if constexpr (have_cell) {
info.sig_set = cell->getPort(ID::S);
info.sig_clr = cell->getPort(ID::R);
info.sig_set = cell->getPort(TW::S);
info.sig_clr = cell->getPort(TW::R);
}
} else if (type_str.substr(0, 6) == "$_DFF_" && type_str.size() == 8) {
info.is_fine = true;
info.has_clk = true;
info.pol_clk = type_str[6] == 'P';
if constexpr (have_cell) {
info.sig_d = cell->getPort(ID::D);
info.sig_clk = cell->getPort(ID::C);
info.sig_d = cell->getPort(TW::D);
info.sig_clk = cell->getPort(TW::C);
}
} else if (type_str.substr(0, 7) == "$_DFFE_" && type_str.size() == 10) {
info.is_fine = true;
@ -151,9 +151,9 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
info.has_ce = true;
info.pol_ce = type_str[8] == 'P';
if constexpr (have_cell) {
info.sig_d = cell->getPort(ID::D);
info.sig_clk = cell->getPort(ID::C);
info.sig_ce = cell->getPort(ID::E);
info.sig_d = cell->getPort(TW::D);
info.sig_clk = cell->getPort(TW::C);
info.sig_ce = cell->getPort(TW::E);
}
} else if (type_str.substr(0, 6) == "$_DFF_" && type_str.size() == 10) {
info.is_fine = true;
@ -163,9 +163,9 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
info.pol_arst = type_str[7] == 'P';
info.val_arst = type_str[8] == '1' ? State::S1 : State::S0;
if constexpr (have_cell) {
info.sig_d = cell->getPort(ID::D);
info.sig_clk = cell->getPort(ID::C);
info.sig_arst = cell->getPort(ID::R);
info.sig_d = cell->getPort(TW::D);
info.sig_clk = cell->getPort(TW::C);
info.sig_arst = cell->getPort(TW::R);
}
} else if (type_str.substr(0, 7) == "$_DFFE_" && type_str.size() == 12) {
info.is_fine = true;
@ -177,10 +177,10 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
info.has_ce = true;
info.pol_ce = type_str[10] == 'P';
if constexpr (have_cell) {
info.sig_d = cell->getPort(ID::D);
info.sig_clk = cell->getPort(ID::C);
info.sig_arst = cell->getPort(ID::R);
info.sig_ce = cell->getPort(ID::E);
info.sig_d = cell->getPort(TW::D);
info.sig_clk = cell->getPort(TW::C);
info.sig_arst = cell->getPort(TW::R);
info.sig_ce = cell->getPort(TW::E);
}
} else if (type_str.substr(0, 8) == "$_ALDFF_" && type_str.size() == 11) {
info.is_fine = true;
@ -189,10 +189,10 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
info.has_aload = true;
info.pol_aload = type_str[9] == 'P';
if constexpr (have_cell) {
info.sig_d = cell->getPort(ID::D);
info.sig_clk = cell->getPort(ID::C);
info.sig_aload = cell->getPort(ID::L);
info.sig_ad = cell->getPort(ID::AD);
info.sig_d = cell->getPort(TW::D);
info.sig_clk = cell->getPort(TW::C);
info.sig_aload = cell->getPort(TW::L);
info.sig_ad = cell->getPort(TW::AD);
}
} else if (type_str.substr(0, 9) == "$_ALDFFE_" && type_str.size() == 13) {
info.is_fine = true;
@ -203,11 +203,11 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
info.has_ce = true;
info.pol_ce = type_str[11] == 'P';
if constexpr (have_cell) {
info.sig_d = cell->getPort(ID::D);
info.sig_clk = cell->getPort(ID::C);
info.sig_aload = cell->getPort(ID::L);
info.sig_ad = cell->getPort(ID::AD);
info.sig_ce = cell->getPort(ID::E);
info.sig_d = cell->getPort(TW::D);
info.sig_clk = cell->getPort(TW::C);
info.sig_aload = cell->getPort(TW::L);
info.sig_ad = cell->getPort(TW::AD);
info.sig_ce = cell->getPort(TW::E);
}
} else if (type_str.substr(0, 8) == "$_DFFSR_" && type_str.size() == 12) {
info.is_fine = true;
@ -217,10 +217,10 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
info.pol_set = type_str[9] == 'P';
info.pol_clr = type_str[10] == 'P';
if constexpr (have_cell) {
info.sig_d = cell->getPort(ID::D);
info.sig_clk = cell->getPort(ID::C);
info.sig_set = cell->getPort(ID::S);
info.sig_clr = cell->getPort(ID::R);
info.sig_d = cell->getPort(TW::D);
info.sig_clk = cell->getPort(TW::C);
info.sig_set = cell->getPort(TW::S);
info.sig_clr = cell->getPort(TW::R);
}
} else if (type_str.substr(0, 9) == "$_DFFSRE_" && type_str.size() == 14) {
info.is_fine = true;
@ -232,11 +232,11 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
info.has_ce = true;
info.pol_ce = type_str[12] == 'P';
if constexpr (have_cell) {
info.sig_d = cell->getPort(ID::D);
info.sig_clk = cell->getPort(ID::C);
info.sig_set = cell->getPort(ID::S);
info.sig_clr = cell->getPort(ID::R);
info.sig_ce = cell->getPort(ID::E);
info.sig_d = cell->getPort(TW::D);
info.sig_clk = cell->getPort(TW::C);
info.sig_set = cell->getPort(TW::S);
info.sig_clr = cell->getPort(TW::R);
info.sig_ce = cell->getPort(TW::E);
}
} else if (type_str.substr(0, 7) == "$_SDFF_" && type_str.size() == 11) {
info.is_fine = true;
@ -246,9 +246,9 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
info.pol_srst = type_str[8] == 'P';
info.val_srst = type_str[9] == '1' ? State::S1 : State::S0;
if constexpr (have_cell) {
info.sig_d = cell->getPort(ID::D);
info.sig_clk = cell->getPort(ID::C);
info.sig_srst = cell->getPort(ID::R);
info.sig_d = cell->getPort(TW::D);
info.sig_clk = cell->getPort(TW::C);
info.sig_srst = cell->getPort(TW::R);
}
} else if (type_str.substr(0, 8) == "$_SDFFE_" && type_str.size() == 13) {
info.is_fine = true;
@ -260,10 +260,10 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
info.has_ce = true;
info.pol_ce = type_str[11] == 'P';
if constexpr (have_cell) {
info.sig_d = cell->getPort(ID::D);
info.sig_clk = cell->getPort(ID::C);
info.sig_srst = cell->getPort(ID::R);
info.sig_ce = cell->getPort(ID::E);
info.sig_d = cell->getPort(TW::D);
info.sig_clk = cell->getPort(TW::C);
info.sig_srst = cell->getPort(TW::R);
info.sig_ce = cell->getPort(TW::E);
}
} else if (type_str.substr(0, 9) == "$_SDFFCE_" && type_str.size() == 14) {
info.is_fine = true;
@ -276,10 +276,10 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
info.pol_ce = type_str[12] == 'P';
info.ce_over_srst = true;
if constexpr (have_cell) {
info.sig_d = cell->getPort(ID::D);
info.sig_clk = cell->getPort(ID::C);
info.sig_srst = cell->getPort(ID::R);
info.sig_ce = cell->getPort(ID::E);
info.sig_d = cell->getPort(TW::D);
info.sig_clk = cell->getPort(TW::C);
info.sig_srst = cell->getPort(TW::R);
info.sig_ce = cell->getPort(TW::E);
}
} else if (type_str.substr(0, 9) == "$_DLATCH_" && type_str.size() == 11) {
info.is_fine = true;
@ -287,8 +287,8 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
info.has_aload = true;
info.pol_aload = type_str[9] == 'P';
if constexpr (have_cell) {
info.sig_ad = cell->getPort(ID::D);
info.sig_aload = cell->getPort(ID::E);
info.sig_ad = cell->getPort(TW::D);
info.sig_aload = cell->getPort(TW::E);
}
} else if (type_str.substr(0, 9) == "$_DLATCH_" && type_str.size() == 13) {
info.is_fine = true;
@ -299,9 +299,9 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
info.pol_arst = type_str[10] == 'P';
info.val_arst = type_str[11] == '1' ? State::S1 : State::S0;
if constexpr (have_cell) {
info.sig_ad = cell->getPort(ID::D);
info.sig_aload = cell->getPort(ID::E);
info.sig_arst = cell->getPort(ID::R);
info.sig_ad = cell->getPort(TW::D);
info.sig_aload = cell->getPort(TW::E);
info.sig_arst = cell->getPort(TW::R);
}
} else if (type_str.substr(0, 11) == "$_DLATCHSR_" && type_str.size() == 15) {
info.is_fine = true;
@ -312,10 +312,10 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
info.pol_set = type_str[12] == 'P';
info.pol_clr = type_str[13] == 'P';
if constexpr (have_cell) {
info.sig_ad = cell->getPort(ID::D);
info.sig_aload = cell->getPort(ID::E);
info.sig_set = cell->getPort(ID::S);
info.sig_clr = cell->getPort(ID::R);
info.sig_ad = cell->getPort(TW::D);
info.sig_aload = cell->getPort(TW::E);
info.sig_set = cell->getPort(TW::S);
info.sig_clr = cell->getPort(TW::R);
}
} else {
log_assert(0);
@ -780,7 +780,7 @@ Cell *FfData::emit() {
}
}
if (initvals && !is_anyinit)
initvals->set_init(cell->getPort(ID::Q), val_init);
initvals->set_init(cell->getPort(TW::Q), val_init);
return cell;
}
@ -823,7 +823,7 @@ void FfData::flip_bits(const pool<int> &bits) {
flip_rst_bits(bits);
Wire *new_q = module->addWire(NEW_ID, width);
Wire *new_q = module->addWire(NEW_TWINE, width);
if (has_sr && cell) {
log_warning("Flipping D/Q/init and inserting priority fixup to legalize %s.%s [%s].\n", module->name.unescape(), cell->name.unescape(), cell->type.unescape());

12
kernel/ffmerge.cc
View File

@ -298,12 +298,12 @@ void FfMergeHelper::remove_output_ff(const pool<std::pair<Cell *, int>> &bits) {
for (auto &it : bits) {
Cell *cell = it.first;
int idx = it.second;
SigSpec q = cell->getPort(ID::Q);
SigSpec q = cell->getPort(TW::Q);
initvals->remove_init(q[idx]);
dff_driver.erase((*sigmap)(q[idx]));
q[idx] = module->addWire(stringf("$ffmerge_disconnected$%d", autoidx++));
cell->setPort(ID::Q, q);
initvals->set_init(cell->getPort(ID::Q), (*initvals)(q));
cell->setPort(TW::Q, q);
initvals->set_init(cell->getPort(TW::Q), (*initvals)(q));
}
}
@ -312,7 +312,7 @@ void FfMergeHelper::mark_input_ff(const pool<std::pair<Cell *, int>> &bits) {
Cell *cell = it.first;
int idx = it.second;
if (cell->hasPort(ID::D)) {
SigSpec d = cell->getPort(ID::D);
SigSpec d = cell->getPort(TW::D);
// The user count was already at least 1
// (for the D port). Bump it as it is now connected
// to the merged-to cell as well. This suffices for
@ -338,11 +338,11 @@ void FfMergeHelper::set(FfInitVals *initvals_, RTLIL::Module *module_)
for (auto cell : module->cells()) {
if (cell->is_builtin_ff()) {
if (cell->hasPort(ID::D)) {
SigSpec d = (*sigmap)(cell->getPort(ID::D));
SigSpec d = (*sigmap)(cell->getPort(TW::D));
for (int i = 0; i < GetSize(d); i++)
dff_sink[d[i]].insert(std::make_pair(cell, i));
}
SigSpec q = (*sigmap)(cell->getPort(ID::Q));
SigSpec q = (*sigmap)(cell->getPort(TW::Q));
for (int i = 0; i < GetSize(q); i++)
dff_driver[q[i]] = std::make_pair(cell, i);
}

16
kernel/macc.h
View File

@ -84,7 +84,7 @@ struct Macc
void from_cell_v1(RTLIL::Cell *cell)
{
RTLIL::SigSpec port_a = cell->getPort(ID::A);
RTLIL::SigSpec port_a = cell->getPort(TW::A);
terms.clear();
@ -129,7 +129,7 @@ struct Macc
terms.push_back(this_port);
}
for (auto bit : cell->getPort(ID::B))
for (auto bit : cell->getPort(TW::B))
terms.push_back(term_t{{bit}, {}, false, false});
log_assert(config_cursor == config_width);
@ -144,9 +144,9 @@ struct Macc
}
log_assert(cell->type == ID($macc_v2));
RTLIL::SigSpec port_a = cell->getPort(ID::A);
RTLIL::SigSpec port_b = cell->getPort(ID::B);
RTLIL::SigSpec port_c = cell->getPort(ID::C);
RTLIL::SigSpec port_a = cell->getPort(TW::A);
RTLIL::SigSpec port_b = cell->getPort(TW::B);
RTLIL::SigSpec port_c = cell->getPort(TW::C);
terms.clear();
@ -255,9 +255,9 @@ struct Macc
cell->setParam(ID::A_WIDTHS, a_widths);
cell->setParam(ID::B_WIDTHS, b_widths);
cell->setParam(ID::C_WIDTHS, c_widths);
cell->setPort(ID::A, a);
cell->setPort(ID::B, b);
cell->setPort(ID::C, c);
cell->setPort(TW::A, a);
cell->setPort(TW::B, b);
cell->setPort(TW::C, c);
}
bool eval(RTLIL::Const &result) const

130
kernel/mem.cc
View File

@ -221,12 +221,12 @@ void Mem::emit() {
cell->parameters[ID::RD_SRST_VALUE] = rd_srst_value;
cell->parameters[ID::RD_INIT_VALUE] = rd_init_value;
cell->parameters.erase(ID::RD_TRANSPARENT);
cell->setPort(ID::RD_CLK, rd_clk);
cell->setPort(ID::RD_EN, rd_en);
cell->setPort(ID::RD_ARST, rd_arst);
cell->setPort(ID::RD_SRST, rd_srst);
cell->setPort(ID::RD_ADDR, rd_addr);
cell->setPort(ID::RD_DATA, rd_data);
cell->setPort(TW::RD_CLK, rd_clk);
cell->setPort(TW::RD_EN, rd_en);
cell->setPort(TW::RD_ARST, rd_arst);
cell->setPort(TW::RD_SRST, rd_srst);
cell->setPort(TW::RD_ADDR, rd_addr);
cell->setPort(TW::RD_DATA, rd_data);
Const::Builder wr_wide_continuation_builder;
Const::Builder wr_clk_enable_builder;
Const::Builder wr_clk_polarity_builder;
@ -270,10 +270,10 @@ void Mem::emit() {
cell->parameters[ID::WR_CLK_POLARITY] = wr_clk_polarity;
cell->parameters[ID::WR_PRIORITY_MASK] = wr_priority_mask;
cell->parameters[ID::WR_WIDE_CONTINUATION] = wr_wide_continuation;
cell->setPort(ID::WR_CLK, wr_clk);
cell->setPort(ID::WR_EN, wr_en);
cell->setPort(ID::WR_ADDR, wr_addr);
cell->setPort(ID::WR_DATA, wr_data);
cell->setPort(TW::WR_CLK, wr_clk);
cell->setPort(TW::WR_EN, wr_en);
cell->setPort(TW::WR_ADDR, wr_addr);
cell->setPort(TW::WR_DATA, wr_data);
for (auto &init : inits) {
for (auto attr: init.attributes)
if (!cell->has_attribute(attr.first))
@ -303,7 +303,7 @@ void Mem::emit() {
mem->attributes = attributes;
for (auto &port : rd_ports) {
if (!port.cell)
port.cell = module->addCell(NEW_ID, ID($memrd_v2));
port.cell = module->addCell(NEW_TWINE, ID($memrd_v2));
port.cell->type = ID($memrd_v2);
port.cell->attributes = port.attributes;
port.cell->parameters[ID::MEMID] = memid.str();
@ -318,17 +318,17 @@ void Mem::emit() {
port.cell->parameters[ID::TRANSPARENCY_MASK] = port.transparency_mask;
port.cell->parameters[ID::COLLISION_X_MASK] = port.collision_x_mask;
port.cell->parameters.erase(ID::TRANSPARENT);
port.cell->setPort(ID::CLK, port.clk);
port.cell->setPort(ID::EN, port.en);
port.cell->setPort(ID::ARST, port.arst);
port.cell->setPort(ID::SRST, port.srst);
port.cell->setPort(ID::ADDR, port.addr);
port.cell->setPort(ID::DATA, port.data);
port.cell->setPort(TW::CLK, port.clk);
port.cell->setPort(TW::EN, port.en);
port.cell->setPort(TW::ARST, port.arst);
port.cell->setPort(TW::SRST, port.srst);
port.cell->setPort(TW::ADDR, port.addr);
port.cell->setPort(TW::DATA, port.data);
}
int idx = 0;
for (auto &port : wr_ports) {
if (!port.cell)
port.cell = module->addCell(NEW_ID, ID($memwr_v2));
port.cell = module->addCell(NEW_TWINE, ID($memwr_v2));
port.cell->type = ID($memwr_v2);
port.cell->attributes = port.attributes;
if (port.cell->parameters.count(ID::PRIORITY))
@ -340,19 +340,19 @@ void Mem::emit() {
port.cell->parameters[ID::CLK_POLARITY] = port.clk_polarity;
port.cell->parameters[ID::PORTID] = idx++;
port.cell->parameters[ID::PRIORITY_MASK] = port.priority_mask;
port.cell->setPort(ID::CLK, port.clk);
port.cell->setPort(ID::EN, port.en);
port.cell->setPort(ID::ADDR, port.addr);
port.cell->setPort(ID::DATA, port.data);
port.cell->setPort(TW::CLK, port.clk);
port.cell->setPort(TW::EN, port.en);
port.cell->setPort(TW::ADDR, port.addr);
port.cell->setPort(TW::DATA, port.data);
}
idx = 0;
for (auto &init : inits) {
bool v2 = !init.en.is_fully_ones();
if (!init.cell)
init.cell = module->addCell(NEW_ID, v2 ? ID($meminit_v2) : ID($meminit));
init.cell = module->addCell(NEW_TWINE, v2 ? ID($meminit_v2) : ID($meminit));
else {
if (!v2)
init.cell->unsetPort(ID::EN);
init.cell->unsetPort(TW::EN);
init.cell->type = v2 ? ID($meminit_v2) : ID($meminit);
}
init.cell->attributes = init.attributes;
@ -361,10 +361,10 @@ void Mem::emit() {
init.cell->parameters[ID::WIDTH] = width;
init.cell->parameters[ID::WORDS] = GetSize(init.data) / width;
init.cell->parameters[ID::PRIORITY] = idx++;
init.cell->setPort(ID::ADDR, init.addr);
init.cell->setPort(ID::DATA, init.data);
init.cell->setPort(TW::ADDR, init.addr);
init.cell->setPort(TW::DATA, init.data);
if (v2)
init.cell->setPort(ID::EN, init.en);
init.cell->setPort(TW::EN, init.en);
}
}
}
@ -576,10 +576,10 @@ namespace {
mrd.attributes = cell->attributes;
mrd.clk_enable = cell->parameters.at(ID::CLK_ENABLE).as_bool();
mrd.clk_polarity = cell->parameters.at(ID::CLK_POLARITY).as_bool();
mrd.clk = cell->getPort(ID::CLK);
mrd.en = cell->getPort(ID::EN);
mrd.addr = cell->getPort(ID::ADDR);
mrd.data = cell->getPort(ID::DATA);
mrd.clk = cell->getPort(TW::CLK);
mrd.en = cell->getPort(TW::EN);
mrd.addr = cell->getPort(TW::ADDR);
mrd.data = cell->getPort(TW::DATA);
mrd.wide_log2 = ceil_log2(GetSize(mrd.data) / mem->width);
bool transparent = false;
if (is_compat) {
@ -604,8 +604,8 @@ namespace {
mrd.arst_value = cell->parameters.at(ID::ARST_VALUE);
mrd.srst_value = cell->parameters.at(ID::SRST_VALUE);
mrd.init_value = cell->parameters.at(ID::INIT_VALUE);
mrd.arst = cell->getPort(ID::ARST);
mrd.srst = cell->getPort(ID::SRST);
mrd.arst = cell->getPort(TW::ARST);
mrd.srst = cell->getPort(TW::SRST);
}
res.rd_ports.push_back(mrd);
rd_transparent.push_back(transparent);
@ -620,10 +620,10 @@ namespace {
mwr.attributes = cell->attributes;
mwr.clk_enable = cell->parameters.at(ID::CLK_ENABLE).as_bool();
mwr.clk_polarity = cell->parameters.at(ID::CLK_POLARITY).as_bool();
mwr.clk = cell->getPort(ID::CLK);
mwr.en = cell->getPort(ID::EN);
mwr.addr = cell->getPort(ID::ADDR);
mwr.data = cell->getPort(ID::DATA);
mwr.clk = cell->getPort(TW::CLK);
mwr.en = cell->getPort(TW::EN);
mwr.addr = cell->getPort(TW::ADDR);
mwr.data = cell->getPort(TW::DATA);
mwr.wide_log2 = ceil_log2(GetSize(mwr.data) / mem->width);
ports.push_back(std::make_pair(cell->parameters.at(is_compat ? ID::PRIORITY : ID::PORTID).as_int(), mwr));
}
@ -662,8 +662,8 @@ namespace {
MemInit init;
init.cell = cell;
init.attributes = cell->attributes;
auto addr = cell->getPort(ID::ADDR);
auto data = cell->getPort(ID::DATA);
auto addr = cell->getPort(TW::ADDR);
auto data = cell->getPort(TW::DATA);
if (!addr.is_fully_const())
log_error("Non-constant address %s in memory initialization %s.\n", log_signal(addr), cell);
if (!data.is_fully_const())
@ -671,7 +671,7 @@ namespace {
init.addr = addr.as_const();
init.data = data.as_const();
if (cell->type == ID($meminit_v2)) {
auto en = cell->getPort(ID::EN);
auto en = cell->getPort(TW::EN);
if (!en.is_fully_const())
log_error("Non-constant enable %s in memory initialization %s.\n", log_signal(en), cell);
init.en = en.as_const();
@ -764,10 +764,10 @@ namespace {
log_assert(ni - i == (1 << mrd.wide_log2));
mrd.clk_enable = cell->parameters.at(ID::RD_CLK_ENABLE).extract(i, 1).as_bool();
mrd.clk_polarity = cell->parameters.at(ID::RD_CLK_POLARITY).extract(i, 1).as_bool();
mrd.clk = cell->getPort(ID::RD_CLK).extract(i, 1);
mrd.en = cell->getPort(ID::RD_EN).extract(i, 1);
mrd.addr = cell->getPort(ID::RD_ADDR).extract(i * abits, abits);
mrd.data = cell->getPort(ID::RD_DATA).extract(i * res.width, (ni - i) * res.width);
mrd.clk = cell->getPort(TW::RD_CLK).extract(i, 1);
mrd.en = cell->getPort(TW::RD_EN).extract(i, 1);
mrd.addr = cell->getPort(TW::RD_ADDR).extract(i * abits, abits);
mrd.data = cell->getPort(TW::RD_DATA).extract(i * res.width, (ni - i) * res.width);
if (is_compat) {
mrd.ce_over_srst = false;
mrd.arst_value = Const(State::Sx, res.width << mrd.wide_log2);
@ -780,8 +780,8 @@ namespace {
mrd.arst_value = cell->parameters.at(ID::RD_ARST_VALUE).extract(i * res.width, (ni - i) * res.width);
mrd.srst_value = cell->parameters.at(ID::RD_SRST_VALUE).extract(i * res.width, (ni - i) * res.width);
mrd.init_value = cell->parameters.at(ID::RD_INIT_VALUE).extract(i * res.width, (ni - i) * res.width);
mrd.arst = cell->getPort(ID::RD_ARST).extract(i, 1);
mrd.srst = cell->getPort(ID::RD_SRST).extract(i, 1);
mrd.arst = cell->getPort(TW::RD_ARST).extract(i, 1);
mrd.srst = cell->getPort(TW::RD_SRST).extract(i, 1);
}
if (!is_compat) {
Const transparency_mask = cell->parameters.at(ID::RD_TRANSPARENCY_MASK).extract(i * n_wr_ports, n_wr_ports);
@ -803,10 +803,10 @@ namespace {
log_assert(ni - i == (1 << mwr.wide_log2));
mwr.clk_enable = cell->parameters.at(ID::WR_CLK_ENABLE).extract(i, 1).as_bool();
mwr.clk_polarity = cell->parameters.at(ID::WR_CLK_POLARITY).extract(i, 1).as_bool();
mwr.clk = cell->getPort(ID::WR_CLK).extract(i, 1);
mwr.en = cell->getPort(ID::WR_EN).extract(i * res.width, (ni - i) * res.width);
mwr.addr = cell->getPort(ID::WR_ADDR).extract(i * abits, abits);
mwr.data = cell->getPort(ID::WR_DATA).extract(i * res.width, (ni - i) * res.width);
mwr.clk = cell->getPort(TW::WR_CLK).extract(i, 1);
mwr.en = cell->getPort(TW::WR_EN).extract(i * res.width, (ni - i) * res.width);
mwr.addr = cell->getPort(TW::WR_ADDR).extract(i * abits, abits);
mwr.data = cell->getPort(TW::WR_DATA).extract(i * res.width, (ni - i) * res.width);
if (!is_compat) {
Const priority_mask = cell->parameters.at(ID::WR_PRIORITY_MASK).extract(i * n_wr_ports, n_wr_ports);
for (int j = 0; j < n_wr_ports; j++)
@ -1178,7 +1178,7 @@ void Mem::emulate_transparency(int widx, int ridx, FfInitVals *initvals) {
// The write data FF doesn't need full reset/init behavior, as it'll be masked by
// the mux whenever this would be relevant. It does, however, need to have the same
// clock enable signal as the read port.
SigSpec wdata_q = module->addWire(NEW_ID, GetSize(wport.data));
SigSpec wdata_q = module->addWire(NEW_TWINE, GetSize(wport.data));
module->addDffe(NEW_ID, rport.clk, rport.en, wport.data, wdata_q, rport.clk_polarity, true);
for (int sub = 0; sub < (1 << max_wide_log2); sub += (1 << min_wide_log2)) {
SigSpec raddr = rport.addr;
@ -1195,7 +1195,7 @@ void Mem::emulate_transparency(int widx, int ridx, FfInitVals *initvals) {
int ewidth = width << min_wide_log2;
int wsub = wide_write ? sub : 0;
int rsub = wide_write ? 0 : sub;
SigSpec rdata_a = module->addWire(NEW_ID, ewidth);
SigSpec rdata_a = module->addWire(NEW_TWINE, ewidth);
while (pos < ewidth) {
int epos = pos;
while (epos < ewidth && wport.en[epos + wsub * width] == wport.en[pos + wsub * width])
@ -1205,7 +1205,7 @@ void Mem::emulate_transparency(int widx, int ridx, FfInitVals *initvals) {
cond = module->And(NEW_ID, wport.en[pos + wsub * width], addr_eq);
else
cond = wport.en[pos + wsub * width];
SigSpec cond_q = module->addWire(NEW_ID);
SigSpec cond_q = module->addWire(NEW_TWINE);
// The FF for storing the bypass enable signal must be carefully
// constructed to preserve the overall init/reset/enable behavior
// of the whole port.
@ -1405,9 +1405,9 @@ void Mem::emulate_rden(int idx, FfInitVals *initvals) {
auto &port = rd_ports[idx];
log_assert(port.clk_enable);
emulate_rd_ce_over_srst(idx);
Wire *new_data = module->addWire(NEW_ID, GetSize(port.data));
Wire *prev_data = module->addWire(NEW_ID, GetSize(port.data));
Wire *sel = module->addWire(NEW_ID);
Wire *new_data = module->addWire(NEW_TWINE, GetSize(port.data));
Wire *prev_data = module->addWire(NEW_TWINE, GetSize(port.data));
Wire *sel = module->addWire(NEW_TWINE);
FfData ff_sel(module, initvals, NEW_ID);
FfData ff_data(module, initvals, NEW_ID);
ff_sel.width = 1;
@ -1465,9 +1465,9 @@ void Mem::emulate_rden(int idx, FfInitVals *initvals) {
void Mem::emulate_reset(int idx, bool emu_init, bool emu_arst, bool emu_srst, FfInitVals *initvals) {
auto &port = rd_ports[idx];
if (emu_init && !port.init_value.is_fully_undef()) {
Wire *sel = module->addWire(NEW_ID);
Wire *sel = module->addWire(NEW_TWINE);
FfData ff_sel(module, initvals, NEW_ID);
Wire *new_data = module->addWire(NEW_ID, GetSize(port.data));
Wire *new_data = module->addWire(NEW_TWINE, GetSize(port.data));
ff_sel.width = 1;
ff_sel.has_clk = true;
ff_sel.sig_clk = port.clk;
@ -1511,9 +1511,9 @@ void Mem::emulate_reset(int idx, bool emu_init, bool emu_arst, bool emu_srst, Ff
port.init_value = Const(State::Sx, GetSize(port.data));
}
if (emu_arst && port.arst != State::S0) {
Wire *sel = module->addWire(NEW_ID);
Wire *sel = module->addWire(NEW_TWINE);
FfData ff_sel(module, initvals, NEW_ID);
Wire *new_data = module->addWire(NEW_ID, GetSize(port.data));
Wire *new_data = module->addWire(NEW_TWINE, GetSize(port.data));
ff_sel.width = 1;
ff_sel.has_clk = true;
ff_sel.sig_clk = port.clk;
@ -1551,9 +1551,9 @@ void Mem::emulate_reset(int idx, bool emu_init, bool emu_arst, bool emu_srst, Ff
port.arst = State::S0;
}
if (emu_srst && port.srst != State::S0) {
Wire *sel = module->addWire(NEW_ID);
Wire *sel = module->addWire(NEW_TWINE);
FfData ff_sel(module, initvals, NEW_ID);
Wire *new_data = module->addWire(NEW_ID, GetSize(port.data));
Wire *new_data = module->addWire(NEW_TWINE, GetSize(port.data));
ff_sel.width = 1;
ff_sel.has_clk = true;
ff_sel.sig_clk = port.clk;
@ -1652,10 +1652,10 @@ void Mem::emulate_read_first(FfInitVals *initvals) {
rd_ports[i].transparency_mask[j] = true;
}
for (auto &port: wr_ports) {
Wire *new_data = module->addWire(NEW_ID, GetSize(port.data));
Wire *new_addr = module->addWire(NEW_ID, GetSize(port.addr));
Wire *new_data = module->addWire(NEW_TWINE, GetSize(port.data));
Wire *new_addr = module->addWire(NEW_TWINE, GetSize(port.addr));
auto compressed = port.compress_en();
Wire *new_en = module->addWire(NEW_ID, GetSize(compressed.first));
Wire *new_en = module->addWire(NEW_TWINE, GetSize(compressed.first));
FfData ff_data(module, initvals, NEW_ID);
FfData ff_addr(module, initvals, NEW_ID);
FfData ff_en(module, initvals, NEW_ID);

18
kernel/modtools.h
View File

@ -47,11 +47,11 @@ struct ModIndex : public RTLIL::Monitor
};
struct PortInfo {
RTLIL::Cell* cell;
RTLIL::IdString port;
TwineRef port;
int offset;
PortInfo() : cell(), port(), offset() { }
PortInfo(RTLIL::Cell* _c, RTLIL::IdString _p, int _o) : cell(_c), port(_p), offset(_o) { }
PortInfo(RTLIL::Cell* _c, TwineRef _p, int _o) : cell(_c), port(_p), offset(_o) { }
bool operator<(const PortInfo &other) const {
if (cell != other.cell)
@ -98,7 +98,7 @@ struct ModIndex : public RTLIL::Monitor
int auto_reload_counter;
bool auto_reload_module;
void port_add(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)
void port_add(RTLIL::Cell *cell, TwineRef port, const RTLIL::SigSpec &sig)
{
for (int i = 0; i < GetSize(sig); i++) {
RTLIL::SigBit bit = sigmap(sig[i]);
@ -107,7 +107,7 @@ struct ModIndex : public RTLIL::Monitor
}
}
void port_del(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)
void port_del(RTLIL::Cell *cell, TwineRef port, const RTLIL::SigSpec &sig)
{
for (int i = 0; i < GetSize(sig); i++) {
RTLIL::SigBit bit = sigmap(sig[i]);
@ -187,7 +187,7 @@ struct ModIndex : public RTLIL::Monitor
log_assert(ok());
}
void notify_connect(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override
void notify_connect(RTLIL::Cell *cell, TwineRef port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override
{
log_assert(module == cell->module);
@ -321,7 +321,7 @@ struct ModIndex : public RTLIL::Monitor
log(" PRIMARY OUTPUT\n");
for (auto &port : it.second.ports)
log(" PORT: %s.%s[%d] (%s)\n", port.cell,
port.port.unescape(), port.offset, port.cell->type.unescape());
module->design->twines.str(port.port), port.offset, port.cell->type.unescape());
}
}
};
@ -331,9 +331,9 @@ struct ModWalker
struct PortBit
{
RTLIL::Cell *cell;
RTLIL::IdString port;
TwineRef port;
int offset;
PortBit(Cell* c, IdString p, int o) : cell(c), port(p), offset(o) {}
PortBit(Cell* c, TwineRef p, int o) : cell(c), port(p), offset(o) {}
bool operator<(const PortBit &other) const {
if (cell != other.cell)
@ -384,7 +384,7 @@ struct ModWalker
}
}
void add_cell_port(RTLIL::Cell *cell, RTLIL::IdString port, std::vector<RTLIL::SigBit> bits, bool is_output, bool is_input)
void add_cell_port(RTLIL::Cell *cell, TwineRef port, std::vector<RTLIL::SigBit> bits, bool is_output, bool is_input)
{
for (int i = 0; i < int(bits.size()); i++)
if (bits[i].wire != NULL) {

4
kernel/newcelltypes.h
View File

@ -586,9 +586,9 @@ struct NewCellTypes {
for (auto wire_name : module->ports) {
RTLIL::Wire *wire = module->wire(wire_name);
if (wire->port_input)
inputs.insert(wire->meta_->name_id);
inputs.insert(wire->meta_->name);
if (wire->port_output)
outputs.insert(wire->meta_->name_id);
outputs.insert(wire->meta_->name);
}
setup_type(module->name, inputs, outputs);
}

2
kernel/pmux.h
View File

@ -14,7 +14,7 @@ struct PmuxBPortIterator {
PmuxBPortIterator(Cell* mux) : cell(mux) {
log_assert(mux->type == ID($mux) || mux->type == ID($pmux));
port_idx = 0;
b = mux->getPort(ID::B).to_sigbit_vector();
b = mux->getPort(TW::B).to_sigbit_vector();
port_count = GetSize(sig_b) / s_width;
}

1934
kernel/rtlil.cc
View File

File diff suppressed because it is too large Load Diff

475
kernel/rtlil.h
View File

@ -129,7 +129,6 @@ namespace RTLIL
struct OwningIdString;
struct StaticIdString;
struct SigNormIndex;
struct SrcAttr;
struct ObjMeta;
struct ModuleNameMasq;
struct WireNameMasq;
@ -139,7 +138,6 @@ namespace RTLIL
struct PortBit;
};
using SrcAttr = TwineRef;
// TODO clean up?
extern int64_t signorm_ns;
@ -806,7 +804,7 @@ namespace RTLIL {
return log_id(str);
}
template <typename T> struct sort_by_name_id {
template <typename T> struct sort_by_name {
bool operator()(T *a, T *b) const {
return a->name < b->name;
}
@ -1285,7 +1283,7 @@ struct RTLIL::ObjMeta
{
TwineRef src = Twine::Null;
// RTLIL::IdString name; // used by Module names
TwineRef name_id = Twine::Null; // used by Wire/Cell names (per-Design twines)
TwineRef name = Twine::Null; // used by Wire/Cell names (per-Design twines)
};
struct RTLIL::AttrObject
@ -1942,8 +1940,8 @@ struct RTLIL::Selection
// add whole module to this selection
template<typename T1> void select(T1 *module) {
if (!selects_all() && selected_modules.count(module->meta_->name_id) == 0) {
TwineRef name = module->meta_->name_id;
if (!selects_all() && selected_modules.count(module->meta_->name) == 0) {
TwineRef name = module->meta_->name;
selected_modules.insert(name);
selected_members.erase(name);
if (module->get_blackbox_attribute())
@ -1992,7 +1990,7 @@ struct RTLIL::Monitor
virtual ~Monitor() { }
virtual void notify_module_add(RTLIL::Module*) { }
virtual void notify_module_del(RTLIL::Module*) { }
virtual void notify_connect(RTLIL::Cell*, RTLIL::IdString, const RTLIL::SigSpec&, const RTLIL::SigSpec&) { }
virtual void notify_connect(RTLIL::Cell*, TwineRef, const RTLIL::SigSpec&, const RTLIL::SigSpec&) { }
virtual void notify_connect(RTLIL::Module*, const RTLIL::SigSig&) { }
virtual void notify_connect(RTLIL::Module*, const std::vector<RTLIL::SigSig>&) { }
virtual void notify_blackout(RTLIL::Module*) { }
@ -2015,7 +2013,7 @@ struct RTLIL::Design
void sigNormalize(bool enable=true);
int refcount_modules_;
dict<IdString, RTLIL::Module*> modules_;
dict<TwineRef, RTLIL::Module*> modules_;
std::vector<RTLIL::Binding*> bindings_;
TwinePool twines;
@ -2035,22 +2033,22 @@ struct RTLIL::Design
void obj_release_src(RTLIL::AttrObject *obj);
std::string obj_name(const RTLIL::AttrObject *obj) const {
return (obj->meta_ ? twines.flat_string(obj->meta_->name_id) : std::string());
return (obj->meta_ ? twines.flat_string(obj->meta_->name) : std::string());
}
void obj_set_name(RTLIL::AttrObject *obj, RTLIL::IdString name);
void obj_release_name(RTLIL::AttrObject *obj);
// void obj_set_name(RTLIL::AttrObject *obj, RTLIL::IdString name);
// void obj_release_name(RTLIL::AttrObject *obj);
// Wire/Cell names: stored as TwineRef in twines.
TwineRef obj_name_id(const RTLIL::AttrObject *obj) const {
return (obj->meta_ ? obj->meta_->name_id : Twine::Null);
}
void obj_set_name_id(RTLIL::AttrObject *obj, TwineRef id);
void obj_release_name_id(RTLIL::AttrObject *obj);
// TwineRef obj_name(const RTLIL::AttrObject *obj) const {
// return (obj->meta_ ? obj->meta_->name : Twine::Null);
// }
// void obj_set_name(RTLIL::AttrObject *obj, TwineRef id);
// void obj_release_name(RTLIL::AttrObject *obj);
// Replacements for the methods that used to live on AttrObject and
// took an explicit TwinePool*. Same semantics; the pool resolves
// to this->twines internally.
void set_src_attribute(RTLIL::AttrObject *obj, const RTLIL::SrcAttr &src);
void set_src_attribute(RTLIL::AttrObject *obj, TwineRef src);
std::string get_src_attribute(const RTLIL::AttrObject *obj) const;
void adopt_src_from(RTLIL::AttrObject *obj, const RTLIL::AttrObject *source);
void adopt_src_from(RTLIL::AttrObject *obj, const RTLIL::AttrObject *source,
@ -2097,11 +2095,12 @@ struct RTLIL::Design
RTLIL::ObjRange<RTLIL::Module*, TwineRef> modules();
RTLIL::Module *module(IdString name);
// RTLIL::Module *module(TwineRef name);
// const RTLIL::Module *module(TwineRef name) const;
const RTLIL::Module *module(IdString name) const;
RTLIL::Module *module(TwineRef name);
const RTLIL::Module *module(TwineRef name) const;
RTLIL::Module *top_module() const;
bool has(IdString id) const {
bool has(TwineRef id) const {
return modules_.count(id) != 0;
}
@ -2188,7 +2187,7 @@ struct RTLIL::Design
// is the given member of the given module in the current selection
template<typename T1, typename T2> bool selected(T1 *module, T2 *member) const {
return selected_member(module->meta_->name_id, member->meta_->name_id);
return selected_member(module->meta_->name, member->meta_->name);
}
// add whole module to the current selection
@ -2250,7 +2249,7 @@ namespace RTLIL_BACKEND {
void dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire, const RTLIL::Design *design, bool resolve_src);
}
struct RTLIL::Wire : public RTLIL::NamedObject
struct RTLIL::Wire : public RTLIL::AttrObject
{
private:
struct ConstructToken { explicit ConstructToken() = default; };
@ -2271,7 +2270,7 @@ public:
friend void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire, const RTLIL::Design *design, bool resolve_src);
RTLIL::Cell *driverCell_ = nullptr;
RTLIL::IdString driverPort_;
TwineRef driverPort_;
// do not simply copy wires
Wire(ConstructToken, RTLIL::Wire &other);
@ -2286,7 +2285,7 @@ public:
TwineRef src_id() const;
TwineRef src_ref() const { return src_id(); }
void set_src_id(TwineRef id);
void set_src_attribute(const RTLIL::SrcAttr &src);
void set_src_attribute(TwineRef src);
std::string get_src_attribute() const;
// Transfer src from `source` verbatim (same pool). Asserts attached
// to a design.
@ -2296,7 +2295,7 @@ public:
bool known_driver() const { return driverCell_ != nullptr; }
RTLIL::Cell *driverCell() const { log_assert(driverCell_); return driverCell_; };
RTLIL::IdString driverPort() const { log_assert(driverCell_); return driverPort_; };
TwineRef driverPort() const { log_assert(driverCell_); return driverPort_; };
int from_hdl_index(int hdl_index) {
int zero_index = hdl_index - start_offset;
@ -2322,7 +2321,7 @@ inline int GetSize(RTLIL::Wire *wire) {
return wire->width;
}
struct RTLIL::Memory : public RTLIL::NamedObject
struct RTLIL::Memory : public RTLIL::AttrObject
{
Hasher::hash_t hashidx_;
[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }
@ -2341,7 +2340,7 @@ struct RTLIL::Memory : public RTLIL::NamedObject
TwineRef src_id() const;
TwineRef src_ref() const { return src_id(); }
void set_src_id(TwineRef id);
void set_src_attribute(const RTLIL::SrcAttr &src);
void set_src_attribute(TwineRef src);
std::string get_src_attribute() const;
void adopt_src_from(const RTLIL::AttrObject *source);
void absorb_attrs(dict<RTLIL::IdString, RTLIL::Const> &&buf);
@ -2354,7 +2353,7 @@ struct RTLIL::Memory : public RTLIL::NamedObject
std::string to_rtlil_str() const;
};
struct RTLIL::Cell : public RTLIL::NamedObject
struct RTLIL::Cell : public RTLIL::AttrObject
{
private:
struct ConstructToken { explicit ConstructToken() = default; };
@ -2366,9 +2365,9 @@ private:
void initIndex();
// Signorm index helpers (used by setPort/unsetPort/initIndex)
void signorm_index_remove(RTLIL::IdString portname, const RTLIL::SigSpec &old_signal, bool is_input);
void signorm_index_add(RTLIL::IdString portname, const RTLIL::SigSpec &new_signal, bool is_input);
bool bufnorm_handle_setPort(RTLIL::IdString portname, RTLIL::SigSpec &signal, dict<RTLIL::IdString, RTLIL::SigSpec>::iterator conn_it);
void signorm_index_remove(TwineRef portname, const RTLIL::SigSpec &old_signal, bool is_input);
void signorm_index_add(TwineRef portname, const RTLIL::SigSpec &new_signal, bool is_input);
bool bufnorm_handle_setPort(TwineRef portname, RTLIL::SigSpec &signal, dict<TwineRef, RTLIL::SigSpec>::iterator conn_it);
public:
// Shadows NamedObject::name. Reads materialise via twines; writes
// are a compile error — use Module::rename(cell, new_name) instead.
@ -2387,7 +2386,7 @@ public:
RTLIL::Module *module;
IdString type;
dict<RTLIL::IdString, RTLIL::SigSpec> connections_;
dict<TwineRef, RTLIL::SigSpec> connections_;
dict<RTLIL::IdString, RTLIL::Const> parameters;
// Context-aware src helpers. Resolve Design via module->design and
@ -2395,7 +2394,7 @@ public:
TwineRef src_id() const;
TwineRef src_ref() const { return src_id(); }
void set_src_id(TwineRef id);
void set_src_attribute(const RTLIL::SrcAttr &src);
void set_src_attribute(TwineRef src);
std::string get_src_attribute() const;
void adopt_src_from(const RTLIL::AttrObject *source);
void absorb_attrs(dict<RTLIL::IdString, RTLIL::Const> &&buf);
@ -2467,7 +2466,7 @@ struct RTLIL::CaseRule : public RTLIL::AttrObject
TwineRef src_id() const;
TwineRef src_ref() const { return src_id(); }
void set_src_id(TwineRef id);
void set_src_attribute(const RTLIL::SrcAttr &src);
void set_src_attribute(TwineRef src);
std::string get_src_attribute() const;
void adopt_src_from(const RTLIL::AttrObject *source);
void absorb_attrs(dict<RTLIL::IdString, RTLIL::Const> &&buf);
@ -2495,7 +2494,7 @@ struct RTLIL::SwitchRule : public RTLIL::AttrObject
TwineRef src_id() const;
TwineRef src_ref() const { return src_id(); }
void set_src_id(TwineRef id);
void set_src_attribute(const RTLIL::SrcAttr &src);
void set_src_attribute(TwineRef src);
std::string get_src_attribute() const;
void adopt_src_from(const RTLIL::AttrObject *source);
void absorb_attrs(dict<RTLIL::IdString, RTLIL::Const> &&buf);
@ -2520,7 +2519,7 @@ struct RTLIL::MemWriteAction : RTLIL::AttrObject
TwineRef src_id() const;
TwineRef src_ref() const { return src_id(); }
void set_src_id(TwineRef id);
void set_src_attribute(const RTLIL::SrcAttr &src);
void set_src_attribute(TwineRef src);
std::string get_src_attribute() const;
void adopt_src_from(const RTLIL::AttrObject *source);
void absorb_attrs(dict<RTLIL::IdString, RTLIL::Const> &&buf);
@ -2538,7 +2537,7 @@ struct RTLIL::SyncRule
RTLIL::SyncRule *clone() const;
};
struct RTLIL::Process : public RTLIL::NamedObject
struct RTLIL::Process : public RTLIL::AttrObject
{
friend struct RTLIL::SigNormIndex;
friend struct RTLIL::Cell;
@ -2563,7 +2562,7 @@ public:
TwineRef src_id() const;
TwineRef src_ref() const { return src_id(); }
void set_src_id(TwineRef id);
void set_src_attribute(const RTLIL::SrcAttr &src);
void set_src_attribute(TwineRef src);
std::string get_src_attribute() const;
void adopt_src_from(const RTLIL::AttrObject *source);
void absorb_attrs(dict<RTLIL::IdString, RTLIL::Const> &&buf);
@ -2578,9 +2577,9 @@ public:
struct RTLIL::PortBit
{
RTLIL::Cell *cell;
RTLIL::IdString port;
TwineRef port;
int offset;
PortBit(Cell* c, IdString p, int o) : cell(c), port(p), offset(o) {}
PortBit(Cell* c, TwineRef p, int o) : cell(c), port(p), offset(o) {}
bool operator<(const PortBit &other) const {
if (cell != other.cell)
@ -2640,9 +2639,9 @@ inline Hasher RTLIL::SigBit::hash_into(Hasher h) const {
inline Hasher RTLIL::SigBit::hash_top() const {
Hasher h;
if (wire) {
// Use the wire's name_id (TwineRef) directly — avoids IdString materialisation.
TwineRef name_id = wire->meta_ ? wire->meta_->name_id : Twine::Null;
h.eat(name_id);
// Use the wire's name (TwineRef) directly — avoids IdString materialisation.
TwineRef name = wire->meta_ ? wire->meta_->name : Twine::Null;
h.eat(name);
h.eat(offset);
return h;
}
@ -2670,212 +2669,212 @@ class CellAdderMixin {
public:
// The add* methods create a cell and return the created cell. All signals must exist in advance.
RTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addPos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addBuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addNeg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addNot (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addPos (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addBuf (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addNeg (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addAnd (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addOr (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addXor (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addXnor (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addReduceAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addReduceOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addReduceXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addReduceAnd (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addReduceOr (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addReduceXor (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addReduceXnor (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addReduceBool (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addShl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addShr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addSshl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addSshr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addShift (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addShiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addShl (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addShr (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addSshl (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addSshr (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addShift (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addShiftx (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addLt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addLe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addEq (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addNe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addEqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addNex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addGe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addGt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addLt (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addLe (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addEq (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addNe (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addEqx (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addNex (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addGe (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addGt (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addAdd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addSub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addMul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addAdd (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addSub (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addMul (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
// truncating division
RTLIL::Cell* addDiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addDiv (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
// truncating modulo
RTLIL::Cell* addMod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addDivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addPow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed = false, bool b_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addMod (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addDivFloor (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addModFloor (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addPow (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed = false, bool b_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addFa (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addFa (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addLogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addLogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addLogicOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addLogicNot (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addLogicAnd (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addLogicOr (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addMux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addPmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addBmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addDemux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addMux (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addPmux (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addBmux (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addDemux (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addBweqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addBwmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addBweqx (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addBwmux (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addSlice (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, TwineRef src = Twine::Null);
RTLIL::Cell* addConcat (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addLut (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, TwineRef src = Twine::Null);
RTLIL::Cell* addTribuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addAssert (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null);
RTLIL::Cell* addAssume (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null);
RTLIL::Cell* addLive (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null);
RTLIL::Cell* addFair (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null);
RTLIL::Cell* addCover (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null);
RTLIL::Cell* addEquiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addSlice (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, TwineRef src = Twine::Null);
RTLIL::Cell* addConcat (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addLut (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, TwineRef src = Twine::Null);
RTLIL::Cell* addTribuf (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addAssert (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null);
RTLIL::Cell* addAssume (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null);
RTLIL::Cell* addLive (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null);
RTLIL::Cell* addFair (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null);
RTLIL::Cell* addCover (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null);
RTLIL::Cell* addEquiv (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addSr (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addFf (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, TwineRef src = Twine::Null);
RTLIL::Cell* addDff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDffsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDffsre (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAldff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAldffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addSdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool srst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addSdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addSdffce (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAdlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool en_polarity = true, bool arst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDlatchsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addSr (Twine &&name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addFf (Twine &&name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, TwineRef src = Twine::Null);
RTLIL::Cell* addDff (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDffe (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDffsr (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDffsre (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAdff (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAdffe (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAldff (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAldffe (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addSdff (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool srst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addSdffe (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addSdffce (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDlatch (Twine &&name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAdlatch (Twine &&name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool en_polarity = true, bool arst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDlatchsr (Twine &&name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addBufGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addNotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addAndGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addNandGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addOrGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addNorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addXorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addXnorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addAndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addOrnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addMuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addNmuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addAoi3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addOai3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addAoi4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addOai4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addBufGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addNotGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addAndGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addNandGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addOrGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addNorGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addXorGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addXnorGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addAndnotGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addOrnotGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addMuxGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addNmuxGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addAoi3Gate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addOai3Gate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addAoi4Gate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addOai4Gate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addSrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
RTLIL::Cell* addSrGate (Twine &&name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
const RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addFfGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, TwineRef src = Twine::Null);
RTLIL::Cell* addDffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDffsrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
RTLIL::Cell* addFfGate (Twine &&name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, TwineRef src = Twine::Null);
RTLIL::Cell* addDffGate (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDffeGate (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDffsrGate (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDffsreGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
RTLIL::Cell* addDffsreGate (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAdffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
RTLIL::Cell* addAdffGate (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
bool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAdffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
RTLIL::Cell* addAdffeGate (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
bool arst_value = false, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAldffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
RTLIL::Cell* addAldffGate (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAldffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
RTLIL::Cell* addAldffeGate (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addSdffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
RTLIL::Cell* addSdffGate (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
bool srst_value = false, bool clk_polarity = true, bool srst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addSdffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
RTLIL::Cell* addSdffeGate (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
bool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addSdffceGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
RTLIL::Cell* addSdffceGate (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
bool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDlatchGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAdlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
RTLIL::Cell* addDlatchGate (Twine &&name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAdlatchGate(Twine &&name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
bool arst_value = false, bool en_polarity = true, bool arst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDlatchsrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
RTLIL::Cell* addDlatchsrGate (Twine &&name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAnyinit(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, TwineRef src = Twine::Null);
RTLIL::Cell* addAnyinit(Twine &&name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, TwineRef src = Twine::Null);
// The methods without the add* prefix create a cell and an output signal. They return the newly created output signal.
RTLIL::SigSpec Not (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Pos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Buf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Neg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Not (Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Pos (Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Buf (Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Neg (Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec And (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Or (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Xor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Xnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec And (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Or (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Xor (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Xnor (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec ReduceAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec ReduceOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec ReduceXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec ReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec ReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec ReduceAnd (Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec ReduceOr (Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec ReduceXor (Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec ReduceXnor (Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec ReduceBool (Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Shl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Shr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Sshl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Sshr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Shift (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Shiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Shl (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Shr (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Sshl (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Sshr (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Shift (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Shiftx (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Lt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Le (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Eq (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Ne (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Eqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Nex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Ge (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Gt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Lt (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Le (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Eq (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Ne (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Eqx (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Nex (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Ge (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Gt (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Add (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Sub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Mul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Add (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Sub (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Mul (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
// truncating division
RTLIL::SigSpec Div (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Div (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
// truncating modulo
RTLIL::SigSpec Mod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec DivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec ModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Pow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool a_signed = false, bool b_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Mod (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec DivFloor (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec ModFloor (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Pow (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool a_signed = false, bool b_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec LogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec LogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec LogicOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec LogicNot (Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec LogicAnd (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec LogicOr (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Mux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null);
RTLIL::SigSpec Pmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null);
RTLIL::SigSpec Bmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null);
RTLIL::SigSpec Demux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null);
RTLIL::SigSpec Mux (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null);
RTLIL::SigSpec Pmux (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null);
RTLIL::SigSpec Bmux (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null);
RTLIL::SigSpec Demux (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null);
RTLIL::SigSpec Bweqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, TwineRef src = Twine::Null);
RTLIL::SigSpec Bwmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null);
RTLIL::SigSpec Bweqx (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, TwineRef src = Twine::Null);
RTLIL::SigSpec Bwmux (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null);
RTLIL::SigBit BufGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, TwineRef src = Twine::Null);
RTLIL::SigBit NotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, TwineRef src = Twine::Null);
RTLIL::SigBit AndGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
RTLIL::SigBit NandGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
RTLIL::SigBit OrGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
RTLIL::SigBit NorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
RTLIL::SigBit XorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
RTLIL::SigBit XnorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
RTLIL::SigBit AndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
RTLIL::SigBit OrnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
RTLIL::SigBit MuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, TwineRef src = Twine::Null);
RTLIL::SigBit NmuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, TwineRef src = Twine::Null);
RTLIL::SigBit Aoi3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, TwineRef src = Twine::Null);
RTLIL::SigBit Oai3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, TwineRef src = Twine::Null);
RTLIL::SigBit Aoi4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, TwineRef src = Twine::Null);
RTLIL::SigBit Oai4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, TwineRef src = Twine::Null);
RTLIL::SigBit BufGate (Twine &&name, const RTLIL::SigBit &sig_a, TwineRef src = Twine::Null);
RTLIL::SigBit NotGate (Twine &&name, const RTLIL::SigBit &sig_a, TwineRef src = Twine::Null);
RTLIL::SigBit AndGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
RTLIL::SigBit NandGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
RTLIL::SigBit OrGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
RTLIL::SigBit NorGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
RTLIL::SigBit XorGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
RTLIL::SigBit XnorGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
RTLIL::SigBit AndnotGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
RTLIL::SigBit OrnotGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
RTLIL::SigBit MuxGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, TwineRef src = Twine::Null);
RTLIL::SigBit NmuxGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, TwineRef src = Twine::Null);
RTLIL::SigBit Aoi3Gate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, TwineRef src = Twine::Null);
RTLIL::SigBit Oai3Gate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, TwineRef src = Twine::Null);
RTLIL::SigBit Aoi4Gate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, TwineRef src = Twine::Null);
RTLIL::SigBit Oai4Gate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, TwineRef src = Twine::Null);
};
// Zero-size masquerade for Module::name. Reads/writes route through
@ -2961,7 +2960,7 @@ public:
TwineRef src_id() const;
TwineRef src_ref() const { return src_id(); }
void set_src_id(TwineRef id);
void set_src_attribute(const RTLIL::SrcAttr &src);
void set_src_attribute(TwineRef src);
std::string get_src_attribute() const;
void adopt_src_from(const RTLIL::AttrObject *source);
void absorb_attrs(dict<RTLIL::IdString, RTLIL::Const> &&buf);
@ -2970,7 +2969,7 @@ public:
virtual ~Module();
virtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail = false);
virtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail = false);
virtual size_t count_id(Twine* id);
virtual size_t count_id(TwineRef id);
virtual void expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces);
virtual bool reprocess_if_necessary(RTLIL::Design *design);
@ -2992,7 +2991,7 @@ public:
void fixup_ports();
pool<RTLIL::Cell *> buf_norm_cell_queue;
pool<pair<RTLIL::Cell *, RTLIL::IdString>> buf_norm_cell_port_queue;
pool<pair<RTLIL::Cell *, TwineRef>> buf_norm_cell_port_queue;
pool<RTLIL::Wire *> buf_norm_wire_queue;
pool<RTLIL::Cell *> pending_deleted_cells;
dict<RTLIL::Wire *, pool<RTLIL::Cell *>> buf_norm_connect_index;
@ -3057,7 +3056,7 @@ public:
std::vector<RTLIL::NamedObject*> selected_members() const;
template<typename T> bool selected(T *member) const {
return design->selected_member(name, member->name);
return design->selected_member(meta_->name, member->meta_->name);
}
// Primary (fast) overloads — key directly into the dict.
@ -3093,29 +3092,35 @@ public:
void remove(RTLIL::Memory *memory);
void remove(RTLIL::Process *process);
void rename(RTLIL::Wire *wire, RTLIL::IdString new_name);
void rename(RTLIL::Cell *cell, RTLIL::IdString new_name);
void rename(RTLIL::IdString old_name, RTLIL::IdString new_name);
void rename(RTLIL::Wire *wire, TwineRef new_name);
void rename(RTLIL::Cell *cell, TwineRef new_name);
void rename(TwineRef old_name, TwineRef new_name);
void swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2);
void swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2);
RTLIL::IdString uniquify(RTLIL::IdString name);
RTLIL::IdString uniquify(RTLIL::IdString name, int &index);
TwineRef uniquify(TwineRef name);
TwineRef uniquify(TwineRef name, int &index);
// Primary overloads: name already interned in design->twines.
RTLIL::Wire *addWire(TwineRef name, int width = 1);
RTLIL::Wire *addWire(TwineRef name, const RTLIL::Wire *other);
// IdString compatibility: interns name into twines, then dispatches.
RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);
RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);
// Convenience: adds name into twines, then dispatches.
RTLIL::Wire *addWire(Twine &&name, int width = 1);
RTLIL::Wire *addWire(Twine &&name, const RTLIL::Wire *other);
// Primary overloads.
RTLIL::Cell *addCell(TwineRef name, RTLIL::IdString type);
RTLIL::Cell *addCell(TwineRef name, const RTLIL::Cell *other);
// IdString compatibility.
RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);
RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other);
// Convenience.
RTLIL::Cell *addCell(Twine &&name, RTLIL::IdString type);
RTLIL::Cell *addCell(Twine &&name, const RTLIL::Cell *other);
// NEW_ID analog for twine names; see NEW_TWINE in yosys_common.h.
TwineRef new_name(const std::string *prefix) {
TwineRef pref = design->twines.add(Twine{*prefix});
return design->twines.add(Twine{Twine::Suffix{pref, std::to_string(autoidx++)}});
}
RTLIL::Memory *addMemory(RTLIL::IdString name);
RTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other);
@ -3129,18 +3134,18 @@ public:
// The methods without the add* prefix create a cell and an output signal. They return the newly created output signal.
RTLIL::SigSpec Anyconst (RTLIL::IdString name, int width = 1, TwineRef src = Twine::Null);
RTLIL::SigSpec Anyseq (RTLIL::IdString name, int width = 1, TwineRef src = Twine::Null);
RTLIL::SigSpec Allconst (RTLIL::IdString name, int width = 1, TwineRef src = Twine::Null);
RTLIL::SigSpec Allseq (RTLIL::IdString name, int width = 1, TwineRef src = Twine::Null);
RTLIL::SigSpec Initstate (RTLIL::IdString name, TwineRef src = Twine::Null);
RTLIL::SigSpec Anyconst (TwineRef name, int width = 1, TwineRef src = Twine::Null);
RTLIL::SigSpec Anyseq (TwineRef name, int width = 1, TwineRef src = Twine::Null);
RTLIL::SigSpec Allconst (TwineRef name, int width = 1, TwineRef src = Twine::Null);
RTLIL::SigSpec Allseq (TwineRef name, int width = 1, TwineRef src = Twine::Null);
RTLIL::SigSpec Initstate (TwineRef name, TwineRef src = Twine::Null);
RTLIL::SigSpec SetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, TwineRef src = Twine::Null);
RTLIL::Cell* addSetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::SigSpec GetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, TwineRef src = Twine::Null);
RTLIL::Cell* addOverwriteTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, TwineRef src = Twine::Null);
RTLIL::SigSpec OriginalTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, TwineRef src = Twine::Null);
RTLIL::SigSpec FutureFF (RTLIL::IdString name, const RTLIL::SigSpec &sig_e, TwineRef src = Twine::Null);
RTLIL::SigSpec SetTag (TwineRef name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, TwineRef src = Twine::Null);
RTLIL::Cell* addSetTag (TwineRef name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::SigSpec GetTag (TwineRef name, const std::string &tag, const RTLIL::SigSpec &sig_a, TwineRef src = Twine::Null);
RTLIL::Cell* addOverwriteTag (TwineRef name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, TwineRef src = Twine::Null);
RTLIL::SigSpec OriginalTag (TwineRef name, const std::string &tag, const RTLIL::SigSpec &sig_a, TwineRef src = Twine::Null);
RTLIL::SigSpec FutureFF (TwineRef name, const RTLIL::SigSpec &sig_e, TwineRef src = Twine::Null);
std::string to_rtlil_str() const;
#ifdef YOSYS_ENABLE_PYTHON
@ -3276,7 +3281,7 @@ inline RTLIL::WireNameMasq::operator RTLIL::IdString() const {
reinterpret_cast<const char *>(this) - offsetof(RTLIL::Wire, name));
if (!w->module || !w->module->design || !w->meta_)
return RTLIL::IdString{};
TwineRef id = w->meta_->name_id;
TwineRef id = w->meta_->name;
if (id == Twine::Null)
return RTLIL::IdString{};
return RTLIL::IdString(w->module->design->twines.flat_string(id));
@ -3287,7 +3292,7 @@ inline RTLIL::CellNameMasq::operator RTLIL::IdString() const {
reinterpret_cast<const char *>(this) - offsetof(RTLIL::Cell, name));
if (!c->module || !c->module->design || !c->meta_)
return RTLIL::IdString{};
TwineRef id = c->meta_->name_id;
TwineRef id = c->meta_->name;
if (id == Twine::Null)
return RTLIL::IdString{};
return RTLIL::IdString(c->module->design->twines.flat_string(id));

97
kernel/rtlil_bufnorm.cc
View File

@ -20,6 +20,7 @@
#include "kernel/yosys.h"
#include "kernel/sigtools.h"
#include "kernel/modtools.h"
#include "kernel/yosys_common.h"
#include <string.h>
#include <algorithm>
@ -28,7 +29,7 @@
YOSYS_NAMESPACE_BEGIN
typedef std::pair<Cell*, IdString> cell_port_t;
typedef std::pair<Cell*, TwineRef> cell_port_t;
// Since this is kernel code, we only log with yosys_xtrace set to not get
// in the way when using `debug` to debug specific passes.q
@ -83,7 +84,7 @@ struct RTLIL::SigNormIndex
if (cell->type != ID($input_port))
continue;
auto const &sig_y = cell->getPort(ID::Y);
auto const &sig_y = cell->getPort(TW::Y);
Wire *wire;
if (sig_y.is_wire() && (wire = sig_y.as_wire())->port_input && !wire->port_output && !input_port_cells.count(wire))
input_port_cells.emplace(wire, cell);
@ -97,16 +98,16 @@ struct RTLIL::SigNormIndex
for (auto portname : module->ports) {
Wire *wire = module->wire(portname);
if (wire->port_input && !wire->port_output && !input_port_cells.count(wire)) {
Cell *cell = module->addCell(NEW_ID, ID($input_port));
Cell *cell = module->addCell(NEW_TWINE, ID($input_port));
cell->setParam(ID::WIDTH, GetSize(wire));
cell->setPort(ID::Y, wire);
cell->setPort(TW::Y, wire);
input_port_cells.emplace(wire, cell);
}
}
for (auto [wire, cell] : input_port_cells) {
wire->driverCell_ = cell;
wire->driverPort_ = ID::Y;
wire->driverPort_ = TW::Y;
}
}
@ -130,7 +131,7 @@ struct RTLIL::SigNormIndex
}
}
Wire *wire = module->addWire(NEW_ID, GetSize(sig));
Wire *wire = module->addWire(NEW_TWINE, GetSize(sig));
wire->driverCell_ = cell;
wire->driverPort_ = port;
@ -194,11 +195,11 @@ struct RTLIL::SigNormIndex
}
if (!connect_lhs.empty()) {
Cell *cell = module->addCell(NEW_ID, ID($connect));
Cell *cell = module->addCell(NEW_TWINE, ID($connect));
xlog("add connect (1) %s\n", cell->name);
cell->setParam(ID::WIDTH, GetSize(connect_lhs));
cell->setPort(ID::A, std::move(connect_lhs));
cell->setPort(ID::B, std::move(connect_rhs));
cell->setPort(TW::A, std::move(connect_lhs));
cell->setPort(TW::B, std::move(connect_rhs));
}
}
@ -287,7 +288,7 @@ void RTLIL::Design::bufNormalize(bool enable)
module->buf_norm_cell_port_queue.clear();
for (auto wire : module->wires()) {
wire->driverCell_ = nullptr;
wire->driverPort_ = IdString();
wire->driverPort_ = Twine::Null;
}
module->buf_norm_connect_index.clear();
}
@ -348,7 +349,7 @@ void RTLIL::Design::sigNormalize(bool enable)
for (auto wire : module->wires()) {
wire->driverCell_ = nullptr;
wire->driverPort_ = IdString();
wire->driverPort_ = Twine::Null;
}
// TODO inefficient?
@ -520,14 +521,14 @@ void RTLIL::Module::remove(RTLIL::Cell *cell)
while (!cell->connections_.empty())
cell->unsetPort(cell->connections_.begin()->first);
log_assert(cell->meta_ && cell->meta_->name_id != Twine::Null);
TwineRef cell_id = cell->meta_->name_id;
log_assert(cell->meta_ && cell->meta_->name != Twine::Null);
TwineRef cell_id = cell->meta_->name;
log_assert(cells_.count(cell_id) != 0);
log_assert(refcount_cells_ == 0);
cells_.erase(cell_id);
if (design && design->flagBufferedNormalized && buf_norm_cell_queue.count(cell)) {
cell->type.clear();
design->obj_release_name_id(cell);
// design->obj_release_name(cell);
pending_deleted_cells.insert(cell);
} else {
if (sig_norm_index != nullptr) {
@ -561,12 +562,12 @@ void RTLIL::Module::bufNormalize()
if (wire->port_input && !wire->port_output) {
if (wire->driverCell_ != nullptr && wire->driverCell_->type != ID($input_port)) {
wire->driverCell_ = nullptr;
wire->driverPort_.clear();
wire->driverPort_ = Twine::Null;
}
if (wire->driverCell_ == nullptr) {
Cell *input_port_cell = addCell(NEW_ID, ID($input_port));
Cell *input_port_cell = addCell(NEW_TWINE, ID($input_port));
input_port_cell->setParam(ID::WIDTH, GetSize(wire));
input_port_cell->setPort(ID::Y, wire); // this hits the fast path that doesn't mutate the queues
input_port_cell->setPort(TW::Y, wire); // this hits the fast path that doesn't mutate the queues
}
}
}
@ -593,19 +594,19 @@ void RTLIL::Module::bufNormalize()
// because it's not driving an input port or because there already is
// another $input_port driver for the same port, we also delete that
// $input_port cell.
dict<Wire *, std::pair<Cell *, IdString>> direct_driven_wires;
dict<Wire *, std::pair<Cell *, TwineRef>> direct_driven_wires;
// Set of cell ports that need a fresh intermediate wire. These are all
// cell ports that drive non-full-wire sigspecs, cell ports driving
// module input ports, and cell ports driving wires that are already
// driven.
pool<std::pair<Cell *, IdString>> pending_ports;
pool<std::pair<Cell *, TwineRef>> pending_ports;
// This helper will be called for every output/inout cell port that is
// already enqueued or becomes reachable when denormalizing $buf or
// $connect cells.
auto enqueue_cell_port = [&](Cell *cell, IdString port) {
xlog("processing cell port %s.%s\n", cell, port.unescape());
auto enqueue_cell_port = [&](Cell *cell, TwineRef port) {
xlog("processing cell port %s.%s\n", cell, design->twines.str(port));
// An empty cell type means the cell got removed
if (cell->type.empty())
@ -632,8 +633,8 @@ void RTLIL::Module::bufNormalize()
// TODO: We could defer removing the $buf cells here, and
// re-use them in case we would create a new identical cell
// later.
log_assert(port == ID::Y);
SigSpec sig_a = cell->getPort(ID::A);
log_assert(port == TW::Y);
SigSpec sig_a = cell->getPort(TW::A);
SigSpec sig_y = sig;
for (auto const &s : {sig_a, sig})
@ -662,7 +663,7 @@ void RTLIL::Module::bufNormalize()
buf_norm_wire_queue.clear();
return;
} else if (cell->type == ID($input_port)) {
log_assert(port == ID::Y);
log_assert(port == TW::Y);
if (sig.is_wire()) {
Wire *w = sig.as_wire();
if (w->port_input && !w->port_output) {
@ -733,7 +734,7 @@ void RTLIL::Module::bufNormalize()
if (wire->driverCell_) {
Cell *cell = wire->driverCell_;
IdString port = wire->driverPort_;
TwineRef port = wire->driverPort_;
enqueue_cell_port(cell, port);
}
@ -744,8 +745,8 @@ void RTLIL::Module::bufNormalize()
while (!found->second.empty()) {
Cell *connect_cell = *found->second.begin();
log_assert(connect_cell->type == ID($connect));
SigSpec const &sig_a = connect_cell->getPort(ID::A);
SigSpec const &sig_b = connect_cell->getPort(ID::B);
SigSpec const &sig_a = connect_cell->getPort(TW::A);
SigSpec const &sig_b = connect_cell->getPort(TW::B);
xlog("found $connect cell %s: %s <-> %s\n", connect_cell, log_signal(sig_a), log_signal(sig_b));
for (auto &side : {sig_a, sig_b})
for (auto chunk : side.chunks())
@ -772,7 +773,7 @@ void RTLIL::Module::bufNormalize()
log_assert(!cell->type.empty());
log_assert(!pending_deleted_cells.count(cell));
SigSpec const &sig = cell->getPort(port);
Wire *w = addWire(NEW_ID, GetSize(sig));
Wire *w = addWire(NEW_TWINE, GetSize(sig));
// We update the module level connections, `direct_driven_wires`
// and `direct_driven_wires_conflicts` in such a way that they
@ -792,7 +793,7 @@ void RTLIL::Module::bufNormalize()
// to keep track of the wires that we still have to update.
for (auto wire : wire_queue_entries) {
wire->driverCell_ = nullptr;
wire->driverPort_.clear();
wire->driverPort_ = Twine::Null;
}
// For the unique driving cell ports fully connected to a full wire, we
@ -912,7 +913,7 @@ void RTLIL::Module::bufNormalize()
if (wire->driverCell_ == nullptr) {
xlog("wire %s drivers %s\n", wire, log_signal(wire_drivers));
addBuf(NEW_ID, wire_drivers, wire);
addBuf(NEW_TWINE, wire_drivers, wire);
}
}
@ -946,10 +947,10 @@ void RTLIL::Module::bufNormalize()
if (sig_a.empty())
return;
xlog("connect %s <-> %s\n", log_signal(sig_a), log_signal(sig_b));
Cell *connect_cell = addCell(NEW_ID, ID($connect));
Cell *connect_cell = addCell(NEW_TWINE, ID($connect));
connect_cell->setParam(ID::WIDTH, GetSize(sig_a));
connect_cell->setPort(ID::A, sig_a);
connect_cell->setPort(ID::B, sig_b);
connect_cell->setPort(TW::A, sig_a);
connect_cell->setPort(TW::B, sig_b);
sig_a = SigSpec();
sig_b = SigSpec();
};
@ -985,7 +986,7 @@ void RTLIL::Module::bufNormalize()
pending_deleted_cells.clear();
}
void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
void RTLIL::Cell::unsetPort(TwineRef portname)
{
RTLIL::SigSpec signal;
auto conn_it = connections_.find(portname);
@ -1000,7 +1001,7 @@ void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
mon->notify_connect(this, conn_it->first, conn_it->second, signal);
if (yosys_xtrace) {
log("#X# Unconnect %s.%s.%s\n", this->module, this, portname.unescape());
log("#X# Unconnect %s.%s.%s\n", module, this, module->design->twines.str(portname));
log_backtrace("-X- ", yosys_xtrace-1);
}
@ -1026,14 +1027,14 @@ void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
log_assert(w->driverCell_ == this);
log_assert(w->driverPort_ == portname);
w->driverCell_ = nullptr;
w->driverPort_ = IdString();
w->driverPort_ = Twine::Null;
}
// bool clear_fanout = true;
// if (conn_it->second.is_wire()) {
// Wire *w = conn_it->second.as_wire();
// if (w->driverCell_ == this && w->driverPort_ == portname) {
// w->driverCell_ = nullptr;
// w->driverPort_ = IdString();
// w->driverPort_ = Twine::Null;
// clear_fanout = false;
// }
// }
@ -1058,7 +1059,7 @@ void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
Wire *w = conn_it->second.as_wire();
if (w->driverCell_ == this && w->driverPort_ == portname) {
w->driverCell_ = nullptr;
w->driverPort_ = IdString();
w->driverPort_ = Twine::Null;
module->buf_norm_wire_queue.insert(w);
} else if (w->driverCell_) {
log_assert(w->driverCell_->getPort(w->driverPort_) == w);
@ -1099,7 +1100,7 @@ static bool ignored_cell(const RTLIL::IdString& type)
return type == ID($specify2) || type == ID($specify3) || type == ID($specrule);
}
void RTLIL::Cell::signorm_index_remove(IdString portname, const SigSpec &old_signal, bool is_input)
void RTLIL::Cell::signorm_index_remove(TwineRef portname, const SigSpec &old_signal, bool is_input)
{
auto &index = *module->sig_norm_index;
index.dirty.insert(this);
@ -1121,11 +1122,11 @@ void RTLIL::Cell::signorm_index_remove(IdString portname, const SigSpec &old_sig
log_assert(w->driverCell_ == this);
log_assert(w->driverPort_ == portname);
w->driverCell_ = nullptr;
w->driverPort_ = IdString();
w->driverPort_ = Twine::Null;
}
}
void RTLIL::Cell::signorm_index_add(IdString portname, const SigSpec &new_signal, bool is_input)
void RTLIL::Cell::signorm_index_add(TwineRef portname, const SigSpec &new_signal, bool is_input)
{
auto &index = *module->sig_norm_index;
index.dirty.insert(this);
@ -1140,7 +1141,7 @@ void RTLIL::Cell::signorm_index_add(IdString portname, const SigSpec &new_signal
} else if (GetSize(new_signal)) {
Wire *w = new_signal.as_wire();
log_assert(w->driverCell_ == nullptr);
log_assert(w->driverPort_.empty());
log_assert(w->driverPort_ == Twine::Null);
w->driverCell_ = this;
w->driverPort_ = portname;
}
@ -1148,14 +1149,14 @@ void RTLIL::Cell::signorm_index_add(IdString portname, const SigSpec &new_signal
// Handles the bufnorm part of setPort. Updates conn_it->second and returns true if the
// connection was stored (fast path or $connect cell). If false, caller must store signal.
bool RTLIL::Cell::bufnorm_handle_setPort(IdString portname, SigSpec &signal, dict<IdString, SigSpec>::iterator conn_it)
bool RTLIL::Cell::bufnorm_handle_setPort(TwineRef portname, SigSpec &signal, dict<TwineRef, SigSpec>::iterator conn_it)
{
// Eagerly clear a driver that got disconnected by changing this port connection
if (conn_it->second.is_wire()) {
Wire *w = conn_it->second.as_wire();
if (w->driverCell_ == this && w->driverPort_ == portname) {
w->driverCell_ = nullptr;
w->driverPort_ = IdString();
w->driverPort_ = Twine::Null;
module->buf_norm_wire_queue.insert(w);
}
}
@ -1260,7 +1261,7 @@ void RTLIL::Cell::setPort(TwineRef portname, RTLIL::SigSpec signal)
if (signal.is_wire() && (wire = signal.as_wire())->driverCell_ != nullptr)
wire = nullptr;
if (wire == nullptr) {
wire = module->addWire(NEW_ID, GetSize(signal));
wire = module->addWire(NEW_TWINE, GetSize(signal));
module->connect(signal, wire);
signal = wire;
}
@ -1282,7 +1283,7 @@ void RTLIL::Cell::setPort(TwineRef portname, RTLIL::SigSpec signal)
}
if (yosys_xtrace) {
log("#X# Connect %s.%s.%s = %s (%d)\n", this->module ? this->module->name.unescape() : "PATCH", this, portname.unescape(), log_signal(signal), GetSize(signal));
log("#X# Connect %s.%s.%s = %s (%d)\n", module ? module->name.unescape() : "PATCH", this, module->design->twines.str(portname), log_signal(signal), GetSize(signal));
log_backtrace("-X- ", yosys_xtrace-1);
}
@ -1302,9 +1303,9 @@ void RTLIL::Cell::setPort(TwineRef portname, RTLIL::SigSpec signal)
void RTLIL::Design::add(RTLIL::Module *module)
{
log_assert(modules_.count(module->name) == 0);
log_assert(modules_.count(module->meta_->name) == 0);
log_assert(refcount_modules_ == 0);
modules_[module->name] = module;
modules_[module->meta_->name] = module;
module->design = this;
for (auto mon : monitors)

356
kernel/satgen.cc
View File

@ -30,9 +30,9 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef && (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor)) || is_arith_compare))
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
if (is_arith_compare)
extendSignalWidth(undef_a, undef_b, cell, true);
else
@ -43,7 +43,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
int undef_y_bit = ez->OR(undef_any_a, undef_any_b);
if (cell->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) {
std::vector<int> b = importSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> b = importSigSpec(cell->getPort(TW::B), timestep);
undef_y_bit = ez->OR(undef_y_bit, ez->NOT(ez->expression(ezSAT::OpOr, b)));
}
@ -62,9 +62,9 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_),
ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($sub)))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
extendSignalWidth(a, b, y, cell);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@ -92,9 +92,9 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef && !arith_undef_handled)
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
extendSignalWidth(undef_a, undef_b, undef_y, cell, false);
if (cell->type.in(ID($and), ID($_AND_), ID($_NAND_))) {
@ -133,7 +133,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
}
else if (model_undef)
{
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
undefGating(y, yy, undef_y);
}
return true;
@ -144,11 +144,11 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
bool aoi_mode = cell->type.in(ID($_AOI3_), ID($_AOI4_));
bool three_mode = cell->type.in(ID($_AOI3_), ID($_OAI3_));
int a = importDefSigSpec(cell->getPort(ID::A), timestep).at(0);
int b = importDefSigSpec(cell->getPort(ID::B), timestep).at(0);
int c = importDefSigSpec(cell->getPort(ID::C), timestep).at(0);
int d = three_mode ? (aoi_mode ? ez->CONST_TRUE : ez->CONST_FALSE) : importDefSigSpec(cell->getPort(ID::D), timestep).at(0);
int y = importDefSigSpec(cell->getPort(ID::Y), timestep).at(0);
int a = importDefSigSpec(cell->getPort(TW::A), timestep).at(0);
int b = importDefSigSpec(cell->getPort(TW::B), timestep).at(0);
int c = importDefSigSpec(cell->getPort(TW::C), timestep).at(0);
int d = three_mode ? (aoi_mode ? ez->CONST_TRUE : ez->CONST_FALSE) : importDefSigSpec(cell->getPort(TW::D), timestep).at(0);
int y = importDefSigSpec(cell->getPort(TW::Y), timestep).at(0);
int yy = model_undef ? ez->literal() : y;
if (cell->type.in(ID($_AOI3_), ID($_AOI4_)))
@ -158,11 +158,11 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef)
{
int undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep).at(0);
int undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep).at(0);
int undef_c = importUndefSigSpec(cell->getPort(ID::C), timestep).at(0);
int undef_d = three_mode ? ez->CONST_FALSE : importUndefSigSpec(cell->getPort(ID::D), timestep).at(0);
int undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep).at(0);
int undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep).at(0);
int undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep).at(0);
int undef_c = importUndefSigSpec(cell->getPort(TW::C), timestep).at(0);
int undef_d = three_mode ? ez->CONST_FALSE : importUndefSigSpec(cell->getPort(TW::D), timestep).at(0);
int undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep).at(0);
if (aoi_mode)
{
@ -207,16 +207,16 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type.in(ID($_NOT_), ID($not)))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
extendSignalWidthUnary(a, y, cell);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
ez->assume(ez->vec_eq(ez->vec_not(a), yy));
if (model_undef) {
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
extendSignalWidthUnary(undef_a, undef_y, cell, false);
ez->assume(ez->vec_eq(undef_a, undef_y));
undefGating(y, yy, undef_y);
@ -226,17 +226,17 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type == ID($bweqx))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
std::vector<int> bweqx = ez->vec_not(ez->vec_xor(a, b));
if (model_undef)
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
std::vector<int> both_undef = ez->vec_and(undef_a, undef_b);
std::vector<int> both_def = ez->vec_and(ez->vec_not(undef_a), ez->vec_not(undef_b));
@ -252,10 +252,10 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type.in(ID($_MUX_), ID($mux), ID($_NMUX_), ID($bwmux)))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> s = importDefSigSpec(cell->getPort(ID::S), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> s = importDefSigSpec(cell->getPort(TW::S), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
if (cell->type == ID($_NMUX_))
@ -267,10 +267,10 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef)
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> undef_s = importUndefSigSpec(cell->getPort(ID::S), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> undef_s = importUndefSigSpec(cell->getPort(TW::S), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
std::vector<int> unequal_ab = ez->vec_not(ez->vec_iff(a, b));
std::vector<int> undef_ab = ez->vec_or(unequal_ab, ez->vec_or(undef_a, undef_b));
@ -287,16 +287,16 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type == ID($bmux))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> s = importDefSigSpec(cell->getPort(ID::S), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> s = importDefSigSpec(cell->getPort(TW::S), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
std::vector<int> undef_a, undef_s, undef_y;
if (model_undef)
{
undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
undef_s = importUndefSigSpec(cell->getPort(ID::S), timestep);
undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
undef_s = importUndefSigSpec(cell->getPort(TW::S), timestep);
undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
}
if (GetSize(s) == 0) {
@ -335,17 +335,17 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type == ID($demux))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> s = importDefSigSpec(cell->getPort(ID::S), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> s = importDefSigSpec(cell->getPort(TW::S), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
std::vector<int> undef_a, undef_s, undef_y;
if (model_undef)
{
undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
undef_s = importUndefSigSpec(cell->getPort(ID::S), timestep);
undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
undef_s = importUndefSigSpec(cell->getPort(TW::S), timestep);
undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
}
if (GetSize(s) == 0) {
@ -387,10 +387,10 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type == ID($pmux))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> s = importDefSigSpec(cell->getPort(ID::S), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> s = importDefSigSpec(cell->getPort(TW::S), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@ -403,10 +403,10 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef)
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> undef_s = importUndefSigSpec(cell->getPort(ID::S), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> undef_s = importUndefSigSpec(cell->getPort(TW::S), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
int all_undef = ez->CONST_FALSE;
int found_active = ez->CONST_FALSE;
@ -433,8 +433,8 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type.in(ID($pos), ID($buf), ID($neg)))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
extendSignalWidthUnary(a, y, cell);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@ -448,8 +448,8 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef)
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
extendSignalWidthUnary(undef_a, undef_y, cell);
if (cell->type.in(ID($pos), ID($buf))) {
@ -467,8 +467,8 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type.in(ID($connect)))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(TW::B), timestep);
extendSignalWidthUnary(a, b, cell);
std::vector<int> bb = model_undef ? ez->vec_var(b.size()) : b;
@ -476,8 +476,8 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef)
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep);
extendSignalWidthUnary(undef_a, undef_b, cell);
ez->assume(ez->vec_eq(undef_a, undef_b));
undefGating(b, bb, undef_b);
@ -487,8 +487,8 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool), ID($logic_not)))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@ -507,8 +507,8 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef)
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
int aX = ez->expression(ezSAT::OpOr, undef_a);
if (cell->type == ID($reduce_and)) {
@ -534,12 +534,12 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type.in(ID($logic_and), ID($logic_or)))
{
std::vector<int> vec_a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> vec_b = importDefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> vec_a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> vec_b = importDefSigSpec(cell->getPort(TW::B), timestep);
int a = ez->expression(ez->OpOr, vec_a);
int b = ez->expression(ez->OpOr, vec_b);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@ -552,9 +552,9 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef)
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
int a0 = ez->NOT(ez->OR(ez->expression(ezSAT::OpOr, vec_a), ez->expression(ezSAT::OpOr, undef_a)));
int b0 = ez->NOT(ez->OR(ez->expression(ezSAT::OpOr, vec_b), ez->expression(ezSAT::OpOr, undef_b)));
@ -581,16 +581,16 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt)))
{
bool is_signed = cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool();
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
extendSignalWidth(a, b, cell);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
if (model_undef && cell->type.in(ID($eqx), ID($nex))) {
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep);
extendSignalWidth(undef_a, undef_b, cell, true);
a = ez->vec_or(a, undef_a);
b = ez->vec_or(b, undef_b);
@ -613,9 +613,9 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef && cell->type.in(ID($eqx), ID($nex)))
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
extendSignalWidth(undef_a, undef_b, cell, true);
if (cell->type == ID($eqx))
@ -630,9 +630,9 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
}
else if (model_undef && cell->type.in(ID($eq), ID($ne)))
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
extendSignalWidth(undef_a, undef_b, cell, true);
int undef_any_a = ez->expression(ezSAT::OpOr, undef_a);
@ -654,7 +654,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
else
{
if (model_undef) {
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
undefGating(y, yy, undef_y);
}
log_assert(!model_undef || arith_undef_handled);
@ -664,9 +664,9 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
int extend_bit = ez->CONST_FALSE;
@ -697,9 +697,9 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef)
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
std::vector<int> undef_a_shifted;
extend_bit = cell->type == ID($shiftx) ? ez->CONST_TRUE : ez->CONST_FALSE;
@ -736,9 +736,9 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type == ID($mul))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
extendSignalWidth(a, b, y, cell);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@ -755,7 +755,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef) {
log_assert(arith_undef_handled);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
undefGating(y, yy, undef_y);
}
return true;
@ -763,8 +763,8 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type.in(ID($macc), ID($macc_v2)))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
Macc macc;
macc.from_cell(cell);
@ -807,19 +807,19 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef)
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> undef_c;
if (cell->type == ID($macc_v2))
undef_c = importUndefSigSpec(cell->getPort(ID::C), timestep);
undef_c = importUndefSigSpec(cell->getPort(TW::C), timestep);
int undef_any_a = ez->expression(ezSAT::OpOr, undef_a);
int undef_any_b = ez->expression(ezSAT::OpOr, undef_b);
int undef_any_c = ez->expression(ezSAT::OpOr, undef_c);
int undef_any = ez->OR(undef_any_a, ez->OR(undef_any_b, undef_any_c));
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
ez->assume(ez->vec_eq(undef_y, std::vector<int>(GetSize(y), undef_any)));
undefGating(y, tmp, undef_y);
@ -832,9 +832,9 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor)))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
extendSignalWidth(a, b, y, cell);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@ -913,12 +913,12 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
only_first_one.at(0) = ez->CONST_TRUE;
div_zero_result = ez->vec_ite(a.back(), only_first_one, all_ones);
} else {
div_zero_result.insert(div_zero_result.end(), cell->getPort(ID::A).size(), ez->CONST_TRUE);
div_zero_result.insert(div_zero_result.end(), cell->getPort(TW::A).size(), ez->CONST_TRUE);
div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->CONST_FALSE);
}
} else if (cell->type.in(ID($mod), ID($modfloor))) {
// a mod 0 = a
int copy_a_bits = min(cell->getPort(ID::A).size(), cell->getPort(ID::B).size());
int copy_a_bits = min(cell->getPort(TW::A).size(), cell->getPort(TW::B).size());
div_zero_result.insert(div_zero_result.end(), a.begin(), a.begin() + copy_a_bits);
if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool())
div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), div_zero_result.back());
@ -930,7 +930,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef) {
log_assert(arith_undef_handled);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
undefGating(y, yy, undef_y);
}
return true;
@ -938,8 +938,8 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type == ID($lut))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
std::vector<int> lut;
for (auto bit : cell->getParam(ID::LUT))
@ -950,7 +950,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef)
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> t(lut), u(GetSize(t), ez->CONST_FALSE);
for (int i = GetSize(a)-1; i >= 0; i--)
@ -968,7 +968,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
log_assert(GetSize(t) == 1);
log_assert(GetSize(u) == 1);
undefGating(y, t, u);
ez->assume(ez->vec_eq(importUndefSigSpec(cell->getPort(ID::Y), timestep), u));
ez->assume(ez->vec_eq(importUndefSigSpec(cell->getPort(TW::Y), timestep), u));
}
else
{
@ -988,8 +988,8 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type == ID($sop))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
int y = importDefSigSpec(cell->getPort(ID::Y), timestep).at(0);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
int y = importDefSigSpec(cell->getPort(TW::Y), timestep).at(0);
int width = cell->getParam(ID::WIDTH).as_int();
int depth = cell->getParam(ID::DEPTH).as_int();
@ -1017,8 +1017,8 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef)
{
std::vector<int> products, undef_products;
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
int undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep).at(0);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
int undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep).at(0);
for (int i = 0; i < depth; i++)
{
@ -1070,11 +1070,11 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type == ID($fa))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> c = importDefSigSpec(cell->getPort(ID::C), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> x = importDefSigSpec(cell->getPort(ID::X), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> c = importDefSigSpec(cell->getPort(TW::C), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
std::vector<int> x = importDefSigSpec(cell->getPort(TW::X), timestep);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
std::vector<int> xx = model_undef ? ez->vec_var(x.size()) : x;
@ -1088,12 +1088,12 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef)
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> undef_c = importUndefSigSpec(cell->getPort(ID::C), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> undef_c = importUndefSigSpec(cell->getPort(TW::C), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_x = importUndefSigSpec(cell->getPort(ID::X), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
std::vector<int> undef_x = importUndefSigSpec(cell->getPort(TW::X), timestep);
ez->assume(ez->vec_eq(undef_y, ez->vec_or(ez->vec_or(undef_a, undef_b), undef_c)));
ez->assume(ez->vec_eq(undef_x, undef_y));
@ -1106,10 +1106,10 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type == ID($lcu))
{
std::vector<int> p = importDefSigSpec(cell->getPort(ID::P), timestep);
std::vector<int> g = importDefSigSpec(cell->getPort(ID::G), timestep);
std::vector<int> ci = importDefSigSpec(cell->getPort(ID::CI), timestep);
std::vector<int> co = importDefSigSpec(cell->getPort(ID::CO), timestep);
std::vector<int> p = importDefSigSpec(cell->getPort(TW::P), timestep);
std::vector<int> g = importDefSigSpec(cell->getPort(TW::G), timestep);
std::vector<int> ci = importDefSigSpec(cell->getPort(TW::CI), timestep);
std::vector<int> co = importDefSigSpec(cell->getPort(TW::CO), timestep);
std::vector<int> yy = model_undef ? ez->vec_var(co.size()) : co;
@ -1118,10 +1118,10 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef)
{
std::vector<int> undef_p = importUndefSigSpec(cell->getPort(ID::P), timestep);
std::vector<int> undef_g = importUndefSigSpec(cell->getPort(ID::G), timestep);
std::vector<int> undef_ci = importUndefSigSpec(cell->getPort(ID::CI), timestep);
std::vector<int> undef_co = importUndefSigSpec(cell->getPort(ID::CO), timestep);
std::vector<int> undef_p = importUndefSigSpec(cell->getPort(TW::P), timestep);
std::vector<int> undef_g = importUndefSigSpec(cell->getPort(TW::G), timestep);
std::vector<int> undef_ci = importUndefSigSpec(cell->getPort(TW::CI), timestep);
std::vector<int> undef_co = importUndefSigSpec(cell->getPort(TW::CO), timestep);
int undef_any_p = ez->expression(ezSAT::OpOr, undef_p);
int undef_any_g = ez->expression(ezSAT::OpOr, undef_g);
@ -1138,13 +1138,13 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type == ID($alu))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> x = importDefSigSpec(cell->getPort(ID::X), timestep);
std::vector<int> ci = importDefSigSpec(cell->getPort(ID::CI), timestep);
std::vector<int> bi = importDefSigSpec(cell->getPort(ID::BI), timestep);
std::vector<int> co = importDefSigSpec(cell->getPort(ID::CO), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
std::vector<int> x = importDefSigSpec(cell->getPort(TW::X), timestep);
std::vector<int> ci = importDefSigSpec(cell->getPort(TW::CI), timestep);
std::vector<int> bi = importDefSigSpec(cell->getPort(TW::BI), timestep);
std::vector<int> co = importDefSigSpec(cell->getPort(TW::CO), timestep);
extendSignalWidth(a, b, y, cell);
extendSignalWidth(a, b, x, cell);
@ -1169,14 +1169,14 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef)
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> undef_ci = importUndefSigSpec(cell->getPort(ID::CI), timestep);
std::vector<int> undef_bi = importUndefSigSpec(cell->getPort(ID::BI), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> undef_ci = importUndefSigSpec(cell->getPort(TW::CI), timestep);
std::vector<int> undef_bi = importUndefSigSpec(cell->getPort(TW::BI), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_x = importUndefSigSpec(cell->getPort(ID::X), timestep);
std::vector<int> undef_co = importUndefSigSpec(cell->getPort(ID::CO), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
std::vector<int> undef_x = importUndefSigSpec(cell->getPort(TW::X), timestep);
std::vector<int> undef_co = importUndefSigSpec(cell->getPort(TW::CO), timestep);
extendSignalWidth(undef_a, undef_b, undef_y, cell);
extendSignalWidth(undef_a, undef_b, undef_x, cell);
@ -1204,17 +1204,17 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type == ID($slice))
{
RTLIL::SigSpec a = cell->getPort(ID::A);
RTLIL::SigSpec y = cell->getPort(ID::Y);
RTLIL::SigSpec a = cell->getPort(TW::A);
RTLIL::SigSpec y = cell->getPort(TW::Y);
ez->assume(signals_eq(a.extract(cell->parameters.at(ID::OFFSET).as_int(), y.size()), y, timestep));
return true;
}
if (cell->type == ID($concat))
{
RTLIL::SigSpec a = cell->getPort(ID::A);
RTLIL::SigSpec b = cell->getPort(ID::B);
RTLIL::SigSpec y = cell->getPort(ID::Y);
RTLIL::SigSpec a = cell->getPort(TW::A);
RTLIL::SigSpec b = cell->getPort(TW::B);
RTLIL::SigSpec y = cell->getPort(TW::Y);
RTLIL::SigSpec ab = a;
ab.append(b);
@ -1233,18 +1233,18 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (timestep == 1)
{
initial_state.add((*sigmap)(cell->getPort(ID::Q)));
initial_state.add((*sigmap)(cell->getPort(TW::Q)));
if (model_undef && def_formal) {
std::vector<int> undef_q = importUndefSigSpec(cell->getPort(ID::Q), timestep);
std::vector<int> undef_q = importUndefSigSpec(cell->getPort(TW::Q), timestep);
ez->assume(ez->NOT(ez->vec_reduce_or(undef_q)));
}
}
else
{
std::vector<int> d = importDefSigSpec(cell->getPort(ID::D), timestep-1);
std::vector<int> d = importDefSigSpec(cell->getPort(TW::D), timestep-1);
std::vector<int> undef_d;
if (model_undef)
undef_d = importUndefSigSpec(cell->getPort(ID::D), timestep-1);
undef_d = importUndefSigSpec(cell->getPort(TW::D), timestep-1);
if (ff.has_srst && ff.has_ce && ff.ce_over_srst) {
int srst = importDefSigSpec(ff.sig_srst, timestep-1).at(0);
std::vector<int> rval = importDefSigSpec(ff.val_srst, timestep-1);
@ -1287,14 +1287,14 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
else
std::tie(d, undef_d) = mux(srst, undef_srst, rval, undef_rval, d, undef_d);
}
std::vector<int> q = importDefSigSpec(cell->getPort(ID::Q), timestep);
std::vector<int> q = importDefSigSpec(cell->getPort(TW::Q), timestep);
std::vector<int> qq = model_undef ? ez->vec_var(q.size()) : q;
ez->assume(ez->vec_eq(d, qq));
if (model_undef)
{
std::vector<int> undef_q = importUndefSigSpec(cell->getPort(ID::Q), timestep);
std::vector<int> undef_q = importUndefSigSpec(cell->getPort(TW::Q), timestep);
ez->assume(ez->vec_eq(undef_d, undef_q));
undefGating(q, qq, undef_q);
@ -1307,22 +1307,22 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
{
if (timestep < 2) {
if (model_undef && def_formal) {
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
ez->assume(ez->NOT(ez->vec_reduce_or(undef_y)));
}
return true;
}
std::vector<int> d = importDefSigSpec(cell->getPort(ID::Y), timestep-1);
std::vector<int> q = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> d = importDefSigSpec(cell->getPort(TW::Y), timestep-1);
std::vector<int> q = importDefSigSpec(cell->getPort(TW::Y), timestep);
std::vector<int> qq = (model_undef && !def_formal) ? ez->vec_var(q.size()) : q;
ez->assume(ez->vec_eq(d, qq));
if (model_undef)
{
std::vector<int> undef_d = importUndefSigSpec(cell->getPort(ID::Y), timestep-1);
std::vector<int> undef_q = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_d = importUndefSigSpec(cell->getPort(TW::Y), timestep-1);
std::vector<int> undef_q = importUndefSigSpec(cell->getPort(TW::Y), timestep);
if (def_formal) {
for (auto &undef_q_bit : undef_q)
@ -1338,7 +1338,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type == ID($anyseq))
{
if (model_undef && def_formal) {
std::vector<int> undef_q = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_q = importUndefSigSpec(cell->getPort(TW::Y), timestep);
for (auto &undef_q_bit : undef_q)
ez->SET(ez->CONST_FALSE, undef_q_bit);
}
@ -1347,16 +1347,16 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type.in(ID($_BUF_), ID($equiv)))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
extendSignalWidthUnary(a, y, cell);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
ez->assume(ez->vec_eq(a, yy));
if (model_undef) {
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
extendSignalWidthUnary(undef_a, undef_y, cell, false);
ez->assume(ez->vec_eq(undef_a, undef_y));
undefGating(y, yy, undef_y);
@ -1370,12 +1370,12 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (initstates.count(key) == 0)
initstates[key] = false;
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
log_assert(GetSize(y) == 1);
ez->SET(y[0], initstates[key] ? ez->CONST_TRUE : ez->CONST_FALSE);
if (model_undef) {
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
log_assert(GetSize(undef_y) == 1);
ez->SET(undef_y[0], ez->CONST_FALSE);
}
@ -1386,16 +1386,16 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type == ID($assert))
{
std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
asserts_a[pf].append((*sigmap)(cell->getPort(ID::A)));
asserts_en[pf].append((*sigmap)(cell->getPort(ID::EN)));
asserts_a[pf].append((*sigmap)(cell->getPort(TW::A)));
asserts_en[pf].append((*sigmap)(cell->getPort(TW::EN)));
return true;
}
if (cell->type == ID($assume))
{
std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
assumes_a[pf].append((*sigmap)(cell->getPort(ID::A)));
assumes_en[pf].append((*sigmap)(cell->getPort(ID::EN)));
assumes_a[pf].append((*sigmap)(cell->getPort(TW::A)));
assumes_en[pf].append((*sigmap)(cell->getPort(TW::EN)));
return true;
}

4
kernel/sigtools.h
View File

@ -233,9 +233,9 @@ struct SigSet
template<typename T>
class SigSet<T, typename std::enable_if<!std::is_pointer<T>::value>::type> : public SigSet<T, std::less<T>> {};
template<typename T>
using sort_by_name_id_guard = typename std::enable_if<std::is_same<T,RTLIL::Cell*>::value>::type;
using sort_by_name_guard = typename std::enable_if<std::is_same<T,RTLIL::Cell*>::value>::type;
template<typename T>
class SigSet<T, sort_by_name_id_guard<T>> : public SigSet<T, RTLIL::sort_by_name_id<typename std::remove_pointer<T>::type>> {};
class SigSet<T, sort_by_name_guard<T>> : public SigSet<T, RTLIL::sort_by_name<typename std::remove_pointer<T>::type>> {};
struct SigMapView
{

14
kernel/timinginfo.h
View File

@ -98,11 +98,11 @@ struct TimingInfo
for (auto cell : module->cells()) {
if (cell->type == ID($specify2)) {
auto en = cell->getPort(ID::EN);
auto en = cell->getPort(TW::EN);
if (en.is_fully_const() && !en.as_bool())
continue;
auto src = cell->getPort(ID::SRC);
auto dst = cell->getPort(ID::DST);
auto src = cell->getPort(TW::SRC);
auto dst = cell->getPort(TW::DST);
for (const auto &c : src.chunks())
if (!c.wire || !c.wire->port_input)
log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", module, cell, log_signal(src));
@ -136,8 +136,8 @@ struct TimingInfo
}
}
else if (cell->type == ID($specify3)) {
auto src = cell->getPort(ID::SRC).as_bit();
auto dst = cell->getPort(ID::DST);
auto src = cell->getPort(TW::SRC).as_bit();
auto dst = cell->getPort(TW::DST);
if (!src.wire || !src.wire->port_input)
log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", module, cell, log_signal(src));
for (const auto &c : dst.chunks())
@ -163,8 +163,8 @@ struct TimingInfo
IdString type = cell->getParam(ID::TYPE).decode_string();
if (type != ID($setup) && type != ID($setuphold))
continue;
auto src = cell->getPort(ID::SRC);
auto dst = cell->getPort(ID::DST).as_bit();
auto src = cell->getPort(TW::SRC);
auto dst = cell->getPort(TW::DST).as_bit();
for (const auto &c : src.chunks())
if (!c.wire || !c.wire->port_input)
log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", module, cell, log_signal(src));

126
kernel/twine.h
View File

@ -23,6 +23,9 @@ struct TwinePool;
using TwineRef = size_t;
// Tags TwineChildPool-local refs; never set on refs handed out by TwinePool.
constexpr TwineRef TWINE_LOCAL_BIT = TwineRef(1) << 63;
enum : short {
STATIC_TWINE_BEGIN = 0,
#define X(N) IDX_##N,
@ -195,6 +198,68 @@ struct TwinePool {
return ref;
}
size_t size() const { return backing.size(); }
TwineRef concat(std::span<const TwineRef> ids) {
if (ids.size() == 1)
return ids[0];
return add(Twine{std::vector<TwineRef>(ids.begin(), ids.end())});
}
TwineRef copy_from(const TwinePool& src, TwineRef ref) {
if (ref == Twine::Null || ref < STATIC_TWINE_END)
return ref;
const Twine& t = src[ref];
if (t.is_leaf())
return add(Twine{t.leaf()});
if (t.is_concat()) {
std::vector<TwineRef> children;
children.reserve(t.children().size());
for (TwineRef c : t.children())
children.push_back(copy_from(src, c));
return add(Twine{std::move(children)});
}
if (t.is_suffix())
return add(Twine{Twine::Suffix{copy_from(src, t.suffix().prefix), t.suffix().tail}});
return Twine::Null;
}
// linear deep scan; only for rare by-string lookups
TwineRef lookup(std::string_view sv) const;
// Erases every backing node not reachable from `roots`; refs to
// surviving nodes stay valid. Returns the number of erased nodes.
template<typename Pool>
size_t gc(const Pool& roots) {
std::unordered_set<TwineRef> live;
for (TwineRef ref : roots)
mark_live(ref, live);
size_t erased = 0;
for (auto it = backing.begin(); it != backing.end();) {
TwineRef ref = STATIC_TWINE_END + backing.get_index(it);
if (live.count(ref)) {
++it;
} else {
index.erase(ref);
it = backing.erase(it);
erased++;
}
}
return erased;
}
void mark_live(TwineRef ref, std::unordered_set<TwineRef>& live) const {
if (ref == Twine::Null || ref < STATIC_TWINE_END || !live.insert(ref).second)
return;
const Twine& t = (*this)[ref];
if (t.is_concat()) {
for (TwineRef c : t.children())
mark_live(c, live);
} else if (t.is_suffix()) {
mark_live(t.suffix().prefix, live);
}
}
void dump(std::ostream& os = std::cout) const {
os << "--- TwinePool Dump (" << backing.size() << " nodes) ---\n";
for (auto it = backing.begin(); it != backing.end(); ++it) {
@ -368,6 +433,67 @@ struct DeepTwineEq {
}
};
// Parallel-safe staging while the parent stays read-only; nodes may reference parent refs and earlier local refs
struct TwineChildPool {
const TwinePool* parent;
std::vector<Twine> local_;
std::vector<TwineRef> remap_;
TwineChildPool(const TwinePool* parent) : parent(parent) {}
static bool is_local(TwineRef ref) {
return ref != Twine::Null && (ref & TWINE_LOCAL_BIT);
}
const Twine& operator[] (TwineRef ref) const {
if (is_local(ref))
return local_[ref & ~TWINE_LOCAL_BIT];
return (*parent)[ref];
}
TwineRef add(Twine t) {
local_.push_back(std::move(t));
return (local_.size() - 1) | TWINE_LOCAL_BIT;
}
bool empty() const { return local_.empty(); }
// serial phase only; dest must be *parent; resolve() covers refs added since the previous commit
void commit_into(TwinePool& dest) {
remap_.clear();
remap_.reserve(local_.size());
for (Twine& t : local_) {
if (t.is_concat()) {
for (TwineRef& c : std::get<std::vector<TwineRef>>(t.data))
c = resolve(c);
} else if (t.is_suffix()) {
std::get<Twine::Suffix>(t.data).prefix = resolve(std::get<Twine::Suffix>(t.data).prefix);
}
remap_.push_back(dest.add(std::move(t)));
}
local_.clear();
}
TwineRef resolve(TwineRef ref) const {
if (!is_local(ref))
return ref;
return remap_[ref & ~TWINE_LOCAL_BIT];
}
};
inline TwineRef TwinePool::lookup(std::string_view sv) const {
DeepTwineEq eq{this};
for (TwineRef ref = 0; ref < globals_.size(); ref++)
if (eq(ref, sv))
return ref;
for (auto it = backing.begin(); it != backing.end(); ++it) {
TwineRef ref = STATIC_TWINE_END + backing.get_index(it);
if (eq(ref, sv))
return ref;
}
return Twine::Null;
}
struct TwineSearch {
TwinePool* pool;
std::unordered_set<TwineRef, DeepTwineHash, DeepTwineEq> index;

87
kernel/unstable/patch.cc
View File

@ -10,7 +10,7 @@ using namespace RTLIL;
template class CellAdderMixin<Patch>;
Cell* Patch::addCell(IdString name, IdString type) {
Cell* Patch::addCell(TwineRef name, IdString type) {
cells_.push_back(std::make_unique<Cell>(Cell::ConstructToken{}));
Cell* cell = cells_.back().get();
@ -20,7 +20,11 @@ Cell* Patch::addCell(IdString name, IdString type) {
return cell;
}
Wire* Patch::addWire(IdString name, int width) {
Cell* Patch::addCell(Twine &&name, IdString type) {
return addCell(twine_staging.add(std::move(name)), type);
}
Wire* Patch::addWire(TwineRef name, int width) {
wires_.push_back(std::make_unique<Wire>(Wire::ConstructToken{}));
Wire* wire = wires_.back().get();
@ -30,11 +34,15 @@ Wire* Patch::addWire(IdString name, int width) {
return wire;
}
Wire* Patch::addWire(Twine &&name, int width) {
return addWire(twine_staging.add(std::move(name)), width);
}
// TODO code golf
RTLIL::Wire *RTLIL::Patch::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
RTLIL::Wire *RTLIL::Patch::addWire(TwineRef name, const RTLIL::Wire *other)
{
RTLIL::Wire *wire = addWire(std::move(name));
RTLIL::Wire *wire = addWire(name);
wire->width = other->width;
wire->start_offset = other->start_offset;
wire->port_id = other->port_id;
@ -46,32 +54,44 @@ RTLIL::Wire *RTLIL::Patch::addWire(RTLIL::IdString name, const RTLIL::Wire *othe
return wire;
}
RTLIL::Wire *RTLIL::Patch::addWire(Twine &&name, const RTLIL::Wire *other)
{
return addWire(twine_staging.add(std::move(name)), other);
}
TwineRef Patch::new_name(const std::string *prefix) {
TwineRef pref;
if (auto it = staged_prefix_cache_.find(prefix); it != staged_prefix_cache_.end())
pref = it->second;
else
pref = staged_prefix_cache_[prefix] = twine_staging.add(Twine{*prefix});
return twine_staging.add(Twine{Twine::Suffix{pref, std::to_string(autoidx++)}});
}
Wire* Patch::commit_wire(std::unique_ptr<Wire> wire) {
Wire* raw = wire.release();
IdString name = staged_wire_names_.at(raw);
TwineRef id = twine_staging.resolve(staged_wire_names_.at(raw));
staged_wire_names_.erase(raw);
TwineRef id = mod->design->twines.intern(name.str());
mod->design->obj_set_name_id(raw, id);
mod->design->twines.release(id);
mod->wires_[raw->meta_->name_id] = raw;
raw->meta_->name = id;
mod->wires_[raw->meta_->name] = raw;
raw->module = mod;
return raw;
}
Cell* Patch::commit_cell(std::unique_ptr<Cell> cell) {
Cell* raw = cell.release();
IdString name = staged_cell_names_.at(raw);
TwineRef id = twine_staging.resolve(staged_cell_names_.at(raw));
staged_cell_names_.erase(raw);
TwineRef id = mod->design->twines.intern(name.str());
mod->design->obj_set_name_id(raw, id);
mod->design->twines.release(id);
raw->meta_->name = id;
raw->module = mod;
mod->cells_[raw->meta_->name_id] = raw;
mod->cells_[raw->meta_->name] = raw;
raw->initIndex();
return raw;
}
std::vector<Cell*> Patch::commit_staged() {
twine_staging.commit_into(mod->design->twines);
staged_prefix_cache_.clear();
std::vector<Cell*> committed;
committed.reserve(cells_.size());
for (auto& cell : cells_) {
@ -86,6 +106,12 @@ std::vector<Cell*> Patch::commit_staged() {
}
namespace {
std::string port_name(Cell* cell, TwineRef port) {
if (cell->module && cell->module->design)
return cell->module->design->twines.str(port);
return "<port#" + std::to_string(port) + ">";
}
void apply_src(Module* mod, Cell* root, const std::vector<Cell*>& extras,
const std::vector<Cell*>& targets, Cell* merge_src_into)
{
@ -107,25 +133,24 @@ namespace {
push(merge_src_into);
if (ids.empty())
return;
TwineRef merged = pool.concat(std::span<const TwineRef>{ids});
TwineRef merged = ids.size() == 1 ? ids[0] : pool.add(Twine{std::move(ids)});
if (ys_debug()) {
log_debug("twine: merge yields %s (pool size %zu)\n",
pool.format_ref(merged).c_str(), pool.size());
pool.str(merged).c_str(), pool.backing.size());
if (ys_debug(2))
pool.dump("twine pool state");
pool.dump();
}
for (Cell* c : targets)
c->set_src_id(merged);
if (merge_src_into)
merge_src_into->set_src_id(merged);
pool.release(merged);
}
// Verifies via newcelltypes that root_cell has exactly one output port
// and that it matches `expected_port`.
void assert_single_output(Cell* root_cell, IdString expected_port) {
void assert_single_output(Cell* root_cell, TwineRef expected_port) {
int count = 0;
IdString found;
TwineRef found = Twine::Null;
for (auto &[port, sig] : root_cell->connections()) {
if (root_cell->output(port)) {
found = port;
@ -138,11 +163,11 @@ namespace {
if (found != expected_port)
log_error("Patch: cell %s of type %s sole output port %s does not match patched port %s\n",
log_id(root_cell->name), log_id(root_cell->type),
log_id(found), log_id(expected_port));
port_name(root_cell, found).c_str(), port_name(root_cell, expected_port).c_str());
}
}
void Patch::patch(Cell* root_cell, IdString old_port, SigSpec new_sig,
void Patch::patch(Cell* root_cell, TwineRef old_port, SigSpec new_sig,
const std::vector<Cell*>& extras, Cell* merge_src_into)
{
assert_single_output(root_cell, old_port);
@ -150,11 +175,11 @@ void Patch::patch(Cell* root_cell, IdString old_port, SigSpec new_sig,
SigSpec old_sig = root_cell->getPort(old_port);
if (old_sig.size() != new_sig.size())
log_error("patch size mismatch on cell %s port %s: old %d (%s) vs new %d (%s)\n",
log_id(root_cell->name), log_id(old_port),
log_id(root_cell->name), port_name(root_cell, old_port).c_str(),
old_sig.size(), log_signal(old_sig),
new_sig.size(), log_signal(new_sig));
log_debug("patching %s %s which is %s with %s\n",
log_id(root_cell->name), log_id(old_port),
log_id(root_cell->name), port_name(root_cell, old_port).c_str(),
log_signal(old_sig), log_signal(new_sig));
std::vector<Cell*> committed = commit_staged();
@ -174,22 +199,22 @@ void Patch::patch(Cell* root_cell, IdString old_port, SigSpec new_sig,
}
void Patch::patch_ports(Cell* root_cell,
const std::vector<std::pair<IdString, SigSpec>>& port_replacements,
const std::vector<std::pair<TwineRef, SigSpec>>& port_replacements,
const std::vector<Cell*>& extras, Cell* merge_src_into)
{
// Verify each listed port is an output of root_cell and that the
// replacements cover every output port of root_cell.
pool<IdString> listed;
pool<TwineRef> listed;
std::vector<SigSpec> old_sigs;
old_sigs.reserve(port_replacements.size());
for (auto &[port, new_sig] : port_replacements) {
if (!root_cell->output(port))
log_error("patch_ports: cell %s of type %s port %s is not an output\n",
log_id(root_cell->name), log_id(root_cell->type), log_id(port));
log_id(root_cell->name), log_id(root_cell->type), port_name(root_cell, port).c_str());
SigSpec old_sig = root_cell->getPort(port);
if (old_sig.size() != new_sig.size())
log_error("patch_ports size mismatch on cell %s port %s: old %d (%s) vs new %d (%s)\n",
log_id(root_cell->name), log_id(port),
log_id(root_cell->name), port_name(root_cell, port).c_str(),
old_sig.size(), log_signal(old_sig),
new_sig.size(), log_signal(new_sig));
listed.insert(port);
@ -198,7 +223,7 @@ void Patch::patch_ports(Cell* root_cell,
for (auto &[port, sig] : root_cell->connections())
if (root_cell->output(port) && !listed.count(port))
log_error("patch_ports: cell %s of type %s has output port %s not in port_replacements\n",
log_id(root_cell->name), log_id(root_cell->type), log_id(port));
log_id(root_cell->name), log_id(root_cell->type), port_name(root_cell, port).c_str());
std::vector<Cell*> committed = commit_staged();
apply_src(mod, root_cell, extras, committed, merge_src_into);
@ -207,7 +232,7 @@ void Patch::patch_ports(Cell* root_cell,
// shell before we wire old_sigs to new_sigs. Doing this first ensures
// the old port signals are not briefly double-driven by root_cell and
// the new connection.
std::vector<IdString> all_ports;
std::vector<TwineRef> all_ports;
all_ports.reserve(root_cell->connections().size());
for (auto &[port, sig] : root_cell->connections())
all_ports.push_back(port);
@ -226,6 +251,8 @@ void Patch::patch_ports(Cell* root_cell,
}
void Patch::commit_inheriting_src(Cell* src_source) {
twine_staging.commit_into(mod->design->twines);
staged_prefix_cache_.clear();
for (auto& cell : cells_) {
cell->fixup_parameters();
Cell *committed = commit_cell(std::move(cell));

31
kernel/unstable/patch.h
View File

@ -26,8 +26,10 @@ public:
SigMap* map;
vector<std::unique_ptr<Wire>> wires_ = {};
vector<std::unique_ptr<Cell>> cells_ = {};
dict<RTLIL::Cell*, Twine> staged_cell_names_;
dict<RTLIL::Wire*, Twine> staged_wire_names_;
TwineChildPool twine_staging;
dict<RTLIL::Cell*, TwineRef> staged_cell_names_;
dict<RTLIL::Wire*, TwineRef> staged_wire_names_;
dict<const std::string*, TwineRef> staged_prefix_cache_;
void connect(const RTLIL::SigSig &conn);
void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);
@ -64,16 +66,29 @@ public:
// tracking carries through transparently). Pass nullptr for src_source
// if the staged helpers have no natural ancestor.
void commit_inheriting_src(Cell* src_source);
RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);
RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);
RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);
RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other);
// Primary overloads: name is a design ref or a twine_staging-local ref.
RTLIL::Wire *addWire(TwineRef name, int width = 1);
RTLIL::Wire *addWire(TwineRef name, const RTLIL::Wire *other);
// Convenience: stages name into twine_staging, then dispatches.
RTLIL::Wire *addWire(Twine &&name, int width = 1);
RTLIL::Wire *addWire(Twine &&name, const RTLIL::Wire *other);
RTLIL::Cell* addDffsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
RTLIL::Cell *addCell(TwineRef name, RTLIL::IdString type);
RTLIL::Cell *addCell(TwineRef name, const RTLIL::Cell *other);
RTLIL::Cell *addCell(Twine &&name, RTLIL::IdString type);
RTLIL::Cell *addCell(Twine &&name, const RTLIL::Cell *other);
// NEW_ID analog for twine names; see NEW_TWINE in yosys_common.h.
// Returned refs are twine_staging-local and die at the next commit.
TwineRef new_name(const std::string *prefix);
RTLIL::Cell* addDffsr(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src);
Patch(Module* mod, SigMap* map = nullptr) : mod(mod), map(map) {}
Patch(Module* mod, SigMap* map = nullptr) :
mod(mod), map(map),
twine_staging(mod && mod->design ? &mod->design->twines : nullptr) {}
};
YOSYS_NAMESPACE_END

4
kernel/wallace_tree.h
View File

@ -21,8 +21,8 @@ YOSYS_NAMESPACE_BEGIN
inline std::pair<SigSpec, SigSpec> emit_fa(Module *module, SigSpec a, SigSpec b, SigSpec c, int width)
{
SigSpec sum = module->addWire(NEW_ID, width);
SigSpec cout = module->addWire(NEW_ID, width);
SigSpec sum = module->addWire(NEW_TWINE, width);
SigSpec cout = module->addWire(NEW_TWINE, width);
module->addFa(NEW_ID, a, b, c, cout, sum);

10
kernel/yosys_common.h
View File

@ -304,6 +304,16 @@ RTLIL::IdString new_id_suffix(std::string_view file, int line, std::string_view
}(__FUNCTION__))
#define NEW_ID_SUFFIX(suffix) \
YOSYS_NAMESPACE_PREFIX new_id_suffix(__FILE__, __LINE__, __FUNCTION__, suffix)
#define NEW_TWINE \
YOSYS_NAMESPACE_PREFIX Twine{*[](std::string_view func) -> const std::string * { \
static std::unique_ptr<const std::string> prefix(YOSYS_NAMESPACE_PREFIX create_id_prefix(__FILE__, __LINE__, func)); \
return prefix.get(); \
}(__FUNCTION__) + std::to_string(YOSYS_NAMESPACE_PREFIX autoidx++)}
#define NEW_TWINE_SUFFIX(suffix) \
YOSYS_NAMESPACE_PREFIX Twine{*[](std::string_view func) -> const std::string * { \
static std::unique_ptr<const std::string> prefix(YOSYS_NAMESPACE_PREFIX create_id_prefix(__FILE__, __LINE__, func)); \
return prefix.get(); \
}(__FUNCTION__) + std::string(suffix) + "$" + std::to_string(YOSYS_NAMESPACE_PREFIX autoidx++)}
namespace ID = RTLIL::ID;

8
passes/cmds/abstract.cc
View File

@ -102,7 +102,7 @@ void emit_mux_anyseq(Module* mod, const SigSpec& mux_input, const SigSpec& mux_o
}
bool abstract_state_port(FfData& ff, SigSpec& port_sig, std::set<int> offsets, EnableLogic enable) {
Wire* abstracted = ff.module->addWire(NEW_ID, offsets.size());
Wire* abstracted = ff.module->addWire(NEW_TWINE, offsets.size());
SigSpec mux_input;
int abstracted_idx = 0;
for (int d_idx = 0; d_idx < ff.width; d_idx++) {
@ -213,7 +213,7 @@ unsigned int abstract_state(Module* mod, EnableLogic enable, const std::vector<S
}
bool abstract_value_cell_port(Module* mod, Cell* cell, std::set<int> offsets, IdString port_name, EnableLogic enable) {
Wire* to_abstract = mod->addWire(NEW_ID, offsets.size());
Wire* to_abstract = mod->addWire(NEW_TWINE, offsets.size());
SigSpec mux_input;
SigSpec mux_output;
const SigSpec& old_port = cell->getPort(port_name);
@ -235,7 +235,7 @@ bool abstract_value_cell_port(Module* mod, Cell* cell, std::set<int> offsets, Id
}
bool abstract_value_mod_port(Module* mod, Wire* wire, std::set<int> offsets, EnableLogic enable) {
Wire* to_abstract = mod->addWire(NEW_ID, wire);
Wire* to_abstract = mod->addWire(NEW_TWINE, wire);
to_abstract->port_input = true;
to_abstract->port_id = wire->port_id;
wire->port_input = false;
@ -507,7 +507,7 @@ struct AbstractPass : public Pass {
case Enable::Initstates: {
SigBit in_init_states = mod->Initstate(NEW_ID);
for (int i = 1; i < initstates; i++) {
Wire *in_init_states_q = mod->addWire(NEW_ID);
Wire *in_init_states_q = mod->addWire(NEW_TWINE);
mod->addFf(NEW_ID, in_init_states, in_init_states_q);
in_init_states_q->attributes[ID::init] = State::S1;
in_init_states = in_init_states_q;

8
passes/cmds/add.cc
View File

@ -41,10 +41,10 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const
log_error("Could not find wire with name \"%s\".\n", name);
}
else {
RTLIL::Cell *formal_cell = module->addCell(NEW_ID, "$" + celltype);
formal_cell->setPort(ID::A, wire);
RTLIL::Cell *formal_cell = module->addCell(NEW_TWINE, "$" + celltype);
formal_cell->setPort(TW::A, wire);
if(enable_name == "") {
formal_cell->setPort(ID::EN, State::S1);
formal_cell->setPort(TW::EN, State::S1);
log("Added $%s cell for wire \"%s.%s\"\n", celltype, module->name.str(), name);
}
else {
@ -52,7 +52,7 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const
if(enable_wire == nullptr)
log_error("Could not find enable wire with name \"%s\".\n", enable_name);
formal_cell->setPort(ID::EN, enable_wire);
formal_cell->setPort(TW::EN, enable_wire);
log("Added $%s cell for wire \"%s.%s\" enabled by wire \"%s.%s\".\n", celltype, module->name.str(), name, module->name.str(), enable_name);
}
}

2
passes/cmds/bugpoint.cc
View File

@ -306,7 +306,7 @@ struct BugpointPass : public Pass {
if (!stage2 && (cell->input(it.first) || cell->output(it.first)) && index++ == seed)
{
log_header(design, "Trying to expose cell port %s.%s.%s as module port.\n", mod, cell, it.first.unescape());
RTLIL::Wire *wire = mod->addWire(NEW_ID, port.size());
RTLIL::Wire *wire = mod->addWire(NEW_TWINE, port.size());
wire->set_bool_attribute(ID($bugpoint));
wire->port_input = cell->input(it.first);
wire->port_output = cell->output(it.first);

10
passes/cmds/check.cc
View File

@ -304,8 +304,8 @@ struct CheckPass : public Pass {
if (cell->type.in(ID($pmux), ID($bmux))) {
// We're skipping inputs A and B, since each of their bits contributes only one edge
in_widths = GetSize(cell->getPort(ID::S));
out_widths = GetSize(cell->getPort(ID::Y));
in_widths = GetSize(cell->getPort(TW::S));
out_widths = GetSize(cell->getPort(TW::Y));
} else {
for (auto &conn : cell->connections()) {
if (cell->input(conn.first))
@ -370,8 +370,8 @@ struct CheckPass : public Pass {
if (cell->type == ID($connect)) {
// Inefficient, but rare case in sane design
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
for (int i = 0; i < sig_a.size(); i++) {
int count_a = wire_drivers_count[sig_a[i]];
int count_b = wire_drivers_count[sig_b[i]];
@ -561,7 +561,7 @@ struct CheckPass : public Pass {
if (cell->is_builtin_ff() == 0)
continue;
for (auto bit : sigmap(cell->getPort(ID::Q)))
for (auto bit : sigmap(cell->getPort(TW::Q)))
init_bits.erase(bit);
}

60
passes/cmds/chformal.cc
View File

@ -275,15 +275,15 @@ struct ChformalPass : public Pass {
for (auto cell : module->selected_cells())
{
if (cell->type == ID($ff)) {
SigSpec D = sigmap(cell->getPort(ID::D));
SigSpec Q = sigmap(cell->getPort(ID::Q));
SigSpec D = sigmap(cell->getPort(TW::D));
SigSpec Q = sigmap(cell->getPort(TW::Q));
for (int i = 0; i < GetSize(D); i++)
ffmap[Q[i]] = make_pair(D[i], make_pair(State::Sm, false));
}
if (cell->type == ID($dff)) {
SigSpec D = sigmap(cell->getPort(ID::D));
SigSpec Q = sigmap(cell->getPort(ID::Q));
SigSpec C = sigmap(cell->getPort(ID::CLK));
SigSpec D = sigmap(cell->getPort(TW::D));
SigSpec Q = sigmap(cell->getPort(TW::Q));
SigSpec C = sigmap(cell->getPort(TW::CLK));
bool clockpol = cell->getParam(ID::CLK_POLARITY).as_bool();
for (int i = 0; i < GetSize(D); i++)
ffmap[Q[i]] = make_pair(D[i], make_pair(C, clockpol));
@ -295,7 +295,7 @@ struct ChformalPass : public Pass {
if (is_triggered_check_cell(cell)) {
if (cell->getParam(ID::TRG_WIDTH).as_int() != 1)
continue;
cell->setPort(ID::TRG, SigSpec());
cell->setPort(TW::TRG, SigSpec());
cell->setParam(ID::TRG_ENABLE, false);
cell->setParam(ID::TRG_WIDTH, 0);
cell->setParam(ID::TRG_POLARITY, false);
@ -305,8 +305,8 @@ struct ChformalPass : public Pass {
while (true)
{
SigSpec A = sigmap(cell->getPort(ID::A));
SigSpec EN = sigmap(cell->getPort(ID::EN));
SigSpec A = sigmap(cell->getPort(TW::A));
SigSpec EN = sigmap(cell->getPort(TW::EN));
if (ffmap.count(A) == 0 || ffmap.count(EN) == 0)
break;
@ -322,8 +322,8 @@ struct ChformalPass : public Pass {
if (A_map.second != EN_map.second)
break;
cell->setPort(ID::A, A_map.first);
cell->setPort(ID::EN, EN_map.first);
cell->setPort(TW::A, A_map.first);
cell->setPort(TW::EN, EN_map.first);
}
}
}
@ -337,18 +337,18 @@ struct ChformalPass : public Pass {
for (int i = 0; i < mode_arg; i++)
{
SigSpec orig_a = cell->getPort(ID::A);
SigSpec orig_en = cell->getPort(ID::EN);
SigSpec orig_a = cell->getPort(TW::A);
SigSpec orig_en = cell->getPort(TW::EN);
Wire *new_a = module->addWire(NEW_ID);
Wire *new_en = module->addWire(NEW_ID);
Wire *new_a = module->addWire(NEW_TWINE);
Wire *new_en = module->addWire(NEW_TWINE);
new_en->attributes[ID::init] = State::S0;
module->addFf(NEW_ID, orig_a, new_a);
module->addFf(NEW_ID, orig_en, new_en);
cell->setPort(ID::A, new_a);
cell->setPort(ID::EN, new_en);
cell->setPort(TW::A, new_a);
cell->setPort(TW::EN, new_en);
}
}
}
@ -358,14 +358,14 @@ struct ChformalPass : public Pass {
SigSpec en = State::S1;
for (int i = 0; i < mode_arg; i++) {
Wire *w = module->addWire(NEW_ID);
Wire *w = module->addWire(NEW_TWINE);
w->attributes[ID::init] = State::S0;
module->addFf(NEW_ID, en, w);
en = w;
}
for (auto cell : constr_cells)
cell->setPort(ID::EN, module->LogicAnd(NEW_ID, en, cell->getPort(ID::EN)));
cell->setPort(TW::EN, module->LogicAnd(NEW_ID, en, cell->getPort(TW::EN)));
}
else
if (mode =='p')
@ -373,7 +373,7 @@ struct ChformalPass : public Pass {
for (auto cell : constr_cells)
{
if (cell->type == ID($check)) {
Cell *cover = module->addCell(NEW_ID_SUFFIX("coverenable"), ID($check));
Cell *cover = module->addCell(NEW_TWINE_SUFFIX("coverenable"), ID($check));
cover->attributes = cell->attributes;
if (cell->src_id() != Twine::Null && module->design)
cover->set_src_id(cell->src_id());
@ -383,11 +383,11 @@ struct ChformalPass : public Pass {
for (auto const &conn : cell->connections())
if (!conn.first.in(ID::A, ID::EN))
cover->setPort(conn.first, conn.second);
cover->setPort(ID::A, cell->getPort(ID::EN));
cover->setPort(ID::EN, State::S1);
cover->setPort(TW::A, cell->getPort(TW::EN));
cover->setPort(TW::EN, State::S1);
} else {
module->addCover(NEW_ID_SUFFIX("coverenable"),
cell->getPort(ID::EN), State::S1, cell->get_src_attribute());
cell->getPort(TW::EN), State::S1, cell->get_src_attribute());
}
}
}
@ -419,17 +419,17 @@ struct ChformalPass : public Pass {
log_error("Cannot lower edge triggered $check cell %s, run async2sync or clk2fflogic first.\n", cell);
Cell *plain_cell = module->addCell(NEW_ID, formal_flavor(cell));
Cell *plain_cell = module->addCell(NEW_TWINE, formal_flavor(cell));
plain_cell->attributes = cell->attributes;
if (cell->src_id() != Twine::Null && module->design)
plain_cell->set_src_id(cell->src_id());
SigBit sig_a = cell->getPort(ID::A);
SigBit sig_en = cell->getPort(ID::EN);
SigBit sig_a = cell->getPort(TW::A);
SigBit sig_en = cell->getPort(TW::EN);
plain_cell->setPort(ID::A, sig_a);
plain_cell->setPort(ID::EN, sig_en);
plain_cell->setPort(TW::A, sig_a);
plain_cell->setPort(TW::EN, sig_en);
if (plain_cell->type.in(ID($assert), ID($assume)))
sig_a = module->Not(NEW_ID, sig_a);
@ -438,12 +438,12 @@ struct ChformalPass : public Pass {
module->swap_names(cell, plain_cell);
if (cell->getPort(ID::ARGS).empty()) {
if (cell->getPort(TW::ARGS).empty()) {
module->remove(cell);
} else {
cell->type = ID($print);
cell->setPort(ID::EN, combined_en);
cell->unsetPort(ID::A);
cell->setPort(TW::EN, combined_en);
cell->unsetPort(TW::A);
cell->unsetParam(ID(FLAVOR));
}
}

16
passes/cmds/clean_zerowidth.cc
View File

@ -77,7 +77,7 @@ struct CleanZeroWidthPass : public Pass {
// Coarse FF cells: remove if WIDTH == 0 (no outputs).
// This will also trigger on fine cells, so use the Q port
// width instead of actual WIDTH parameter.
if (GetSize(cell->getPort(ID::Q)) == 0) {
if (GetSize(cell->getPort(TW::Q)) == 0) {
module->remove(cell);
}
} else if (cell->type.in(ID($pmux), ID($bmux), ID($demux))) {
@ -87,17 +87,17 @@ struct CleanZeroWidthPass : public Pass {
module->remove(cell);
}
if (cell->getParam(ID::S_WIDTH).as_int() == 0) {
module->connect(cell->getPort(ID::Y), cell->getPort(ID::A));
module->connect(cell->getPort(TW::Y), cell->getPort(TW::A));
module->remove(cell);
}
} else if (cell->type == ID($concat)) {
// If a concat has a zero-width input: replace with direct
// connection to the other input.
if (cell->getParam(ID::A_WIDTH).as_int() == 0) {
module->connect(cell->getPort(ID::Y), cell->getPort(ID::B));
module->connect(cell->getPort(TW::Y), cell->getPort(TW::B));
module->remove(cell);
} else if (cell->getParam(ID::B_WIDTH).as_int() == 0) {
module->connect(cell->getPort(ID::Y), cell->getPort(ID::A));
module->connect(cell->getPort(TW::Y), cell->getPort(TW::A));
module->remove(cell);
}
} else if (cell->type == ID($fsm)) {
@ -107,7 +107,7 @@ struct CleanZeroWidthPass : public Pass {
} else if (cell->type == ID($lut)) {
// Zero-width LUT is just a const driver.
if (cell->getParam(ID::WIDTH).as_int() == 0) {
module->connect(cell->getPort(ID::Y), cell->getParam(ID::LUT)[0]);
module->connect(cell->getPort(TW::Y), cell->getParam(ID::LUT)[0]);
module->remove(cell);
}
} else if (cell->type == ID($sop)) {
@ -115,7 +115,7 @@ struct CleanZeroWidthPass : public Pass {
if (cell->getParam(ID::WIDTH).as_int() == 0) {
// The value is 1 iff DEPTH is non-0.
bool val = cell->getParam(ID::DEPTH).as_int() != 0;
module->connect(cell->getPort(ID::Y), val);
module->connect(cell->getPort(TW::Y), val);
module->remove(cell);
}
} else if (cell->hasParam(ID::WIDTH)) {
@ -132,11 +132,11 @@ struct CleanZeroWidthPass : public Pass {
// TODO: fixing zero-width A and B not supported.
} else {
if (cell->getParam(ID::A_WIDTH).as_int() == 0) {
cell->setPort(ID::A, State::S0);
cell->setPort(TW::A, State::S0);
cell->setParam(ID::A_WIDTH, 1);
}
if (cell->hasParam(ID::B_WIDTH) && cell->getParam(ID::B_WIDTH).as_int() == 0) {
cell->setPort(ID::B, State::S0);
cell->setPort(TW::B, State::S0);
cell->setParam(ID::B_WIDTH, 1);
}
}

2
passes/cmds/connect.cc
View File

@ -30,7 +30,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &
{
CellTypes ct(design);
RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size());
RTLIL::Wire *dummy_wire = module->addWire(NEW_TWINE, sig.size());
// (void)module->connections(); // trigger signorm flush

94
passes/cmds/dft_tag.cc
View File

@ -98,10 +98,10 @@ struct DftTagWorker {
}
for (auto cell : overwrite_cells) {
log_debug("Applying $overwrite_tag %s for signal %s\n", cell->name.unescape(), log_signal(cell->getPort(ID::A)));
SigSpec orig_signal = cell->getPort(ID::A);
log_debug("Applying $overwrite_tag %s for signal %s\n", cell->name.unescape(), log_signal(cell->getPort(TW::A)));
SigSpec orig_signal = cell->getPort(TW::A);
SigSpec interposed_signal = divert_users(orig_signal);
auto *set_tag_cell = module->addSetTag(NEW_ID, cell->getParam(ID::TAG).decode_string(), orig_signal, cell->getPort(ID::SET), cell->getPort(ID::CLR), interposed_signal);
auto *set_tag_cell = module->addSetTag(NEW_ID, cell->getParam(ID::TAG).decode_string(), orig_signal, cell->getPort(TW::SET), cell->getPort(TW::CLR), interposed_signal);
modwalker.add_cell(set_tag_cell); // Make sure the next $overwrite_tag sees the new connections
design_changed = true;
}
@ -123,7 +123,7 @@ struct DftTagWorker {
signal_mapped.sort_and_unify();
if (GetSize(signal_mapped) < GetSize(signal))
log_warning("Detected $overwrite_tag on signal %s which contains repeated bits, this can result in unexpected behavior.\n", log_signal(signal));
SigSpec new_wire = module->addWire(NEW_ID, GetSize(signal));
SigSpec new_wire = module->addWire(NEW_TWINE, GetSize(signal));
for (int i = 0; i < GetSize(new_wire); ++i)
divert_users(signal[i], new_wire[i]);
return new_wire;
@ -359,7 +359,7 @@ struct DftTagWorker {
// when the outer call for this tag/cell returns
for (auto &conn : cell->connections())
if (cell->output(conn.first))
emit_tag_signal(tag, conn.second, module->addWire(NEW_ID, GetSize(conn.second)));
emit_tag_signal(tag, conn.second, module->addWire(NEW_TWINE, GetSize(conn.second)));
return;
}
@ -380,8 +380,8 @@ struct DftTagWorker {
group_of_tag[tag] = tag_group;
}
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
// TODO handle constant set/clr masks
add_tags(sig_y, singleton(tag));
forward_tags(sig_y, sig_a);
@ -393,8 +393,8 @@ struct DftTagWorker {
}
if (cell->type.in(ID($not), ID($pos))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
if (cell->type.in(ID($not), ID($or))) {
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
}
@ -403,9 +403,9 @@ struct DftTagWorker {
}
if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($bweqx))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
@ -416,10 +416,10 @@ struct DftTagWorker {
}
if (cell->type.in(ID($mux), ID($bwmux))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_b = cell->getPort(ID::B);
auto sig_s = cell->getPort(ID::S);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_b = cell->getPort(TW::B);
auto sig_s = cell->getPort(TW::S);
if (cell->type == ID($mux))
sig_s = SigSpec(sig_s[0], GetSize(sig_y));
@ -445,7 +445,7 @@ struct DftTagWorker {
ID($reduce_bool), ID($logic_not), ID($logic_or), ID($logic_and),
ID($eq), ID($ne)
)) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_y = cell->getPort(TW::Y);
add_tags(sig_y[0], tags(cell));
return;
@ -480,12 +480,12 @@ struct DftTagWorker {
if (cell->type == ID($set_tag)) {
IdString cell_tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string());
auto tag_sig_a = tag_signal(tag, cell->getPort(ID::A));
auto &sig_y = cell->getPort(ID::Y);
auto tag_sig_a = tag_signal(tag, cell->getPort(TW::A));
auto &sig_y = cell->getPort(TW::Y);
if (cell_tag == tag) {
auto &sig_set = cell->getPort(ID::SET);
auto &sig_clr = cell->getPort(ID::CLR);
auto &sig_set = cell->getPort(TW::SET);
auto &sig_clr = cell->getPort(TW::CLR);
tag_sig_a = autoAnd(NEW_ID, tag_sig_a, autoNot(NEW_ID, sig_clr));
tag_sig_a = autoOr(NEW_ID, tag_sig_a, sig_set);
}
@ -499,8 +499,8 @@ struct DftTagWorker {
}
if (cell->type.in(ID($not), ID($pos), ID($_NOT_), ID($_BUF_))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
if (cell->type.in(ID($not), ID($or))) {
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
}
@ -512,9 +512,9 @@ struct DftTagWorker {
ID($and), ID($or),
ID($_AND_), ID($_OR_), ID($_NAND_), ID($_NOR_), ID($_ANDNOT_), ID($_ORNOT_)
)) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
if (cell->type.in(ID($and), ID($or))) {
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
@ -555,9 +555,9 @@ struct DftTagWorker {
}
if (cell->type.in(ID($xor), ID($xnor), ID($bweqx), ID($_XOR_), ID($_XNOR_))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
if (cell->type.in(ID($xor), ID($xnor))) {
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
@ -573,10 +573,10 @@ struct DftTagWorker {
if (cell->type.in(ID($_MUX_), ID($mux), ID($bwmux))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_b = cell->getPort(ID::B);
auto sig_s = cell->getPort(ID::S);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_b = cell->getPort(TW::B);
auto sig_s = cell->getPort(TW::S);
if (cell->type == ID($mux))
sig_s = SigSpec(sig_s[0], GetSize(sig_y));
@ -607,9 +607,9 @@ struct DftTagWorker {
}
if (cell->type.in(ID($eq), ID($ne), ID($eqx), ID($nex))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
int width = std::max(GetSize(sig_a), GetSize(sig_b));
sig_a.extend_u0(width, cell->getParam(ID::A_SIGNED).as_bool());
sig_b.extend_u0(width, cell->getParam(ID::B_SIGNED).as_bool());
@ -636,9 +636,9 @@ struct DftTagWorker {
if (cell->type.in(ID($lt), ID($gt), ID($le), ID($ge))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
int width = std::max(GetSize(sig_a), GetSize(sig_b));
sig_a.extend_u0(width, cell->getParam(ID::A_SIGNED).as_bool());
sig_b.extend_u0(width, cell->getParam(ID::B_SIGNED).as_bool());
@ -667,8 +667,8 @@ struct DftTagWorker {
}
if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($logic_not))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto group_sig_a = tag_group_signal(tag, sig_a);
auto tag_sig_a = tag_signal(tag, sig_a);
@ -701,7 +701,7 @@ struct DftTagWorker {
ff.name = NEW_ID;
ff.cell = nullptr;
ff.sig_d = tag_signal(tag, ff.sig_d);
ff.sig_q = module->addWire(NEW_ID, width);
ff.sig_q = module->addWire(NEW_TWINE, width);
ff.is_anyinit = false;
ff.val_init = Const(0, width);
ff.emit();
@ -751,7 +751,7 @@ struct DftTagWorker {
get_tag_cells.push_back(cell);
for (auto cell : get_tag_cells) {
auto &sig_a = cell->getPort(ID::A);
auto &sig_a = cell->getPort(TW::A);
IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string());
tag_signal(tag, sig_a);
@ -808,15 +808,15 @@ struct DftTagWorker {
}
for (auto cell : set_tag_cells) {
auto &sig_a = cell->getPort(ID::A);
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_y = cell->getPort(TW::Y);
module->connect(sig_y, sig_a);
module->remove(cell);
}
for (auto cell : get_tag_cells) {
auto &sig_a = cell->getPort(ID::A);
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_y = cell->getPort(TW::Y);
IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string());
auto tag_sig = tag_signal(tag, sig_a);

2
passes/cmds/future.cc
View File

@ -53,7 +53,7 @@ struct FutureWorker {
if (cell->type != ID($future_ff))
continue;
module->connect(cell->getPort(ID::Y), future_ff(cell->getPort(ID::A)));
module->connect(cell->getPort(TW::Y), future_ff(cell->getPort(TW::A)));
replaced_cells.push_back(cell);
}

8
passes/cmds/glift.cc
View File

@ -189,7 +189,7 @@ private:
if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_))) {
const unsigned int A = 0, B = 1, Y = 2;
const unsigned int NUM_PORTS = 3;
RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(ID::A), cell->getPort(ID::B), cell->getPort(ID::Y)};
RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(TW::A), cell->getPort(TW::B), cell->getPort(TW::Y)};
RTLIL::SigSpec port_taints[NUM_PORTS];
if (ports[A].size() != 1 || ports[B].size() != 1 || ports[Y].size() != 1)
@ -254,7 +254,7 @@ private:
else if (cell->type.in(ID($_XOR_), ID($_XNOR_))) {
const unsigned int A = 0, B = 1, Y = 2;
const unsigned int NUM_PORTS = 3;
RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(ID::A), cell->getPort(ID::B), cell->getPort(ID::Y)};
RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(TW::A), cell->getPort(TW::B), cell->getPort(TW::Y)};
RTLIL::SigSpec port_taints[NUM_PORTS];
if (ports[A].size() != 1 || ports[B].size() != 1 || ports[Y].size() != 1)
@ -310,7 +310,7 @@ private:
else if (cell->type.in(ID($_MUX_), ID($_NMUX_))) {
const unsigned int A = 0, B = 1, S = 2, Y = 3;
const unsigned int NUM_PORTS = 4;
RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(ID::A), cell->getPort(ID::B), cell->getPort(ID::S), cell->getPort(ID::Y)};
RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(TW::A), cell->getPort(TW::B), cell->getPort(TW::S), cell->getPort(TW::Y)};
RTLIL::SigSpec port_taints[NUM_PORTS];
if (ports[A].size() != 1 || ports[B].size() != 1 || ports[S].size() != 1 || ports[Y].size() != 1)
@ -323,7 +323,7 @@ private:
else if (cell->type.in(ID($_NOT_))) {
const unsigned int A = 0, Y = 1;
const unsigned int NUM_PORTS = 2;
RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(ID::A), cell->getPort(ID::Y)};
RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(TW::A), cell->getPort(TW::Y)};
RTLIL::SigSpec port_taints[NUM_PORTS];
if (ports[A].size() != 1 || ports[Y].size() != 1)

10
passes/cmds/portarcs.cc
View File

@ -32,7 +32,7 @@ static RTLIL::SigBit canonical_bit(RTLIL::SigBit bit)
RTLIL::Wire *w;
while ((w = bit.wire) != NULL && !w->port_input &&
w->driverCell()->type.in(ID($buf), ID($_BUF_))) {
bit = w->driverCell()->getPort(ID::A)[bit.offset];
bit = w->driverCell()->getPort(TW::A)[bit.offset];
}
return bit;
}
@ -292,7 +292,7 @@ struct PortarcsPass : Pass {
int *p = annotations.at(canonical_bit(bit));
for (auto i = 0; i < inputs.size(); i++) {
if (p[i] >= 0) {
Cell *spec = m->addCell(NEW_ID, ID($specify2));
Cell *spec = m->addCell(NEW_TWINE, ID($specify2));
spec->setParam(ID::SRC_WIDTH, 1);
spec->setParam(ID::DST_WIDTH, 1);
spec->setParam(ID::T_FALL_MAX, p[i]);
@ -304,9 +304,9 @@ struct PortarcsPass : Pass {
spec->setParam(ID::SRC_DST_POL, false);
spec->setParam(ID::SRC_DST_PEN, false);
spec->setParam(ID::FULL, false);
spec->setPort(ID::EN, Const(1, 1));
spec->setPort(ID::SRC, inputs[i]);
spec->setPort(ID::DST, bit);
spec->setPort(TW::EN, Const(1, 1));
spec->setPort(TW::SRC, inputs[i]);
spec->setPort(TW::DST, bit);
}
}
}

2
passes/cmds/scatter.cc
View File

@ -51,7 +51,7 @@ struct ScatterPass : public Pass {
for (auto cell : module->cells()) {
dict<RTLIL::IdString, RTLIL::SigSig> new_connections;
for (auto conn : cell->connections())
new_connections.emplace(conn.first, RTLIL::SigSig(conn.second, module->addWire(NEW_ID, GetSize(conn.second))));
new_connections.emplace(conn.first, RTLIL::SigSig(conn.second, module->addWire(NEW_TWINE, GetSize(conn.second))));
for (auto &it : new_connections) {
if (ct.cell_output(cell->type, it.first))
module->connect(RTLIL::SigSig(it.second.first, it.second.second));

4
passes/cmds/scc.cc
View File

@ -152,14 +152,14 @@ struct SccWorker
if (subcell->type != ID($specify2))
continue;
for (auto bit : subcell->getPort(ID::SRC))
for (auto bit : subcell->getPort(TW::SRC))
{
if (!bit.wire || !cell->hasPort(bit.wire->name))
continue;
inputSignals.append(sigmap(cell->getPort(bit.wire->name)));
}
for (auto bit : subcell->getPort(ID::DST))
for (auto bit : subcell->getPort(TW::DST))
{
if (!bit.wire || !cell->hasPort(bit.wire->name))
continue;

4
passes/cmds/setundef.cc
View File

@ -371,13 +371,13 @@ struct SetundefPass : public Pass {
bool cell_selected = design->selected(module, cell);
bool wire_selected = false;
for (auto bit : sigmap(cell->getPort(ID::Q)))
for (auto bit : sigmap(cell->getPort(TW::Q)))
if (bit.wire && design->selected(module, bit.wire))
wire_selected = true;
if (!cell_selected && !wire_selected)
continue;
for (auto bit : sigmap(cell->getPort(ID::Q)))
for (auto bit : sigmap(cell->getPort(TW::Q)))
ffbits.insert(bit);
}

18
passes/cmds/splice.cc
View File

@ -75,13 +75,13 @@ struct SpliceWorker
RTLIL::SigSpec new_sig = sig;
if (sig_a.size() != sig.size()) {
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($slice));
RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($slice));
cell->parameters[ID::OFFSET] = offset;
cell->parameters[ID::A_WIDTH] = sig_a.size();
cell->parameters[ID::Y_WIDTH] = sig.size();
cell->setPort(ID::A, sig_a);
cell->setPort(ID::Y, module->addWire(NEW_ID, sig.size()));
new_sig = cell->getPort(ID::Y);
cell->setPort(TW::A, sig_a);
cell->setPort(TW::Y, module->addWire(NEW_TWINE, sig.size()));
new_sig = cell->getPort(TW::Y);
}
sliced_signals_cache[sig] = new_sig;
@ -132,13 +132,13 @@ struct SpliceWorker
RTLIL::SigSpec new_sig = get_sliced_signal(chunks.front());
for (size_t i = 1; i < chunks.size(); i++) {
RTLIL::SigSpec sig2 = get_sliced_signal(chunks[i]);
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($concat));
RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($concat));
cell->parameters[ID::A_WIDTH] = new_sig.size();
cell->parameters[ID::B_WIDTH] = sig2.size();
cell->setPort(ID::A, new_sig);
cell->setPort(ID::B, sig2);
cell->setPort(ID::Y, module->addWire(NEW_ID, new_sig.size() + sig2.size()));
new_sig = cell->getPort(ID::Y);
cell->setPort(TW::A, new_sig);
cell->setPort(TW::B, sig2);
cell->setPort(TW::Y, module->addWire(NEW_TWINE, new_sig.size() + sig2.size()));
new_sig = cell->getPort(TW::Y);
}
spliced_signals_cache[sig] = new_sig;

30
passes/cmds/splitcells.cc
View File

@ -70,16 +70,16 @@ struct SplitcellsWorker
{
if (cell->type.in("$and", "$mux", "$not", "$or", "$pmux", "$xnor", "$xor"))
{
SigSpec outsig = sigmap(cell->getPort(ID::Y));
SigSpec outsig = sigmap(cell->getPort(TW::Y));
if (GetSize(outsig) <= 1) return 0;
std::vector<int> slices;
slices.push_back(0);
int width = GetSize(outsig);
width = std::min(width, GetSize(cell->getPort(ID::A)));
width = std::min(width, GetSize(cell->getPort(TW::A)));
if (cell->hasPort(ID::B))
width = std::min(width, GetSize(cell->getPort(ID::B)));
width = std::min(width, GetSize(cell->getPort(TW::B)));
for (int i = 1; i < width; i++) {
auto &last_users = bit_users_db[outsig[slices.back()]];
@ -110,23 +110,23 @@ struct SplitcellsWorker
return new_sig;
};
slice->setPort(ID::A, slice_signal(slice->getPort(ID::A)));
slice->setPort(TW::A, slice_signal(slice->getPort(TW::A)));
if (slice->hasParam(ID::A_WIDTH))
slice->setParam(ID::A_WIDTH, GetSize(slice->getPort(ID::A)));
slice->setParam(ID::A_WIDTH, GetSize(slice->getPort(TW::A)));
if (slice->hasPort(ID::B)) {
slice->setPort(ID::B, slice_signal(slice->getPort(ID::B)));
slice->setPort(TW::B, slice_signal(slice->getPort(TW::B)));
if (slice->hasParam(ID::B_WIDTH))
slice->setParam(ID::B_WIDTH, GetSize(slice->getPort(ID::B)));
slice->setParam(ID::B_WIDTH, GetSize(slice->getPort(TW::B)));
}
slice->setPort(ID::Y, slice_signal(slice->getPort(ID::Y)));
slice->setPort(TW::Y, slice_signal(slice->getPort(TW::Y)));
if (slice->hasParam(ID::Y_WIDTH))
slice->setParam(ID::Y_WIDTH, GetSize(slice->getPort(ID::Y)));
slice->setParam(ID::Y_WIDTH, GetSize(slice->getPort(TW::Y)));
if (slice->hasParam(ID::WIDTH))
slice->setParam(ID::WIDTH, GetSize(slice->getPort(ID::Y)));
slice->setParam(ID::WIDTH, GetSize(slice->getPort(TW::Y)));
log(" slice %d: %s => %s\n", i, slice_name, log_signal(slice->getPort(ID::Y)));
log(" slice %d: %s => %s\n", i, slice_name, log_signal(slice->getPort(TW::Y)));
}
module->remove(cell);
@ -139,7 +139,7 @@ struct SplitcellsWorker
auto splitports = {ID::D, ID::Q, ID::AD, ID::SET, ID::CLR};
auto splitparams = {ID::ARST_VALUE, ID::SRST_VALUE};
SigSpec outsig = sigmap(cell->getPort(ID::Q));
SigSpec outsig = sigmap(cell->getPort(TW::Q));
if (GetSize(outsig) <= 1) return 0;
int width = GetSize(outsig);
@ -167,7 +167,7 @@ struct SplitcellsWorker
Cell *slice = module->addCell(slice_name, cell);
for (IdString portname : splitports) {
for (TwineRef portname : splitports) {
if (slice->hasPort(portname)) {
SigSpec sig = slice->getPort(portname);
sig = sig.extract(slice_lsb, slice_msb-slice_lsb+1);
@ -183,9 +183,9 @@ struct SplitcellsWorker
}
}
slice->setParam(ID::WIDTH, GetSize(slice->getPort(ID::Q)));
slice->setParam(ID::WIDTH, GetSize(slice->getPort(TW::Q)));
log(" slice %d: %s => %s\n", i, slice_name.unescape(), log_signal(slice->getPort(ID::Q)));
log(" slice %d: %s => %s\n", i, slice_name.unescape(), log_signal(slice->getPort(TW::Q)));
}
module->remove(cell);

24
passes/cmds/stat.cc
View File

@ -190,22 +190,22 @@ struct statdata_t {
ID($xor), ID($xnor), ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx), ID($lt),
ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt), ID($add), ID($sub), ID($mul),
ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow), ID($alu))) {
int width_a = cell->hasPort(ID::A) ? GetSize(cell->getPort(ID::A)) : 0;
int width_b = cell->hasPort(ID::B) ? GetSize(cell->getPort(ID::B)) : 0;
int width_y = cell->hasPort(ID::Y) ? GetSize(cell->getPort(ID::Y)) : 0;
int width_a = cell->hasPort(ID::A) ? GetSize(cell->getPort(TW::A)) : 0;
int width_b = cell->hasPort(ID::B) ? GetSize(cell->getPort(TW::B)) : 0;
int width_y = cell->hasPort(ID::Y) ? GetSize(cell->getPort(TW::Y)) : 0;
cell_type = stringf("%s_%d", cell_type, max<int>({width_a, width_b, width_y}));
} else if (cell_type.in(ID($mux)))
cell_type = stringf("%s_%d", cell_type, GetSize(cell->getPort(ID::Y)));
cell_type = stringf("%s_%d", cell_type, GetSize(cell->getPort(TW::Y)));
else if (cell_type.in(ID($bmux), ID($pmux)))
cell_type =
stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(ID::Y)), GetSize(cell->getPort(ID::S)));
stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(TW::Y)), GetSize(cell->getPort(TW::S)));
else if (cell_type == ID($demux))
cell_type =
stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::S)));
stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::S)));
else if (cell_type.in(ID($sr), ID($ff), ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe),
ID($sdff), ID($sdffe), ID($sdffce), ID($aldff), ID($aldffe), ID($dlatch), ID($adlatch),
ID($dlatchsr)))
cell_type = stringf("%s_%d", cell_type, GetSize(cell->getPort(ID::Q)));
cell_type = stringf("%s_%d", cell_type, GetSize(cell->getPort(TW::Q)));
}
if (!cell_area.empty()) {
@ -215,10 +215,10 @@ struct statdata_t {
if (cell_data.single_parameter_area.size() > 0) {
// assume that we just take the max of the A,B,Y ports
int width_a = cell->hasPort(ID::A) ? GetSize(cell->getPort(ID::A)) : 0;
int width_b = cell->hasPort(ID::B) ? GetSize(cell->getPort(ID::B)) : 0;
int width_y = cell->hasPort(ID::Y) ? GetSize(cell->getPort(ID::Y)) : 0;
int width_q = cell->hasPort(ID::Q) ? GetSize(cell->getPort(ID::Q)) : 0;
int width_a = cell->hasPort(ID::A) ? GetSize(cell->getPort(TW::A)) : 0;
int width_b = cell->hasPort(ID::B) ? GetSize(cell->getPort(TW::B)) : 0;
int width_y = cell->hasPort(ID::Y) ? GetSize(cell->getPort(TW::Y)) : 0;
int width_q = cell->hasPort(ID::Q) ? GetSize(cell->getPort(TW::Q)) : 0;
int max_width = max<int>({width_a, width_b, width_y, width_q});
if (!cell_area.count(cell_type)) {
cell_area[cell_type] = cell_data;
@ -237,7 +237,7 @@ struct statdata_t {
vector<double> widths;
if (cell_data.parameter_names.size() > 0) {
for (auto &it : cell_data.parameter_names) {
RTLIL::IdString port_name;
TwineRef port_name;
if (it == "A") {
port_name = ID::A;
} else if (it == "B") {

18
passes/cmds/test_patch.cc
View File

@ -19,18 +19,18 @@ struct TestPatchPass : public Pass {
for (auto cell : module->selected_cells()) {
if (cell->type == ID($add)) {
Cell* add = cell;
log_assert(add->getPort(ID::B).is_wire());
log_assert(add->getPort(ID::B).known_driver());
auto neg = add->getPort(ID::B)[0].wire->driverCell();
log_assert(add->getPort(TW::B).is_wire());
log_assert(add->getPort(TW::B).known_driver());
auto neg = add->getPort(TW::B)[0].wire->driverCell();
log_assert(neg->type == ID($not));
RTLIL::Patch patcher(module, nullptr);
int width = cell->getPort(ID::A).size();
int width = cell->getPort(TW::A).size();
auto sub = patcher.addSub(NEW_ID,
neg->getPort(ID::A),
add->getPort(ID::A),
patcher.addWire(NEW_ID, width));
auto new_out_wire = patcher.addWire(NEW_ID, width);
auto new_cell = patcher.addNeg(NEW_ID, sub->getPort(ID::Y), new_out_wire);
neg->getPort(TW::A),
add->getPort(TW::A),
patcher.addWire(NEW_TWINE, width));
auto new_out_wire = patcher.addWire(NEW_TWINE, width);
auto new_cell = patcher.addNeg(NEW_ID, sub->getPort(TW::Y), new_out_wire);
log_cell(new_cell);
patcher.patch(add, ID::Y, new_out_wire);
}

2
passes/cmds/trace.cc
View File

@ -36,7 +36,7 @@ struct TraceMonitor : public RTLIL::Monitor
log("#TRACE# Module delete: %s\n", module);
}
void notify_connect(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override
void notify_connect(RTLIL::Cell *cell, TwineRef port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override
{
log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", cell->module, cell, port.unescape(), log_signal(sig), log_signal(old_sig));
}

180
passes/cmds/xprop.cc
View File

@ -202,9 +202,9 @@ struct XpropWorker
EncodedSig new_sigs;
if (new_bits > 0) {
new_sigs.is_0 = module->addWire(NEW_ID, new_bits);
new_sigs.is_1 = module->addWire(NEW_ID, new_bits);
new_sigs.is_x = module->addWire(NEW_ID, new_bits);
new_sigs.is_0 = module->addWire(NEW_TWINE, new_bits);
new_sigs.is_1 = module->addWire(NEW_TWINE, new_bits);
new_sigs.is_x = module->addWire(NEW_TWINE, new_bits);
}
int invert_pos = 0;
@ -319,8 +319,8 @@ struct XpropWorker
}
if (cell->type == ID($not)) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A); sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A); sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
for (int i = 0; i < GetSize(sig_y); i++)
if (maybe_x(sig_a[i]))
mark_maybe_x(sig_y[i]);
@ -328,9 +328,9 @@ struct XpropWorker
}
if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A); sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
auto sig_b = cell->getPort(ID::B); sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A); sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
auto sig_b = cell->getPort(TW::B); sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
for (int i = 0; i < GetSize(sig_y); i++)
if (maybe_x(sig_a[i]) || maybe_x(sig_b[i]))
mark_maybe_x(sig_y[i]);
@ -338,10 +338,10 @@ struct XpropWorker
}
if (cell->type.in(ID($bwmux))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_b = cell->getPort(ID::B);
auto &sig_s = cell->getPort(ID::S);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_b = cell->getPort(TW::B);
auto &sig_s = cell->getPort(TW::S);
for (int i = 0; i < GetSize(sig_y); i++)
if (maybe_x(sig_a[i]) || maybe_x(sig_b[i]) || maybe_x(sig_s[i]))
mark_maybe_x(sig_y[i]);
@ -349,10 +349,10 @@ struct XpropWorker
}
if (cell->type.in(ID($_MUX_), ID($mux), ID($bmux))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_b = cell->getPort(ID::B);
auto &sig_s = cell->getPort(ID::S);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_b = cell->getPort(TW::B);
auto &sig_s = cell->getPort(TW::S);
if (maybe_x(sig_s)) {
mark_maybe_x(sig_y);
return;
@ -373,9 +373,9 @@ struct XpropWorker
}
if (cell->type.in(ID($demux))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_s = cell->getPort(ID::S);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_s = cell->getPort(TW::S);
if (maybe_x(sig_s)) {
mark_maybe_x(sig_y);
return;
@ -388,15 +388,15 @@ struct XpropWorker
}
if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift))) {
auto &sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(ID::Y);
auto &sig_b = cell->getPort(TW::B);
auto &sig_y = cell->getPort(TW::Y);
if (maybe_x(sig_b)) {
mark_maybe_x(sig_y);
return;
}
auto &sig_a = cell->getPort(ID::A);
auto &sig_a = cell->getPort(TW::A);
if (maybe_x(sig_a)) {
// We could be more precise for shifts, but that's not required
@ -408,15 +408,15 @@ struct XpropWorker
}
if (cell->type.in(ID($shiftx))) {
auto &sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(ID::Y);
auto &sig_b = cell->getPort(TW::B);
auto &sig_y = cell->getPort(TW::Y);
if (cell->getParam(ID::B_SIGNED).as_bool() || GetSize(sig_b) >= 30) {
mark_maybe_x(sig_y);
} else {
int max_shift = (1 << GetSize(sig_b)) - 1;
auto &sig_a = cell->getPort(ID::A);
auto &sig_a = cell->getPort(TW::A);
for (int i = 0; i < GetSize(sig_y); i++)
if (i + max_shift >= GetSize(sig_a))
@ -428,7 +428,7 @@ struct XpropWorker
return;
}
auto &sig_a = cell->getPort(ID::A);
auto &sig_a = cell->getPort(TW::A);
if (maybe_x(sig_a)) {
// We could be more precise for shifts, but that's not required
// for correctness, so let's keep it simple
@ -457,7 +457,7 @@ struct XpropWorker
ID($_NOT_), ID($_AND_), ID($_NAND_), ID($_ANDNOT_), ID($_OR_), ID($_NOR_), ID($_ORNOT_), ID($_XOR_), ID($_XNOR_)
)) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_y = cell->getPort(TW::Y);
if (inputs_maybe_x(cell))
mark_maybe_x(sig_y[0]);
return;
@ -482,9 +482,9 @@ struct XpropWorker
if (!ports_maybe_x(cell)) {
if (cell->type == ID($bweq)) {
auto sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
RTLIL::IdString name(cell->name);
module->remove(cell);
@ -493,9 +493,9 @@ struct XpropWorker
}
if (cell->type.in(ID($nex), ID($eqx))) {
auto sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
RTLIL::IdString name(cell->name);
auto type = cell->type;
@ -511,8 +511,8 @@ struct XpropWorker
}
if (cell->type.in(ID($not), ID($_NOT_))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
if (cell->type == ID($not))
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
@ -528,9 +528,9 @@ struct XpropWorker
}
if (cell->type.in(ID($and), ID($or), ID($_AND_), ID($_OR_), ID($_NAND_), ID($_NOR_), ID($_ANDNOT_), ID($_ORNOT_))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
if (cell->type.in(ID($and), ID($or))) {
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
@ -555,8 +555,8 @@ struct XpropWorker
}
if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($logic_not))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto enc_a = encoded(sig_a);
auto enc_y = encoded(sig_y, true);
@ -577,8 +577,8 @@ struct XpropWorker
}
if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto enc_a = encoded(sig_a);
auto enc_y = encoded(sig_y, true);
@ -597,9 +597,9 @@ struct XpropWorker
}
if (cell->type.in(ID($logic_and), ID($logic_or))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_b = cell->getPort(TW::B);
auto enc_a = encoded(sig_a);
auto enc_b = encoded(sig_b);
@ -623,9 +623,9 @@ struct XpropWorker
}
if (cell->type.in(ID($xor), ID($xnor), ID($_XOR_), ID($_XNOR_))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
if (cell->type.in(ID($xor), ID($xnor))) {
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
@ -646,9 +646,9 @@ struct XpropWorker
}
if (cell->type.in(ID($eq), ID($ne))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
int width = std::max(GetSize(sig_a), GetSize(sig_b));
sig_a.extend_u0(width, cell->getParam(ID::A_SIGNED).as_bool());
sig_b.extend_u0(width, cell->getParam(ID::B_SIGNED).as_bool());
@ -672,9 +672,9 @@ struct XpropWorker
}
if (cell->type.in(ID($eqx), ID($nex))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
int width = std::max(GetSize(sig_a), GetSize(sig_b));
sig_a.extend_u0(width, cell->getParam(ID::A_SIGNED).as_bool());
sig_b.extend_u0(width, cell->getParam(ID::B_SIGNED).as_bool());
@ -697,9 +697,9 @@ struct XpropWorker
}
if (cell->type.in(ID($bweqx))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_b = cell->getPort(TW::B);
auto enc_a = encoded(sig_a);
auto enc_b = encoded(sig_b);
@ -712,10 +712,10 @@ struct XpropWorker
}
if (cell->type.in(ID($_MUX_), ID($mux), ID($bwmux))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_b = cell->getPort(ID::B);
auto sig_s = cell->getPort(ID::S);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_b = cell->getPort(TW::B);
auto sig_s = cell->getPort(TW::S);
if (cell->type == ID($mux))
sig_s = SigSpec(sig_s[0], GetSize(sig_y));
@ -737,10 +737,10 @@ struct XpropWorker
}
if (cell->type.in(ID($pmux))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_b = cell->getPort(ID::B);
auto &sig_s = cell->getPort(ID::S);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_b = cell->getPort(TW::B);
auto &sig_s = cell->getPort(TW::S);
auto enc_a = encoded(sig_a);
auto enc_b = encoded(sig_b);
@ -772,9 +772,9 @@ struct XpropWorker
}
if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_b = cell->getPort(TW::B);
auto enc_a = encoded(sig_a);
auto enc_b = encoded(sig_b);
@ -783,9 +783,9 @@ struct XpropWorker
auto all_x = module->ReduceOr(NEW_ID, enc_b.is_x)[0];
auto not_all_x = module->Not(NEW_ID, all_x)[0];
SigSpec y_not_0 = module->addWire(NEW_ID, GetSize(sig_y));
SigSpec y_1 = module->addWire(NEW_ID, GetSize(sig_y));
SigSpec y_x = module->addWire(NEW_ID, GetSize(sig_y));
SigSpec y_not_0 = module->addWire(NEW_TWINE, GetSize(sig_y));
SigSpec y_1 = module->addWire(NEW_TWINE, GetSize(sig_y));
SigSpec y_x = module->addWire(NEW_TWINE, GetSize(sig_y));
auto encoded_type = cell->type == ID($shiftx) ? ID($shift) : cell->type;
@ -793,23 +793,23 @@ struct XpropWorker
std::swap(enc_a.is_0, enc_a.is_x);
}
auto shift_0 = module->addCell(NEW_ID, encoded_type);
auto shift_0 = module->addCell(NEW_TWINE, encoded_type);
shift_0->parameters = cell->parameters;
shift_0->setPort(ID::A, module->Not(NEW_ID, enc_a.is_0));
shift_0->setPort(ID::B, enc_b.is_1);
shift_0->setPort(ID::Y, y_not_0);
shift_0->setPort(TW::A, module->Not(NEW_ID, enc_a.is_0));
shift_0->setPort(TW::B, enc_b.is_1);
shift_0->setPort(TW::Y, y_not_0);
auto shift_1 = module->addCell(NEW_ID, encoded_type);
auto shift_1 = module->addCell(NEW_TWINE, encoded_type);
shift_1->parameters = cell->parameters;
shift_1->setPort(ID::A, enc_a.is_1);
shift_1->setPort(ID::B, enc_b.is_1);
shift_1->setPort(ID::Y, y_1);
shift_1->setPort(TW::A, enc_a.is_1);
shift_1->setPort(TW::B, enc_b.is_1);
shift_1->setPort(TW::Y, y_1);
auto shift_x = module->addCell(NEW_ID, encoded_type);
auto shift_x = module->addCell(NEW_TWINE, encoded_type);
shift_x->parameters = cell->parameters;
shift_x->setPort(ID::A, enc_a.is_x);
shift_x->setPort(ID::B, enc_b.is_1);
shift_x->setPort(ID::Y, y_x);
shift_x->setPort(TW::A, enc_a.is_x);
shift_x->setPort(TW::B, enc_b.is_1);
shift_x->setPort(TW::Y, y_x);
SigSpec y_0 = module->Not(NEW_ID, y_not_0);
@ -825,8 +825,8 @@ struct XpropWorker
}
if (cell->type.in(ID($ff))) {
auto &sig_d = cell->getPort(ID::D);
auto &sig_q = cell->getPort(ID::Q);
auto &sig_d = cell->getPort(TW::D);
auto &sig_q = cell->getPort(TW::Q);
auto init_q = initvals(sig_q);
auto init_q_is_1 = init_q;
@ -842,7 +842,7 @@ struct XpropWorker
auto enc_d = encoded(sig_d);
auto enc_q = encoded(sig_q, true);
auto data_q = module->addWire(NEW_ID, GetSize(sig_q));
auto data_q = module->addWire(NEW_TWINE, GetSize(sig_q));
module->addFf(NEW_ID, enc_d.is_1, data_q);
module->addFf(NEW_ID, enc_d.is_x, enc_q.is_x);
@ -885,7 +885,7 @@ struct XpropWorker
auto enc_d = encoded(ff.sig_d);
auto enc_q = encoded(ff.sig_q, true);
auto data_q = module->addWire(NEW_ID, GetSize(ff.sig_q));
auto data_q = module->addWire(NEW_TWINE, GetSize(ff.sig_q));
ff.sig_d = enc_d.is_1;
ff.sig_q = data_q;
@ -928,11 +928,11 @@ struct XpropWorker
}
if (cell->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) {
auto sig_b = cell->getPort(ID::B);
auto sig_b = cell->getPort(TW::B);
auto invalid = module->LogicNot(NEW_ID, sig_b);
inbits_x.append(invalid);
sig_b[0] = module->Or(NEW_ID, sig_b[0], invalid);
cell->setPort(ID::B, sig_b);
cell->setPort(TW::B, sig_b);
}
SigBit outbits_x = (GetSize(inbits_x) == 1 ? inbits_x : module->ReduceOr(NEW_ID, inbits_x));
@ -945,7 +945,7 @@ struct XpropWorker
if (bool_out)
enc_port.connect_as_bool();
SigSpec new_output = module->addWire(NEW_ID, GetSize(conn.second));
SigSpec new_output = module->addWire(NEW_TWINE, GetSize(conn.second));
enc_port.connect_1_under_x(bool_out ? new_output.extract(0) : new_output);
enc_port.connect_x(SigSpec(outbits_x, GetSize(enc_port)));

8
passes/equiv/equiv_add.cc
View File

@ -84,7 +84,7 @@ struct EquivAddPass : public Pass {
if (gold_cell->input(port) && gate_cell->input(port))
{
SigSpec combined_sig = module->addWire(NEW_ID, width);
SigSpec combined_sig = module->addWire(NEW_TWINE, width);
for (int i = 0; i < width; i++) {
module->addEquiv(NEW_ID, gold_sig[i], gate_sig[i], combined_sig[i]);
@ -98,8 +98,8 @@ struct EquivAddPass : public Pass {
if (gold_cell->output(port) && gate_cell->output(port))
{
SigSpec new_gold_wire = module->addWire(NEW_ID, width);
SigSpec new_gate_wire = module->addWire(NEW_ID, width);
SigSpec new_gold_wire = module->addWire(NEW_TWINE, width);
SigSpec new_gate_wire = module->addWire(NEW_TWINE, width);
SigSig gg_conn;
for (int i = 0; i < width; i++) {
@ -141,7 +141,7 @@ struct EquivAddPass : public Pass {
}
log_assert(GetSize(gold_signal) == GetSize(gate_signal));
SigSpec equiv_signal = module->addWire(NEW_ID, GetSize(gold_signal));
SigSpec equiv_signal = module->addWire(NEW_TWINE, GetSize(gold_signal));
SigMap sigmap(module);
sigmap.apply(gold_signal);

16
passes/equiv/equiv_induct.cc
View File

@ -48,8 +48,8 @@ struct EquivInductWorker : public EquivWorker<>
report_missing_model(cfg.ignore_unknown_cells, cell);
}
if (cell->type == ID($equiv)) {
SigBit bit_a = sigmap(cell->getPort(ID::A)).as_bit();
SigBit bit_b = sigmap(cell->getPort(ID::B)).as_bit();
SigBit bit_a = sigmap(cell->getPort(TW::A)).as_bit();
SigBit bit_b = sigmap(cell->getPort(TW::B)).as_bit();
if (bit_a != bit_b) {
int ez_a = satgen.importSigBit(bit_a, step);
int ez_b = satgen.importSigBit(bit_b, step);
@ -126,7 +126,7 @@ struct EquivInductWorker : public EquivWorker<>
if (!ez->solve(new_step_not_consistent)) {
log(" Proof for induction step holds. Entire workset of %d cells proven!\n", GetSize(workset));
for (auto cell : workset)
cell->setPort(ID::B, cell->getPort(ID::A));
cell->setPort(TW::B, cell->getPort(TW::A));
success_counter += GetSize(workset);
return;
}
@ -138,10 +138,10 @@ struct EquivInductWorker : public EquivWorker<>
for (auto cell : workset)
{
SigBit bit_a = sigmap(cell->getPort(ID::A)).as_bit();
SigBit bit_b = sigmap(cell->getPort(ID::B)).as_bit();
SigBit bit_a = sigmap(cell->getPort(TW::A)).as_bit();
SigBit bit_b = sigmap(cell->getPort(TW::B)).as_bit();
log(" Trying to prove $equiv for %s:", log_signal(sigmap(cell->getPort(ID::Y))));
log(" Trying to prove $equiv for %s:", log_signal(sigmap(cell->getPort(TW::Y))));
int ez_a = satgen.importSigBit(bit_a, cfg.max_seq+1);
int ez_b = satgen.importSigBit(bit_b, cfg.max_seq+1);
@ -152,7 +152,7 @@ struct EquivInductWorker : public EquivWorker<>
if (!ez->solve(cond)) {
log(" success!\n");
cell->setPort(ID::B, cell->getPort(ID::A));
cell->setPort(TW::B, cell->getPort(TW::A));
success_counter++;
} else {
log(" failed.\n");
@ -212,7 +212,7 @@ struct EquivInductPass : public Pass {
for (auto cell : module->selected_cells())
if (cell->type == ID($equiv)) {
if (cell->getPort(ID::A) != cell->getPort(ID::B))
if (cell->getPort(TW::A) != cell->getPort(TW::B))
unproven_equiv_cells.insert(cell);
}

6
passes/equiv/equiv_make.cc
View File

@ -210,8 +210,8 @@ struct EquivMakeWorker
for (auto &bit : enc_result)
if (bit != State::S1) bit = State::S0;
SigSpec dec_eq = equiv_mod->addWire(NEW_ID);
SigSpec enc_eq = equiv_mod->addWire(NEW_ID);
SigSpec dec_eq = equiv_mod->addWire(NEW_TWINE);
SigSpec enc_eq = equiv_mod->addWire(NEW_TWINE);
equiv_mod->addEq(NEW_ID, reduced_dec_sig, reduced_dec_pat, dec_eq);
cells_list.push_back(equiv_mod->addEq(NEW_ID, reduced_enc_sig, reduced_enc_pat, enc_eq));
@ -370,7 +370,7 @@ struct EquivMakeWorker
{
for (int i = 0; i < GetSize(gold_sig); i++)
if (gold_sig[i] != gate_sig[i]) {
Wire *w = equiv_mod->addWire(NEW_ID);
Wire *w = equiv_mod->addWire(NEW_TWINE);
equiv_mod->addEquiv(NEW_ID, gold_sig[i], gate_sig[i], w);
gold_sig[i] = w;
}

8
passes/equiv/equiv_mark.cc
View File

@ -122,8 +122,8 @@ struct EquivMarkWorker
{
auto cell = module->cell(cell_name);
SigSpec sig_a = sigmap(cell->getPort(ID::A));
SigSpec sig_b = sigmap(cell->getPort(ID::B));
SigSpec sig_a = sigmap(cell->getPort(TW::A));
SigSpec sig_b = sigmap(cell->getPort(TW::B));
if (sig_a == sig_b) {
for (auto bit : sig_a)
@ -142,8 +142,8 @@ struct EquivMarkWorker
if (cell_regions.count(cell->name) || cell->type != ID($equiv))
continue;
SigSpec sig_a = sigmap(cell->getPort(ID::A));
SigSpec sig_b = sigmap(cell->getPort(ID::B));
SigSpec sig_a = sigmap(cell->getPort(TW::A));
SigSpec sig_b = sigmap(cell->getPort(TW::B));
log_assert(sig_a != sig_b);

10
passes/equiv/equiv_miter.cc
View File

@ -214,18 +214,18 @@ struct EquivMiterWorker
vector<Cell*> equiv_cells;
for (auto c : miter_module->cells())
if (c->type == ID($equiv) && c->getPort(ID::A) != c->getPort(ID::B))
if (c->type == ID($equiv) && c->getPort(TW::A) != c->getPort(TW::B))
equiv_cells.push_back(c);
for (auto c : equiv_cells)
{
SigSpec cmp = mode_undef ?
miter_module->LogicOr(NEW_ID, miter_module->Eqx(NEW_ID, c->getPort(ID::A), State::Sx),
miter_module->Eqx(NEW_ID, c->getPort(ID::A), c->getPort(ID::B))) :
miter_module->Eq(NEW_ID, c->getPort(ID::A), c->getPort(ID::B));
miter_module->LogicOr(NEW_ID, miter_module->Eqx(NEW_ID, c->getPort(TW::A), State::Sx),
miter_module->Eqx(NEW_ID, c->getPort(TW::A), c->getPort(TW::B))) :
miter_module->Eq(NEW_ID, c->getPort(TW::A), c->getPort(TW::B));
if (mode_cmp) {
string cmp_name = stringf("\\cmp%s", log_signal(c->getPort(ID::Y)));
string cmp_name = stringf("\\cmp%s", log_signal(c->getPort(TW::Y)));
for (int i = 1; i < GetSize(cmp_name); i++)
if (cmp_name[i] == '\\')
cmp_name[i] = '_';

14
passes/equiv/equiv_purge.cc
View File

@ -67,7 +67,7 @@ struct EquivPurgeWorker
log(" Module input: %s\n", log_signal(wire));
wire->port_input = true;
}
return module->addWire(NEW_ID, GetSize(sig));
return module->addWire(NEW_TWINE, GetSize(sig));
}
}
@ -81,7 +81,7 @@ struct EquivPurgeWorker
wire->port_input = true;
module->connect(sig, wire);
log(" Module input: %s (%s)\n", log_signal(wire), log_signal(sig));
return module->addWire(NEW_ID, GetSize(sig));
return module->addWire(NEW_TWINE, GetSize(sig));
}
}
@ -114,9 +114,9 @@ struct EquivPurgeWorker
continue;
}
SigSpec sig_a = sigmap(cell->getPort(ID::A));
SigSpec sig_b = sigmap(cell->getPort(ID::B));
SigSpec sig_y = sigmap(cell->getPort(ID::Y));
SigSpec sig_a = sigmap(cell->getPort(TW::A));
SigSpec sig_b = sigmap(cell->getPort(TW::B));
SigSpec sig_y = sigmap(cell->getPort(TW::Y));
if (sig_a == sig_b)
continue;
@ -130,7 +130,7 @@ struct EquivPurgeWorker
for (auto bit : sig_y)
visited.insert(bit);
cell->setPort(ID::Y, make_output(sig_y, cell->name));
cell->setPort(TW::Y, make_output(sig_y, cell->name));
}
SigSpec srcsig;
@ -168,7 +168,7 @@ struct EquivPurgeWorker
for (auto cell : module->cells())
if (cell->type == ID($equiv))
cell->setPort(ID::Y, rewrite_sigmap(sigmap(cell->getPort(ID::Y))));
cell->setPort(TW::Y, rewrite_sigmap(sigmap(cell->getPort(TW::Y))));
module->fixup_ports();
}

6
passes/equiv/equiv_remove.cc
View File

@ -68,9 +68,9 @@ struct EquivRemovePass : public Pass {
for (auto module : design->selected_modules())
{
for (auto cell : module->selected_cells())
if (cell->type == ID($equiv) && (mode_gold || mode_gate || cell->getPort(ID::A) == cell->getPort(ID::B))) {
log("Removing $equiv cell %s.%s (%s).\n", module, cell, log_signal(cell->getPort(ID::Y)));
module->connect(cell->getPort(ID::Y), mode_gate ? cell->getPort(ID::B) : cell->getPort(ID::A));
if (cell->type == ID($equiv) && (mode_gold || mode_gate || cell->getPort(TW::A) == cell->getPort(TW::B))) {
log("Removing $equiv cell %s.%s (%s).\n", module, cell, log_signal(cell->getPort(TW::Y)));
module->connect(cell->getPort(TW::Y), mode_gate ? cell->getPort(TW::B) : cell->getPort(TW::A));
module->remove(cell);
remove_count++;
}

20
passes/equiv/equiv_simple.cc
View File

@ -230,8 +230,8 @@ struct EquivSimpleWorker : public EquivWorker<EquivSimpleConfig>
pool<Cell*> extra_problem_cells;
for (auto assume : assume_cells) {
pool<SigBit> assume_seed, dummy_next_seed, overlap_bits;
assume_seed.insert(model.sigmap(assume->getPort(ID::A)).as_bit());
assume_seed.insert(model.sigmap(assume->getPort(ID::EN)).as_bit());
assume_seed.insert(model.sigmap(assume->getPort(TW::A)).as_bit());
assume_seed.insert(model.sigmap(assume->getPort(TW::EN)).as_bit());
for (auto& cone : {cone_a, cone_b}) {
Cone assume_cone;
@ -292,8 +292,8 @@ struct EquivSimpleWorker : public EquivWorker<EquivSimpleConfig>
bool prove_equiv_cell(Cell* cell)
{
SigBit bit_a = model.sigmap(cell->getPort(ID::A)).as_bit();
SigBit bit_b = model.sigmap(cell->getPort(ID::B)).as_bit();
SigBit bit_a = model.sigmap(cell->getPort(TW::A)).as_bit();
SigBit bit_b = model.sigmap(cell->getPort(TW::B)).as_bit();
int ez_context = ez->frozen_literal();
prepare_ezsat(ez_context, bit_a, bit_b);
@ -306,9 +306,9 @@ struct EquivSimpleWorker : public EquivWorker<EquivSimpleConfig>
if (cfg.verbose) {
log(" Trying to prove $equiv cell %s:\n", cell);
log(" A = %s, B = %s, Y = %s\n", log_signal(bit_a), log_signal(bit_b), log_signal(cell->getPort(ID::Y)));
log(" A = %s, B = %s, Y = %s\n", log_signal(bit_a), log_signal(bit_b), log_signal(cell->getPort(TW::Y)));
} else {
log(" Trying to prove $equiv for %s:", log_signal(cell->getPort(ID::Y)));
log(" Trying to prove $equiv for %s:", log_signal(cell->getPort(TW::Y)));
}
int step = cfg.max_seq;
@ -347,7 +347,7 @@ struct EquivSimpleWorker : public EquivWorker<EquivSimpleConfig>
if (!ez->solve(ez_context)) {
log("%s", cfg.verbose ? " Proved equivalence! Marking $equiv cell as proven.\n" : " success!\n");
// Replace $equiv cell with a short
cell->setPort(ID::B, cell->getPort(ID::A));
cell->setPort(TW::B, cell->getPort(TW::A));
ez->assume(ez->NOT(ez_context));
return true;
}
@ -404,7 +404,7 @@ struct EquivSimpleWorker : public EquivWorker<EquivSimpleConfig>
if (GetSize(equiv_cells) > 1) {
SigSpec sig;
for (auto c : equiv_cells)
sig.append(model.sigmap(c->getPort(ID::Y)));
sig.append(model.sigmap(c->getPort(TW::Y)));
log(" Grouping SAT models for %s:\n", log_signal(sig));
}
@ -461,8 +461,8 @@ struct EquivSimplePass : public Pass {
int unproven_cells_counter = 0;
for (auto cell : module->selected_cells()) {
if (cell->type == ID($equiv) && cell->getPort(ID::A) != cell->getPort(ID::B)) {
auto bit = sigmap(cell->getPort(ID::Y).as_bit());
if (cell->type == ID($equiv) && cell->getPort(TW::A) != cell->getPort(TW::B)) {
auto bit = sigmap(cell->getPort(TW::Y).as_bit());
auto bit_group = bit;
if (cfg.group && bit_group.wire)
bit_group.offset = 0;

4
passes/equiv/equiv_status.cc
View File

@ -60,7 +60,7 @@ struct EquivStatusPass : public Pass {
for (auto cell : module->selected_cells())
if (cell->type == ID($equiv)) {
if (cell->getPort(ID::A) != cell->getPort(ID::B))
if (cell->getPort(TW::A) != cell->getPort(TW::B))
unproven_equiv_cells.push_back(cell);
else
proven_equiv_cells++;
@ -77,7 +77,7 @@ struct EquivStatusPass : public Pass {
log(" Equivalence successfully proven!\n");
} else {
for (auto cell : unproven_equiv_cells)
log(" Unproven $equiv %s: %s %s\n", cell, log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::B)));
log(" Unproven $equiv %s: %s %s\n", cell, log_signal(cell->getPort(TW::A)), log_signal(cell->getPort(TW::B)));
}
unproven_count += GetSize(unproven_equiv_cells);

12
passes/equiv/equiv_struct.cc
View File

@ -85,7 +85,7 @@ struct EquivStructWorker
for (int i = 0; i < GetSize(inputs_a); i++) {
SigBit bit_a = inputs_a[i], bit_b = inputs_b[i];
SigBit bit_y = module->addWire(NEW_ID);
SigBit bit_y = module->addWire(NEW_TWINE);
log(" New $equiv for input %s: A: %s, B: %s, Y: %s\n",
input_names[i].c_str(), log_signal(bit_a), log_signal(bit_b), log_signal(bit_y));
module->addEquiv(NEW_ID, bit_a, bit_b, bit_y);
@ -127,8 +127,8 @@ struct EquivStructWorker
for (auto cell : module->selected_cells())
if (cell->type == ID($equiv)) {
SigBit sig_a = sigmap(cell->getPort(ID::A).as_bit());
SigBit sig_b = sigmap(cell->getPort(ID::B).as_bit());
SigBit sig_a = sigmap(cell->getPort(TW::A).as_bit());
SigBit sig_b = sigmap(cell->getPort(TW::B).as_bit());
equiv_bits.add(sig_b, sig_a);
equiv_inputs.insert(sig_a);
equiv_inputs.insert(sig_b);
@ -140,9 +140,9 @@ struct EquivStructWorker
for (auto cell : module->selected_cells())
if (cell->type == ID($equiv)) {
SigBit sig_a = sigmap(cell->getPort(ID::A).as_bit());
SigBit sig_b = sigmap(cell->getPort(ID::B).as_bit());
SigBit sig_y = sigmap(cell->getPort(ID::Y).as_bit());
SigBit sig_a = sigmap(cell->getPort(TW::A).as_bit());
SigBit sig_b = sigmap(cell->getPort(TW::B).as_bit());
SigBit sig_y = sigmap(cell->getPort(TW::Y).as_bit());
if (sig_a == sig_b && equiv_inputs.count(sig_y)) {
log(" Purging redundant $equiv cell %s.\n", cell);
module->connect(sig_y, sig_a);

16
passes/fsm/fsm_detect.cc
View File

@ -67,8 +67,8 @@ ret_false:
recursion_monitor.insert(cellport.first);
RTLIL::SigSpec sig_a = assign_map(cellport.first->getPort(ID::A));
RTLIL::SigSpec sig_b = assign_map(cellport.first->getPort(ID::B));
RTLIL::SigSpec sig_a = assign_map(cellport.first->getPort(TW::A));
RTLIL::SigSpec sig_b = assign_map(cellport.first->getPort(TW::B));
if (!check_state_mux_tree(old_sig, sig_a, recursion_monitor, mux_tree_cache)) {
recursion_monitor.erase(cellport.first);
@ -101,7 +101,7 @@ static bool check_state_users(RTLIL::SigSpec sig)
continue;
if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
continue;
if (cell->type == ID($logic_not) && assign_map(cell->getPort(ID::A)) == sig)
if (cell->type == ID($logic_not) && assign_map(cell->getPort(TW::A)) == sig)
continue;
if (cellport.second != ID::A && cellport.second != ID::B)
return false;
@ -110,9 +110,9 @@ static bool check_state_users(RTLIL::SigSpec sig)
for (auto &port_it : cell->connections())
if (port_it.first != ID::A && port_it.first != ID::B && port_it.first != ID::Y)
return false;
if (assign_map(cell->getPort(ID::A)) == sig && cell->getPort(ID::B).is_fully_const())
if (assign_map(cell->getPort(TW::A)) == sig && cell->getPort(TW::B).is_fully_const())
continue;
if (assign_map(cell->getPort(ID::B)) == sig && cell->getPort(ID::A).is_fully_const())
if (assign_map(cell->getPort(TW::B)) == sig && cell->getPort(TW::A).is_fully_const())
continue;
return false;
}
@ -150,8 +150,8 @@ static void detect_fsm(RTLIL::Wire *wire, bool ignore_self_reset=false)
muxtree_cells.clear();
pool<Cell*> recursion_monitor;
RTLIL::SigSpec sig_q = assign_map(cellport.first->getPort(ID::Q));
RTLIL::SigSpec sig_d = assign_map(cellport.first->getPort(ID::D));
RTLIL::SigSpec sig_q = assign_map(cellport.first->getPort(TW::Q));
RTLIL::SigSpec sig_d = assign_map(cellport.first->getPort(TW::D));
dict<RTLIL::SigSpec, bool> mux_tree_cache;
if (sig_q != assign_map(wire))
@ -203,7 +203,7 @@ static void detect_fsm(RTLIL::Wire *wire, bool ignore_self_reset=false)
SigSpec sig_y = sig_d, sig_undef;
if (!ignore_self_reset) {
if (cellport.first->type == ID($adff)) {
SigSpec sig_arst = assign_map(cellport.first->getPort(ID::ARST));
SigSpec sig_arst = assign_map(cellport.first->getPort(TW::ARST));
if (ce.eval(sig_arst, sig_undef))
is_self_resetting = true;
}

46
passes/fsm/fsm_expand.cc
View File

@ -35,12 +35,12 @@ struct FsmExpand
bool full_mode;
SigMap assign_map;
SigSet<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> sig2driver, sig2user;
SigSet<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> sig2driver, sig2user;
CellTypes ct;
std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> merged_set;
std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> current_set;
std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> no_candidate_set;
std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> merged_set;
std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> current_set;
std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> no_candidate_set;
bool already_optimized;
int limit_transitions;
@ -51,38 +51,38 @@ struct FsmExpand
return true;
if (cell->type.in(ID($mux), ID($pmux)))
if (cell->getPort(ID::A).size() < 2)
if (cell->getPort(TW::A).size() < 2)
return true;
int in_bits = 0;
RTLIL::SigSpec new_signals;
if (cell->hasPort(ID::A)) {
in_bits += GetSize(cell->getPort(ID::A));
new_signals.append(assign_map(cell->getPort(ID::A)));
in_bits += GetSize(cell->getPort(TW::A));
new_signals.append(assign_map(cell->getPort(TW::A)));
}
if (cell->hasPort(ID::B)) {
in_bits += GetSize(cell->getPort(ID::B));
new_signals.append(assign_map(cell->getPort(ID::B)));
in_bits += GetSize(cell->getPort(TW::B));
new_signals.append(assign_map(cell->getPort(TW::B)));
}
if (cell->hasPort(ID::S)) {
in_bits += GetSize(cell->getPort(ID::S));
new_signals.append(assign_map(cell->getPort(ID::S)));
in_bits += GetSize(cell->getPort(TW::S));
new_signals.append(assign_map(cell->getPort(TW::S)));
}
if (in_bits > 8)
return false;
if (cell->hasPort(ID::Y))
new_signals.append(assign_map(cell->getPort(ID::Y)));
new_signals.append(assign_map(cell->getPort(TW::Y)));
new_signals.sort_and_unify();
new_signals.remove_const();
new_signals.remove(assign_map(fsm_cell->getPort(ID::CTRL_IN)));
new_signals.remove(assign_map(fsm_cell->getPort(ID::CTRL_OUT)));
new_signals.remove(assign_map(fsm_cell->getPort(TW::CTRL_IN)));
new_signals.remove(assign_map(fsm_cell->getPort(TW::CTRL_OUT)));
if (new_signals.size() > 3)
return false;
@ -94,10 +94,10 @@ struct FsmExpand
{
std::vector<RTLIL::Cell*> cell_list;
for (auto c : sig2driver.find(assign_map(fsm_cell->getPort(ID::CTRL_IN))))
for (auto c : sig2driver.find(assign_map(fsm_cell->getPort(TW::CTRL_IN))))
cell_list.push_back(c);
for (auto c : sig2user.find(assign_map(fsm_cell->getPort(ID::CTRL_OUT))))
for (auto c : sig2user.find(assign_map(fsm_cell->getPort(TW::CTRL_OUT))))
cell_list.push_back(c);
current_set.clear();
@ -160,11 +160,11 @@ struct FsmExpand
RTLIL::Const in_val(i, input_sig.size());
RTLIL::SigSpec A, B, S;
if (cell->hasPort(ID::A))
A = assign_map(cell->getPort(ID::A));
A = assign_map(cell->getPort(TW::A));
if (cell->hasPort(ID::B))
B = assign_map(cell->getPort(ID::B));
B = assign_map(cell->getPort(TW::B));
if (cell->hasPort(ID::S))
S = assign_map(cell->getPort(ID::S));
S = assign_map(cell->getPort(TW::S));
A.replace(input_sig, RTLIL::SigSpec(in_val));
B.replace(input_sig, RTLIL::SigSpec(in_val));
S.replace(input_sig, RTLIL::SigSpec(in_val));
@ -178,14 +178,14 @@ struct FsmExpand
fsm_data.copy_from_cell(fsm_cell);
fsm_data.num_inputs += input_sig.size();
RTLIL::SigSpec new_ctrl_in = fsm_cell->getPort(ID::CTRL_IN);
RTLIL::SigSpec new_ctrl_in = fsm_cell->getPort(TW::CTRL_IN);
new_ctrl_in.append(input_sig);
fsm_cell->setPort(ID::CTRL_IN, new_ctrl_in);
fsm_cell->setPort(TW::CTRL_IN, new_ctrl_in);
fsm_data.num_outputs += output_sig.size();
RTLIL::SigSpec new_ctrl_out = fsm_cell->getPort(ID::CTRL_OUT);
RTLIL::SigSpec new_ctrl_out = fsm_cell->getPort(TW::CTRL_OUT);
new_ctrl_out.append(output_sig);
fsm_cell->setPort(ID::CTRL_OUT, new_ctrl_out);
fsm_cell->setPort(TW::CTRL_OUT, new_ctrl_out);
if (GetSize(input_sig) > 10)
log_warning("Cell %s.%s (%s) has %d input bits, merging into FSM %s.%s might be problematic.\n",

34
passes/fsm/fsm_extract.cc
View File

@ -75,10 +75,10 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
return false;
}
RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B));
RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID::S));
RTLIL::SigSpec sig_y = assign_map(cell->getPort(ID::Y));
RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A));
RTLIL::SigSpec sig_b = assign_map(cell->getPort(TW::B));
RTLIL::SigSpec sig_s = assign_map(cell->getPort(TW::S));
RTLIL::SigSpec sig_y = assign_map(cell->getPort(TW::Y));
RTLIL::SigSpec sig_aa = sig;
sig_aa.replace(sig_y, sig_a);
@ -275,12 +275,12 @@ static void extract_fsm(RTLIL::Wire *wire)
if ((cell->type != ID($dff) && cell->type != ID($adff)) || cellport.second != ID::Q)
continue;
log(" found %s cell for state register: %s\n", cell->type, cell->name);
RTLIL::SigSpec sig_q = assign_map(cell->getPort(ID::Q));
RTLIL::SigSpec sig_d = assign_map(cell->getPort(ID::D));
clk = cell->getPort(ID::CLK);
RTLIL::SigSpec sig_q = assign_map(cell->getPort(TW::Q));
RTLIL::SigSpec sig_d = assign_map(cell->getPort(TW::D));
clk = cell->getPort(TW::CLK);
clk_polarity = cell->parameters[ID::CLK_POLARITY].as_bool();
if (cell->type == ID($adff)) {
arst = cell->getPort(ID::ARST);
arst = cell->getPort(TW::ARST);
arst_polarity = cell->parameters[ID::ARST_POLARITY].as_bool();
reset_state = cell->parameters[ID::ARST_VALUE];
}
@ -320,11 +320,11 @@ static void extract_fsm(RTLIL::Wire *wire)
sig2trigger.find(dff_out, cellport_list);
for (auto &cellport : cellport_list) {
RTLIL::Cell *cell = module->cell(cellport.first);
RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A));
RTLIL::SigSpec sig_b;
if (cell->hasPort(ID::B))
sig_b = assign_map(cell->getPort(ID::B));
RTLIL::SigSpec sig_y = assign_map(cell->getPort(ID::Y));
sig_b = assign_map(cell->getPort(TW::B));
RTLIL::SigSpec sig_y = assign_map(cell->getPort(TW::Y));
if (cellport.second == ID::A && !sig_b.is_fully_const())
continue;
if (cellport.second == ID::B && !sig_a.is_fully_const())
@ -369,12 +369,12 @@ static void extract_fsm(RTLIL::Wire *wire)
// create fsm cell
RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name, autoidx++), ID($fsm));
fsm_cell->setPort(ID::CLK, clk);
fsm_cell->setPort(ID::ARST, arst);
fsm_cell->setPort(TW::CLK, clk);
fsm_cell->setPort(TW::ARST, arst);
fsm_cell->parameters[ID::CLK_POLARITY] = clk_polarity ? State::S1 : State::S0;
fsm_cell->parameters[ID::ARST_POLARITY] = arst_polarity ? State::S1 : State::S0;
fsm_cell->setPort(ID::CTRL_IN, ctrl_in);
fsm_cell->setPort(ID::CTRL_OUT, ctrl_out);
fsm_cell->setPort(TW::CTRL_IN, ctrl_in);
fsm_cell->setPort(TW::CTRL_OUT, ctrl_out);
fsm_cell->parameters[ID::NAME] = RTLIL::Const(wire->name.str());
fsm_cell->attributes = wire->attributes;
if(fsm_cell->attributes.count(ID::hdlname)) {
@ -452,14 +452,14 @@ struct FsmExtractPass : public Pass {
sig2driver.insert(sig, sig2driver_entry_t(cell->name, conn_it.first));
}
if (ct.cell_input(cell->type, conn_it.first) && cell->hasPort(ID::Y) &&
cell->getPort(ID::Y).size() == 1 && (conn_it.first == ID::A || conn_it.first == ID::B)) {
cell->getPort(TW::Y).size() == 1 && (conn_it.first == ID::A || conn_it.first == ID::B)) {
RTLIL::SigSpec sig = conn_it.second;
assign_map.apply(sig);
sig2trigger.insert(sig, sig2driver_entry_t(cell->name, conn_it.first));
}
}
if (cell->type == ID($pmux)) {
RTLIL::SigSpec sel_sig = assign_map(cell->getPort(ID::S));
RTLIL::SigSpec sel_sig = assign_map(cell->getPort(TW::S));
for (auto &bit1 : sel_sig)
for (auto &bit2 : sel_sig)
if (bit1 != bit2)

74
passes/fsm/fsm_map.cc
View File

@ -71,13 +71,13 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
if (eq_sig_a.size() > 0)
{
RTLIL::Wire *eq_wire = module->addWire(NEW_ID);
RTLIL::Wire *eq_wire = module->addWire(NEW_TWINE);
and_sig.append(RTLIL::SigSpec(eq_wire));
RTLIL::Cell *eq_cell = module->addCell(NEW_ID, ID($eq));
eq_cell->setPort(ID::A, eq_sig_a);
eq_cell->setPort(ID::B, eq_sig_b);
eq_cell->setPort(ID::Y, RTLIL::SigSpec(eq_wire));
RTLIL::Cell *eq_cell = module->addCell(NEW_TWINE, ID($eq));
eq_cell->setPort(TW::A, eq_sig_a);
eq_cell->setPort(TW::B, eq_sig_b);
eq_cell->setPort(TW::Y, RTLIL::SigSpec(eq_wire));
eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
eq_cell->parameters[ID::B_SIGNED] = RTLIL::Const(false);
eq_cell->parameters[ID::A_WIDTH] = RTLIL::Const(eq_sig_a.size());
@ -99,12 +99,12 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
}
else
{
RTLIL::Wire *or_wire = module->addWire(NEW_ID);
RTLIL::Wire *or_wire = module->addWire(NEW_TWINE);
and_sig.append(RTLIL::SigSpec(or_wire));
RTLIL::Cell *or_cell = module->addCell(NEW_ID, ID($reduce_or));
or_cell->setPort(ID::A, or_sig);
or_cell->setPort(ID::Y, RTLIL::SigSpec(or_wire));
RTLIL::Cell *or_cell = module->addCell(NEW_TWINE, ID($reduce_or));
or_cell->setPort(TW::A, or_sig);
or_cell->setPort(TW::Y, RTLIL::SigSpec(or_wire));
or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
or_cell->parameters[ID::A_WIDTH] = RTLIL::Const(or_sig.size());
or_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
@ -115,13 +115,13 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
{
case 2:
{
RTLIL::Wire *and_wire = module->addWire(NEW_ID);
RTLIL::Wire *and_wire = module->addWire(NEW_TWINE);
cases_vector.append(RTLIL::SigSpec(and_wire));
RTLIL::Cell *and_cell = module->addCell(NEW_ID, ID($and));
and_cell->setPort(ID::A, and_sig.extract(0, 1));
and_cell->setPort(ID::B, and_sig.extract(1, 1));
and_cell->setPort(ID::Y, RTLIL::SigSpec(and_wire));
RTLIL::Cell *and_cell = module->addCell(NEW_TWINE, ID($and));
and_cell->setPort(TW::A, and_sig.extract(0, 1));
and_cell->setPort(TW::B, and_sig.extract(1, 1));
and_cell->setPort(TW::Y, RTLIL::SigSpec(and_wire));
and_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
and_cell->parameters[ID::B_SIGNED] = RTLIL::Const(false);
and_cell->parameters[ID::A_WIDTH] = RTLIL::Const(1);
@ -141,9 +141,9 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
}
if (cases_vector.size() > 1) {
RTLIL::Cell *or_cell = module->addCell(NEW_ID, ID($reduce_or));
or_cell->setPort(ID::A, cases_vector);
or_cell->setPort(ID::Y, output);
RTLIL::Cell *or_cell = module->addCell(NEW_TWINE, ID($reduce_or));
or_cell->setPort(TW::A, cases_vector);
or_cell->setPort(TW::Y, output);
or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
or_cell->parameters[ID::A_WIDTH] = RTLIL::Const(cases_vector.size());
or_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
@ -161,16 +161,16 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
FsmData fsm_data;
fsm_data.copy_from_cell(fsm_cell);
RTLIL::SigSpec ctrl_in = fsm_cell->getPort(ID::CTRL_IN);
RTLIL::SigSpec ctrl_out = fsm_cell->getPort(ID::CTRL_OUT);
RTLIL::SigSpec ctrl_in = fsm_cell->getPort(TW::CTRL_IN);
RTLIL::SigSpec ctrl_out = fsm_cell->getPort(TW::CTRL_OUT);
// create state register
RTLIL::Wire *state_wire = module->addWire(module->uniquify(fsm_cell->parameters[ID::NAME].decode_string()), fsm_data.state_bits);
RTLIL::Wire *next_state_wire = module->addWire(NEW_ID, fsm_data.state_bits);
RTLIL::Wire *next_state_wire = module->addWire(NEW_TWINE, fsm_data.state_bits);
RTLIL::Cell *state_dff = module->addCell(NEW_ID, "");
if (fsm_cell->getPort(ID::ARST).is_fully_const()) {
RTLIL::Cell *state_dff = module->addCell(NEW_TWINE, "");
if (fsm_cell->getPort(TW::ARST).is_fully_const()) {
state_dff->type = ID($dff);
} else {
state_dff->type = ID($adff);
@ -179,19 +179,19 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
for (auto bit : state_dff->parameters[ID::ARST_VALUE])
if (bit != RTLIL::State::S1)
bit = RTLIL::State::S0;
state_dff->setPort(ID::ARST, fsm_cell->getPort(ID::ARST));
state_dff->setPort(TW::ARST, fsm_cell->getPort(TW::ARST));
}
state_dff->parameters[ID::WIDTH] = RTLIL::Const(fsm_data.state_bits);
state_dff->parameters[ID::CLK_POLARITY] = fsm_cell->parameters[ID::CLK_POLARITY];
state_dff->setPort(ID::CLK, fsm_cell->getPort(ID::CLK));
state_dff->setPort(ID::D, RTLIL::SigSpec(next_state_wire));
state_dff->setPort(ID::Q, RTLIL::SigSpec(state_wire));
state_dff->setPort(TW::CLK, fsm_cell->getPort(TW::CLK));
state_dff->setPort(TW::D, RTLIL::SigSpec(next_state_wire));
state_dff->setPort(TW::Q, RTLIL::SigSpec(state_wire));
// decode state register
bool encoding_is_onehot = true;
RTLIL::Wire *state_onehot = module->addWire(NEW_ID, fsm_data.state_table.size());
RTLIL::Wire *state_onehot = module->addWire(NEW_TWINE, fsm_data.state_table.size());
for (size_t i = 0; i < fsm_data.state_table.size(); i++)
{
@ -212,10 +212,10 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
{
encoding_is_onehot = false;
RTLIL::Cell *eq_cell = module->addCell(NEW_ID, ID($eq));
eq_cell->setPort(ID::A, sig_a);
eq_cell->setPort(ID::B, sig_b);
eq_cell->setPort(ID::Y, RTLIL::SigSpec(state_onehot, i));
RTLIL::Cell *eq_cell = module->addCell(NEW_TWINE, ID($eq));
eq_cell->setPort(TW::A, sig_a);
eq_cell->setPort(TW::B, sig_b);
eq_cell->setPort(TW::Y, RTLIL::SigSpec(state_onehot, i));
eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
eq_cell->parameters[ID::B_SIGNED] = RTLIL::Const(false);
eq_cell->parameters[ID::A_WIDTH] = RTLIL::Const(sig_a.size());
@ -235,7 +235,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
}
else
{
RTLIL::Wire *next_state_onehot = module->addWire(NEW_ID, fsm_data.state_table.size());
RTLIL::Wire *next_state_onehot = module->addWire(NEW_TWINE, fsm_data.state_table.size());
for (size_t i = 0; i < fsm_data.state_table.size(); i++)
{
@ -285,11 +285,11 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
}
}
RTLIL::Cell *mux_cell = module->addCell(NEW_ID, ID($pmux));
mux_cell->setPort(ID::A, sig_a);
mux_cell->setPort(ID::B, sig_b);
mux_cell->setPort(ID::S, sig_s);
mux_cell->setPort(ID::Y, RTLIL::SigSpec(next_state_wire));
RTLIL::Cell *mux_cell = module->addCell(NEW_TWINE, ID($pmux));
mux_cell->setPort(TW::A, sig_a);
mux_cell->setPort(TW::B, sig_b);
mux_cell->setPort(TW::S, sig_s);
mux_cell->setPort(TW::Y, RTLIL::SigSpec(next_state_wire));
mux_cell->parameters[ID::WIDTH] = RTLIL::Const(sig_a.size());
mux_cell->parameters[ID::S_WIDTH] = RTLIL::Const(sig_s.size());
}

14
passes/fsm/fsm_opt.cc
View File

@ -98,7 +98,7 @@ struct FsmOpt
void opt_const_and_unused_inputs()
{
RTLIL::SigSpec ctrl_in = cell->getPort(ID::CTRL_IN);
RTLIL::SigSpec ctrl_in = cell->getPort(TW::CTRL_IN);
std::vector<bool> ctrl_in_used(ctrl_in.size());
std::vector<FsmData::transition_t> new_transition_table;
@ -119,15 +119,15 @@ struct FsmOpt
for (int i = int(ctrl_in_used.size())-1; i >= 0; i--) {
if (!ctrl_in_used[i]) {
log(" Removing unused input signal %s.\n", log_signal(cell->getPort(ID::CTRL_IN).extract(i, 1)));
log(" Removing unused input signal %s.\n", log_signal(cell->getPort(TW::CTRL_IN).extract(i, 1)));
for (auto &tr : new_transition_table) {
RTLIL::SigSpec tmp(tr.ctrl_in);
tmp.remove(i, 1);
tr.ctrl_in = tmp.as_const();
}
RTLIL::SigSpec new_ctrl_in = cell->getPort(ID::CTRL_IN);
RTLIL::SigSpec new_ctrl_in = cell->getPort(TW::CTRL_IN);
new_ctrl_in.remove(i, 1);
cell->setPort(ID::CTRL_IN, new_ctrl_in);
cell->setPort(TW::CTRL_IN, new_ctrl_in);
fsm_data.num_inputs--;
}
}
@ -139,12 +139,12 @@ struct FsmOpt
void opt_unused_outputs()
{
for (int i = 0; i < fsm_data.num_outputs; i++) {
RTLIL::SigSpec sig = cell->getPort(ID::CTRL_OUT).extract(i, 1);
RTLIL::SigSpec sig = cell->getPort(TW::CTRL_OUT).extract(i, 1);
if (signal_is_unused(sig)) {
log(" Removing unused output signal %s.\n", log_signal(sig));
RTLIL::SigSpec new_ctrl_out = cell->getPort(ID::CTRL_OUT);
RTLIL::SigSpec new_ctrl_out = cell->getPort(TW::CTRL_OUT);
new_ctrl_out.remove(i, 1);
cell->setPort(ID::CTRL_OUT, new_ctrl_out);
cell->setPort(TW::CTRL_OUT, new_ctrl_out);
for (auto &tr : fsm_data.transition_table) {
RTLIL::SigSpec tmp(tr.ctrl_out);
tmp.remove(i, 1);

4
passes/fsm/fsmdata.h
View File

@ -127,13 +127,13 @@ struct FsmData
log("\n");
log(" Input signals:\n");
RTLIL::SigSpec sig_in = cell->getPort(ID::CTRL_IN);
RTLIL::SigSpec sig_in = cell->getPort(TW::CTRL_IN);
for (int i = 0; i < GetSize(sig_in); i++)
log(" %3d: %s\n", i, log_signal(sig_in[i]));
log("\n");
log(" Output signals:\n");
RTLIL::SigSpec sig_out = cell->getPort(ID::CTRL_OUT);
RTLIL::SigSpec sig_out = cell->getPort(TW::CTRL_OUT);
for (int i = 0; i < GetSize(sig_out); i++)
log(" %3d: %s\n", i, log_signal(sig_out[i]));

2
passes/hierarchy/flatten.cc
View File

@ -275,7 +275,7 @@ struct FlattenWorker
if (create_scopeinfo && cell_name.isPublic())
{
// The $scopeinfo's name will be changed below after removing the flattened cell
scopeinfo = module->addCell(NEW_ID, ID($scopeinfo));
scopeinfo = module->addCell(NEW_TWINE, ID($scopeinfo));
scopeinfo->setParam(ID::TYPE, RTLIL::Const("module"));
for (auto const &attr : cell->attributes)

8
passes/hierarchy/hierarchy.cc
View File

@ -98,7 +98,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
}
while (portnames.size() > 0) {
RTLIL::IdString portname = *portnames.begin();
TwineRef portname = *portnames.begin();
for (auto &decl : portdecls)
if (decl.index == 0 && patmatch(decl.portname.c_str(), portname.unescape().c_str())) {
generate_port_decl_t d = decl;
@ -604,7 +604,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
for (auto &conn : cell->connections_) {
int conn_size = conn.second.size();
RTLIL::IdString portname = conn.first;
TwineRef portname = conn.first;
if (portname.begins_with("$")) {
int port_id = atoi(portname.substr(1).c_str());
for (auto wire : mod->wires())
@ -1421,7 +1421,7 @@ struct HierarchyPass : public Pass {
continue;
}
Wire *t = module->addWire(NEW_ID, GetSize(c));
Wire *t = module->addWire(NEW_TWINE, GetSize(c));
new_sig.append(t);
update_port = true;
@ -1524,7 +1524,7 @@ struct HierarchyPass : public Pass {
if (w->port_input && !w->port_output)
sig.extend_u0(GetSize(w), sig.is_wire() && sig.as_wire()->is_signed);
else
sig.append(module->addWire(NEW_ID, n));
sig.append(module->addWire(NEW_TWINE, n));
}
if (!conn.second.is_fully_const() || !w->port_input || w->port_output)

4
passes/hierarchy/submod.cc
View File

@ -233,10 +233,10 @@ struct SubmodWorker
auto &b = old_sig[i];
// Prevents "ERROR: Mismatch in directionality ..." when flattening
if (!b.wire)
b = module->addWire(NEW_ID);
b = module->addWire(NEW_TWINE);
// Prevents "Warning: multiple conflicting drivers ..."
else if (!it.second.is_int_driven[i])
b = module->addWire(NEW_ID);
b = module->addWire(NEW_TWINE);
}
new_cell->setPort(new_wire->name, old_sig);
}

6
passes/memory/memory_bmux2rom.cc
View File

@ -50,7 +50,7 @@ struct MemoryBmux2RomPass : public Pass {
if (cell->type != ID($bmux))
continue;
SigSpec sig_a = cell->getPort(ID::A);
SigSpec sig_a = cell->getPort(TW::A);
if (!sig_a.is_fully_const())
continue;
@ -70,8 +70,8 @@ struct MemoryBmux2RomPass : public Pass {
mem.inits.push_back(std::move(init));
MemRd rd;
rd.addr = cell->getPort(ID::S);
rd.data = cell->getPort(ID::Y);
rd.addr = cell->getPort(TW::S);
rd.data = cell->getPort(TW::Y);
rd.init_value = Const(State::Sx, width);
rd.arst_value = Const(State::Sx, width);
rd.srst_value = Const(State::Sx, width);

6
passes/memory/memory_bram.cc
View File

@ -903,7 +903,7 @@ grow_read_ports:;
// Swizzle read ports.
for (auto &port : mem.rd_ports) {
SigSpec new_data = module->addWire(NEW_ID, mem.width);
SigSpec new_data = module->addWire(NEW_TWINE, mem.width);
Const new_init_value = Const(State::Sx, mem.width);
Const new_arst_value = Const(State::Sx, mem.width);
Const new_srst_value = Const(State::Sx, mem.width);
@ -1023,12 +1023,12 @@ grow_read_ports:;
auto &port = mem.rd_ports[pi.mapped_port];
SigSpec sig_data = port.data.extract(grid_d * bram.dbits, bram.dbits);
SigSpec bram_dout = module->addWire(NEW_ID, bram.dbits);
SigSpec bram_dout = module->addWire(NEW_TWINE, bram.dbits);
c->setPort(stringf("\\%sDATA", pf), bram_dout);
SigSpec addr_ok_q = addr_ok;
if (port.clk_enable && !addr_ok.empty()) {
addr_ok_q = module->addWire(NEW_ID);
addr_ok_q = module->addWire(NEW_TWINE);
module->addDffe(NEW_ID, port.clk, port.en, addr_ok, addr_ok_q, port.clk_polarity);
}

10
passes/memory/memory_dff.cc
View File

@ -177,7 +177,7 @@ struct MemQueryCache
if (!driver.cell->type.in(ID($mux), ID($pmux)))
return false;
log_assert(driver.port == ID::Y);
SigSpec sig_s = driver.cell->getPort(ID::S);
SigSpec sig_s = driver.cell->getPort(TW::S);
int sel_sat = qcsat.importSigBit(sel);
if (neg_sel)
sel_sat = qcsat.ez->NOT(sel_sat);
@ -187,14 +187,14 @@ struct MemQueryCache
int sbit = qcsat.importSigBit(sig_s[i]);
qcsat.prepare();
if (!qcsat.ez->solve(port_ren, sel_sat, qcsat.ez->NOT(sbit))) {
bit = driver.cell->getPort(ID::B)[i * width + driver.offset];
bit = driver.cell->getPort(TW::B)[i * width + driver.offset];
return true;
}
if (qcsat.ez->solve(port_ren, sel_sat, sbit))
all_0 = false;
}
if (all_0) {
bit = driver.cell->getPort(ID::A)[driver.offset];
bit = driver.cell->getPort(TW::A)[driver.offset];
return true;
}
return false;
@ -264,7 +264,7 @@ struct MemoryDffWorker
} else {
continue;
}
SigSpec y = consumer.cell->getPort(ID::Y);
SigSpec y = consumer.cell->getPort(TW::Y);
int mux_width = GetSize(y);
SigBit ybit = y.extract(consumer.offset);
if (prev_cell != consumer.cell || prev_idx+1 != i || prev_is_b != is_b) {
@ -272,7 +272,7 @@ struct MemoryDffWorker
md.base_idx = i;
md.size = 0;
md.is_b = is_b;
md.sig_s = consumer.cell->getPort(ID::S);
md.sig_s = consumer.cell->getPort(TW::S);
md.sig_other.resize(GetSize(md.sig_s));
prev_cell = consumer.cell;
prev_is_b = is_b;

16
passes/memory/memory_libmap.cc
View File

@ -142,13 +142,13 @@ struct MapWorker {
{
if (cell->type == ID($mux))
{
RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(ID::A));
RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(ID::B));
RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(TW::A));
RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(TW::B));
if (sig_a.is_fully_undef())
sigmap_xmux.add(cell->getPort(ID::Y), sig_b);
sigmap_xmux.add(cell->getPort(TW::Y), sig_b);
else if (sig_b.is_fully_undef())
sigmap_xmux.add(cell->getPort(ID::Y), sig_a);
sigmap_xmux.add(cell->getPort(TW::Y), sig_a);
}
}
}
@ -1665,14 +1665,14 @@ std::vector<SigSpec> generate_mux(Mem &mem, int rpidx, const Swizzle &swz) {
return {port.data};
}
if (port.clk_enable) {
SigSpec new_sig_s = mem.module->addWire(NEW_ID, GetSize(sig_s));
SigSpec new_sig_s = mem.module->addWire(NEW_TWINE, GetSize(sig_s));
mem.module->addDffe(NEW_ID, port.clk, port.en, sig_s, new_sig_s, port.clk_polarity);
sig_s = new_sig_s;
}
SigSpec sig_a = Const(State::Sx, GetSize(port.data) << hi_bits << GetSize(swz.addr_mux_bits));
for (int i = 0; i < ((swz.addr_end - swz.addr_start) >> swz.addr_shift); i++) {
for (int j = 0; j < (1 << GetSize(swz.addr_mux_bits)); j++) {
SigSpec sig = mem.module->addWire(NEW_ID, GetSize(port.data));
SigSpec sig = mem.module->addWire(NEW_TWINE, GetSize(port.data));
int hi = ((swz.addr_start >> swz.addr_shift) + i) & ((1 << hi_bits) - 1);
int pos = (hi << GetSize(swz.addr_mux_bits) | j) * GetSize(port.data);
for (int k = 0; k < GetSize(port.data); k++)
@ -1948,7 +1948,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, cons
cell->setParam(stringf("\\PORT_%s_RD_SRST_VALUE", name), hw_val);
}
}
SigSpec hw_rdata = mem.module->addWire(NEW_ID, width);
SigSpec hw_rdata = mem.module->addWire(NEW_TWINE, width);
cell->setPort(stringf("\\PORT_%s_RD_DATA", name), hw_rdata);
SigSpec lhs;
SigSpec rhs;
@ -1983,7 +1983,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, cons
else if (pdef.rdsrstval == ResetValKind::NoUndef)
cell->setParam(stringf("\\PORT_%s_RD_SRST_VALUE", name), Const(State::S0, width));
}
SigSpec hw_rdata = mem.module->addWire(NEW_ID, width);
SigSpec hw_rdata = mem.module->addWire(NEW_TWINE, width);
cell->setPort(stringf("\\PORT_%s_RD_DATA", name), hw_rdata);
}
}

34
passes/memory/memory_map.cc
View File

@ -241,7 +241,7 @@ struct MemoryMapWorker
} else {
c = module->addCell(ff_id, ID($dff));
c->parameters[ID::CLK_POLARITY] = RTLIL::Const(RTLIL::State::S1);
c->setPort(ID::CLK, RTLIL::SigSpec(RTLIL::State::S0));
c->setPort(TW::CLK, RTLIL::SigSpec(RTLIL::State::S0));
}
} else if (async_wr) {
log_assert(formal); // General async write not implemented yet, checked against above
@ -249,14 +249,14 @@ struct MemoryMapWorker
} else {
c = module->addCell(ff_id, ID($dff));
c->parameters[ID::CLK_POLARITY] = RTLIL::Const(refclock_pol);
c->setPort(ID::CLK, refclock);
c->setPort(TW::CLK, refclock);
}
c->set_src_attribute(mem_src);
c->parameters[ID::WIDTH] = mem.width;
RTLIL::Wire *w_in = module->addWire(genid(mem.memid, "", addr, "$d"), mem.width);
data_reg_in[idx] = w_in;
c->setPort(ID::D, w_in);
c->setPort(TW::D, w_in);
std::string w_out_name = stringf("%s[%d]", mem.memid, addr);
if (module->wire(RTLIL::IdString(w_out_name)) != nullptr)
@ -276,7 +276,7 @@ struct MemoryMapWorker
w_out->attributes[ID::init] = w_init.as_const();
data_reg_out[idx] = w_out;
c->setPort(ID::Q, w_out);
c->setPort(TW::Q, w_out);
if (static_only)
module->connect(RTLIL::SigSig(w_in, w_out));
@ -308,15 +308,15 @@ struct MemoryMapWorker
RTLIL::Cell *c = module->addCell(genid(mem.memid, "$rdmux", i, "", j, "", k), ID($mux));
c->set_src_attribute(mem_src);
c->parameters[ID::WIDTH] = GetSize(port.data);
c->setPort(ID::Y, rd_signals[k]);
c->setPort(ID::S, rd_addr.extract(abits-j-1, 1));
c->setPort(TW::Y, rd_signals[k]);
c->setPort(TW::S, rd_addr.extract(abits-j-1, 1));
count_mux++;
c->setPort(ID::A, module->addWire(genid(mem.memid, "$rdmux", i, "", j, "", k, "$a"), GetSize(port.data)));
c->setPort(ID::B, module->addWire(genid(mem.memid, "$rdmux", i, "", j, "", k, "$b"), GetSize(port.data)));
c->setPort(TW::A, module->addWire(genid(mem.memid, "$rdmux", i, "", j, "", k, "$a"), GetSize(port.data)));
c->setPort(TW::B, module->addWire(genid(mem.memid, "$rdmux", i, "", j, "", k, "$b"), GetSize(port.data)));
next_rd_signals.push_back(c->getPort(ID::A));
next_rd_signals.push_back(c->getPort(ID::B));
next_rd_signals.push_back(c->getPort(TW::A));
next_rd_signals.push_back(c->getPort(TW::B));
}
next_rd_signals.swap(rd_signals);
@ -372,22 +372,22 @@ struct MemoryMapWorker
c->parameters[ID::A_WIDTH] = RTLIL::Const(1);
c->parameters[ID::B_WIDTH] = RTLIL::Const(1);
c->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
c->setPort(ID::A, w);
c->setPort(ID::B, wr_bit);
c->setPort(TW::A, w);
c->setPort(TW::B, wr_bit);
w = module->addWire(genid(mem.memid, "$wren", addr, "", j, "", wr_offset, "$y"));
c->setPort(ID::Y, RTLIL::SigSpec(w));
c->setPort(TW::Y, RTLIL::SigSpec(w));
}
RTLIL::Cell *c = module->addCell(genid(mem.memid, "$wrmux", addr, "", j, "", wr_offset), ID($mux));
c->set_src_attribute(mem_src);
c->parameters[ID::WIDTH] = wr_width;
c->setPort(ID::A, sig.extract(wr_offset, wr_width));
c->setPort(ID::B, port.data.extract(wr_offset + sub * mem.width, wr_width));
c->setPort(ID::S, RTLIL::SigSpec(w));
c->setPort(TW::A, sig.extract(wr_offset, wr_width));
c->setPort(TW::B, port.data.extract(wr_offset + sub * mem.width, wr_width));
c->setPort(TW::S, RTLIL::SigSpec(w));
w = module->addWire(genid(mem.memid, "$wrmux", addr, "", j, "", wr_offset, "$y"), wr_width);
c->setPort(ID::Y, w);
c->setPort(TW::Y, w);
sig.replace(wr_offset, w);
wr_offset += wr_width;

2
passes/memory/memory_memx.cc
View File

@ -63,7 +63,7 @@ struct MemoryMemxPass : public Pass {
module, mem.memid.unescape());
SigSpec addr_ok = make_addr_check(mem, port.addr);
Wire *raw_rdata = module->addWire(NEW_ID, GetSize(port.data));
Wire *raw_rdata = module->addWire(NEW_TWINE, GetSize(port.data));
module->addMux(NEW_ID, SigSpec(State::Sx, GetSize(port.data)), raw_rdata, addr_ok, port.data);
port.data = raw_rdata;
}

12
passes/memory/memory_share.cc
View File

@ -164,7 +164,7 @@ struct MemoryShareWorker
port2.addr = addr2;
mem.prepare_rd_merge(i, j, &initvals);
mem.widen_prep(wide_log2);
SigSpec new_data = module->addWire(NEW_ID, mem.width << wide_log2);
SigSpec new_data = module->addWire(NEW_TWINE, mem.width << wide_log2);
module->connect(port1.data, new_data.extract(sub1 * mem.width, mem.width << port1.wide_log2));
module->connect(port2.data, new_data.extract(sub2 * mem.width, mem.width << port2.wide_log2));
for (int k = 0; k < wide_log2; k++)
@ -438,7 +438,7 @@ struct MemoryShareWorker
std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups_en;
RTLIL::SigSpec grouped_last_en, grouped_this_en, en;
RTLIL::Wire *grouped_en = module->addWire(NEW_ID, 0);
RTLIL::Wire *grouped_en = module->addWire(NEW_TWINE, 0);
for (int j = 0; j < int(this_en.size()); j++) {
std::pair<RTLIL::SigBit, RTLIL::SigBit> key(last_en[j], this_en[j]);
@ -484,13 +484,13 @@ struct MemoryShareWorker
{
if (cell->type == ID($mux))
{
RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(ID::A));
RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(ID::B));
RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(TW::A));
RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(TW::B));
if (sig_a.is_fully_undef())
sigmap_xmux.add(cell->getPort(ID::Y), sig_b);
sigmap_xmux.add(cell->getPort(TW::Y), sig_b);
else if (sig_b.is_fully_undef())
sigmap_xmux.add(cell->getPort(ID::Y), sig_a);
sigmap_xmux.add(cell->getPort(TW::Y), sig_a);
}
}

50
passes/opt/muxpack.cc
View File

@ -38,11 +38,11 @@ struct ExclusiveDatabase
pool<Cell*> reduce_or;
for (auto cell : module->cells()) {
if (cell->type == ID($eq)) {
SigSpec y_sig = sigmap(cell->getPort(ID::Y));
SigSpec y_sig = sigmap(cell->getPort(TW::Y));
if (GetSize(y_sig) == 0)
continue;
nonconst_sig = sigmap(cell->getPort(ID::A));
const_sig = sigmap(cell->getPort(ID::B));
nonconst_sig = sigmap(cell->getPort(TW::A));
const_sig = sigmap(cell->getPort(TW::B));
if (!const_sig.is_fully_const()) {
if (!nonconst_sig.is_fully_const())
continue;
@ -51,10 +51,10 @@ struct ExclusiveDatabase
y_port = y_sig[0];
}
else if (cell->type == ID($logic_not)) {
SigSpec y_sig = sigmap(cell->getPort(ID::Y));
SigSpec y_sig = sigmap(cell->getPort(TW::Y));
if (GetSize(y_sig) == 0)
continue;
nonconst_sig = sigmap(cell->getPort(ID::A));
nonconst_sig = sigmap(cell->getPort(TW::A));
const_sig = Const(State::S0, GetSize(nonconst_sig));
y_port = y_sig[0];
}
@ -72,7 +72,7 @@ struct ExclusiveDatabase
for (auto cell : reduce_or) {
nonconst_sig = SigSpec();
std::vector<Const> values;
SigSpec a_port = sigmap(cell->getPort(ID::A));
SigSpec a_port = sigmap(cell->getPort(TW::A));
for (auto bit : a_port) {
auto it = sig_cmp_prev.find(bit);
if (it == sig_cmp_prev.end()) {
@ -90,7 +90,7 @@ struct ExclusiveDatabase
}
if (nonconst_sig.empty())
continue;
SigSpec y_sig = sigmap(cell->getPort(ID::Y));
SigSpec y_sig = sigmap(cell->getPort(TW::Y));
if (GetSize(y_sig) == 0)
continue;
y_port = y_sig[0];
@ -154,11 +154,11 @@ struct MuxpackWorker
{
if (cell->type.in(ID($mux), ID($pmux)) && !cell->get_bool_attribute(ID::keep))
{
SigSpec a_sig = sigmap(cell->getPort(ID::A));
SigSpec a_sig = sigmap(cell->getPort(TW::A));
SigSpec b_sig;
if (cell->type == ID($mux))
b_sig = sigmap(cell->getPort(ID::B));
SigSpec y_sig = sigmap(cell->getPort(ID::Y));
b_sig = sigmap(cell->getPort(TW::B));
SigSpec y_sig = sigmap(cell->getPort(TW::Y));
if (sig_chain_next.count(a_sig))
for (auto a_bit : a_sig)
@ -195,9 +195,9 @@ struct MuxpackWorker
{
log_debug("Considering %s (%s)\n", cell, cell->type.unescape());
SigSpec a_sig = sigmap(cell->getPort(ID::A));
SigSpec a_sig = sigmap(cell->getPort(TW::A));
if (cell->type == ID($mux)) {
SigSpec b_sig = sigmap(cell->getPort(ID::B));
SigSpec b_sig = sigmap(cell->getPort(TW::B));
if (sig_chain_prev.count(a_sig) + sig_chain_prev.count(b_sig) != 1)
goto start_cell;
@ -217,8 +217,8 @@ struct MuxpackWorker
{
Cell *prev_cell = sig_chain_prev.at(a_sig);
log_assert(prev_cell);
SigSpec s_sig = sigmap(cell->getPort(ID::S));
s_sig.append(sigmap(prev_cell->getPort(ID::S)));
SigSpec s_sig = sigmap(cell->getPort(TW::S));
s_sig.append(sigmap(prev_cell->getPort(TW::S)));
if (!excl_db.query(s_sig))
goto start_cell;
}
@ -239,7 +239,7 @@ struct MuxpackWorker
{
chain.push_back(c);
SigSpec y_sig = sigmap(c->getPort(ID::Y));
SigSpec y_sig = sigmap(c->getPort(TW::Y));
if (sig_chain_next.count(y_sig) == 0)
break;
@ -278,28 +278,28 @@ struct MuxpackWorker
pmux_count += 1;
first_cell->type = ID($pmux);
SigSpec b_sig = first_cell->getPort(ID::B);
SigSpec s_sig = first_cell->getPort(ID::S);
SigSpec b_sig = first_cell->getPort(TW::B);
SigSpec s_sig = first_cell->getPort(TW::S);
for (int i = 1; i < cases; i++) {
Cell* prev_cell = chain[cursor+i-1];
Cell* cursor_cell = chain[cursor+i];
if (sigmap(prev_cell->getPort(ID::Y)) == sigmap(cursor_cell->getPort(ID::A))) {
b_sig.append(cursor_cell->getPort(ID::B));
s_sig.append(cursor_cell->getPort(ID::S));
if (sigmap(prev_cell->getPort(TW::Y)) == sigmap(cursor_cell->getPort(TW::A))) {
b_sig.append(cursor_cell->getPort(TW::B));
s_sig.append(cursor_cell->getPort(TW::S));
}
else {
log_assert(cursor_cell->type == ID($mux));
b_sig.append(cursor_cell->getPort(ID::A));
s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort(ID::S)));
b_sig.append(cursor_cell->getPort(TW::A));
s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort(TW::S)));
}
remove_cells.insert(cursor_cell);
}
first_cell->setPort(ID::B, b_sig);
first_cell->setPort(ID::S, s_sig);
first_cell->setPort(TW::B, b_sig);
first_cell->setPort(TW::S, s_sig);
first_cell->setParam(ID::S_WIDTH, GetSize(s_sig));
first_cell->setPort(ID::Y, last_cell->getPort(ID::Y));
first_cell->setPort(TW::Y, last_cell->getPort(TW::Y));
cursor += cases;
}

26
passes/opt/opt_balance_tree.cc
View File

@ -77,7 +77,7 @@ struct OptBalanceTreeWorker {
// Base case: if we have two sources, create a single cell
if (sources.size() == 2) {
// Create a new cell of the same type
Cell* new_cell = module->addCell(NEW_ID, cell_type);
Cell* new_cell = module->addCell(NEW_TWINE, cell_type);
// Copy attributes from reference cell
new_cell->attributes = cell->attributes;
@ -88,12 +88,12 @@ struct OptBalanceTreeWorker {
out_width = max(sources[0].size(), sources[1].size()) + 1;
else if (cell_type == ID($mul))
out_width = sources[0].size() + sources[1].size();
Wire* out_wire = module->addWire(NEW_ID, out_width);
Wire* out_wire = module->addWire(NEW_TWINE, out_width);
// Connect ports and fix up parameters
new_cell->setPort(ID::A, sources[0]);
new_cell->setPort(ID::B, sources[1]);
new_cell->setPort(ID::Y, out_wire);
new_cell->setPort(TW::A, sources[0]);
new_cell->setPort(TW::B, sources[1]);
new_cell->setPort(TW::Y, out_wire);
new_cell->fixup_parameters();
new_cell->setParam(ID::A_SIGNED, cell->getParam(ID::A_SIGNED));
new_cell->setParam(ID::B_SIGNED, cell->getParam(ID::B_SIGNED));
@ -112,7 +112,7 @@ struct OptBalanceTreeWorker {
SigSpec right_tree = create_balanced_tree(right_sources, cell_type, cell);
// Create a cell to combine the two subtrees
Cell* new_cell = module->addCell(NEW_ID, cell_type);
Cell* new_cell = module->addCell(NEW_TWINE, cell_type);
// Copy attributes from reference cell
new_cell->attributes = cell->attributes;
@ -123,12 +123,12 @@ struct OptBalanceTreeWorker {
out_width = max(left_tree.size(), right_tree.size()) + 1;
else if (cell_type == ID($mul))
out_width = left_tree.size() + right_tree.size();
Wire* out_wire = module->addWire(NEW_ID, out_width);
Wire* out_wire = module->addWire(NEW_TWINE, out_width);
// Connect ports and fix up parameters
new_cell->setPort(ID::A, left_tree);
new_cell->setPort(ID::B, right_tree);
new_cell->setPort(ID::Y, out_wire);
new_cell->setPort(TW::A, left_tree);
new_cell->setPort(TW::B, right_tree);
new_cell->setPort(TW::Y, out_wire);
new_cell->fixup_parameters();
new_cell->setParam(ID::A_SIGNED, cell->getParam(ID::A_SIGNED));
new_cell->setParam(ID::B_SIGNED, cell->getParam(ID::B_SIGNED));
@ -185,7 +185,7 @@ struct OptBalanceTreeWorker {
// BFS, following all chains until they hit a cell of a different type
// Pick the longest one
auto y = sigmap(cell->getPort(ID::Y));
auto y = sigmap(cell->getPort(TW::Y));
pool<Cell*> sinks;
pool<Cell*> current_loads = sig_to_sink[y];
pool<Cell*> next_loads;
@ -202,7 +202,7 @@ struct OptBalanceTreeWorker {
continue;
}
auto xy = sigmap(x->getPort(ID::Y));
auto xy = sigmap(x->getPort(TW::Y));
// If this signal drives a port, add it to the sinks
// (even though it may not be the end of a chain)
@ -300,7 +300,7 @@ struct OptBalanceTreeWorker {
SigSpec tree_output = create_balanced_tree(source_signals, cell_type, head_cell);
// Connect the tree output to the head cell's output
SigSpec head_output = sigmap(head_cell->getPort(ID::Y));
SigSpec head_output = sigmap(head_cell->getPort(TW::Y));
int connect_width = std::min(head_output.size(), tree_output.size());
module->connect(head_output.extract(0, connect_width), tree_output.extract(0, connect_width));
if (head_output.size() > tree_output.size()) {

6
passes/opt/opt_clean/cells_all.cc
View File

@ -202,7 +202,7 @@ ConflictLogs explore(CellAnalysis& analysis, CellTraversal& traversal, const Sig
if (bit.wire == nullptr && clean_ctx.ct_all.cell_known(cell->type)) {
std::string msg = stringf("Driver-driver conflict "
"for %s between cell %s.%s and constant %s in %s: Resolved using constant.",
log_signal(raw_bit), cell->name.unescape(), it2.first.unescape(), log_signal(bit), actx.mod->name.unescape());
log_signal(raw_bit), cell->name.unescape(), actx.mod->design->twines.str(it2.first), log_signal(bit), actx.mod->name);
logs.logs.insert(ctx, {wire_map(raw_bit), msg});
}
if (bit.wire != nullptr)
@ -304,7 +304,7 @@ pool<Cell*> all_unused_cells(const Module *mod, const CellAnalysis& analysis, Wi
});
for (int cell_index : sharded_unused_cells)
unused_cells.insert(mod->cell_at(cell_index));
unused_cells.sort(RTLIL::sort_by_name_id<RTLIL::Cell>());
unused_cells.sort(RTLIL::sort_by_name<RTLIL::Cell>());
return unused_cells;
}
@ -314,7 +314,7 @@ void remove_cells(RTLIL::Module* mod, FfInitVals& ffinit, const pool<Cell*>& cel
log_debug(" removing unused `%s' cell `%s'.\n", cell->type, cell->name);
mod->design->scratchpad_set_bool("opt.did_something", true);
if (cell->is_builtin_ff())
ffinit.remove_init(cell->getPort(ID::Q));
ffinit.remove_init(cell->getPort(TW::Q));
mod->remove(cell);
stats.count_rm_cells++;
}

18
passes/opt/opt_clean/cells_temp.cc
View File

@ -27,8 +27,8 @@ bool is_signed(RTLIL::Cell* cell) {
}
bool trim_buf(RTLIL::Cell* cell, ShardedVector<RTLIL::SigSig>& new_connections, const ParallelDispatchThreadPool::RunCtx &ctx) {
RTLIL::SigSpec a = cell->getPort(ID::A);
RTLIL::SigSpec y = cell->getPort(ID::Y);
RTLIL::SigSpec a = cell->getPort(TW::A);
RTLIL::SigSpec y = cell->getPort(TW::Y);
a.extend_u0(GetSize(y), is_signed(cell));
if (a.has_const(State::Sz)) {
@ -58,20 +58,20 @@ bool remove(ShardedVector<RTLIL::Cell*>& cells, RTLIL::Module* mod, bool verbose
if (verbose) {
if (cell->type == ID($connect)) {
log_debug(" removing connect cell `%s': %s <-> %s\n", cell->name,
log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::B)));
log_signal(cell->getPort(TW::A)), log_signal(cell->getPort(TW::B)));
} else if (cell->type == ID($input_port)) {
log_debug(" removing input port marker cell `%s': %s\n", cell->name,
log_signal(cell->getPort(ID::Y)));
log_signal(cell->getPort(TW::Y)));
} else if (cell->type == ID($output_port)) {
log_debug(" removing output port marker cell `%s': %s\n", cell->name,
log_signal(cell->getPort(ID::A)));
log_signal(cell->getPort(TW::A)));
} else if (cell->type == ID($public)) {
log_debug(" removing public wire marker cell `%s': %s\n", cell->name,
log_signal(cell->getPort(ID::A)));
log_signal(cell->getPort(TW::A)));
} else {
did_something = true;
log_debug(" removing buffer cell `%s': %s = %s\n", cell->name,
log_signal(cell->getPort(ID::Y)), log_signal(cell->getPort(ID::A)));
log_signal(cell->getPort(TW::Y)), log_signal(cell->getPort(TW::A)));
}
}
mod->remove(cell);
@ -93,8 +93,8 @@ void remove_temporary_cells(RTLIL::Module *module, ParallelDispatchThreadPool::S
if (trim_buf(cell, new_connections, ctx))
delcells.insert(ctx, cell);
} else if (cell->type.in(ID($connect)) && !cell->has_keep_attr()) {
RTLIL::SigSpec a = cell->getPort(ID::A);
RTLIL::SigSpec b = cell->getPort(ID::B);
RTLIL::SigSpec a = cell->getPort(TW::A);
RTLIL::SigSpec b = cell->getPort(TW::B);
if (a.has_const() && !b.has_const())
std::swap(a, b);
new_connections.insert(ctx, {a, b});

4
passes/opt/opt_clean/inits.cc
View File

@ -27,9 +27,9 @@ ShardedVector<std::pair<SigBit, State>> build_inits(AnalysisContext& actx) {
actx.subpool.run([&results, &actx](const ParallelDispatchThreadPool::RunCtx &ctx) {
for (int i : ctx.item_range(actx.mod->cells_size())) {
RTLIL::Cell *cell = actx.mod->cell_at(i);
if (StaticCellTypes::Compat::internals_mem_ff(cell->type) && cell->hasPort(ID::Q))
if (StaticCellTypes::Compat::internals_mem_ff(cell->type) && cell->hasPort(TW::Q))
{
SigSpec sig = cell->getPort(ID::Q);
SigSpec sig = cell->getPort(TW::Q);
for (int i = 0; i < GetSize(sig); i++)
{

4
passes/opt/opt_clean/wires.cc
View File

@ -178,7 +178,7 @@ bool check_all(const ShardedSigPool &sigs, const RTLIL::SigSpec &spec) {
struct UpdateConnection {
RTLIL::Cell *cell;
RTLIL::IdString port;
TwineRef port;
RTLIL::SigSpec spec;
};
void fixup_cell_ports(ShardedVector<UpdateConnection> &update_connections)
@ -256,7 +256,7 @@ struct SigConnKinds {
// see commit message e36c71b5
bool clk2fflogic = cell->get_bool_attribute(ID::clk2fflogic);
for (auto &[port, sig] : cell->connections())
if (clk2fflogic ? port == ID::D : clean_ctx.ct_all.cell_output(cell->type, port))
if (clk2fflogic ? port == TW::D : clean_ctx.ct_all.cell_output(cell->type, port))
add_spec(raw_register_builder, ctx, sig);
}
for (auto &[_, sig] : cell->connections())

14
passes/opt/opt_demorgan.cc
View File

@ -38,7 +38,7 @@ void demorgan_worker(
if( (cell->type != ID($reduce_and)) && (cell->type != ID($reduce_or)) )
return;
auto insig = sigmap(cell->getPort(ID::A));
auto insig = sigmap(cell->getPort(TW::A));
if (GetSize(insig) < 1)
return;
@ -99,7 +99,7 @@ void demorgan_worker(
//We are NOT inverted! Add an inverter
if(!srcinv)
{
auto inverted_b = m->addWire(NEW_ID);
auto inverted_b = m->addWire(NEW_TWINE);
m->addNot(NEW_ID, RTLIL::SigSpec(b), RTLIL::SigSpec(inverted_b));
insig[i] = inverted_b;
}
@ -107,7 +107,7 @@ void demorgan_worker(
//We ARE inverted - bypass it
//Don't automatically delete the inverter since other stuff might still use it
else
insig[i] = srcinv->getPort(ID::A);
insig[i] = srcinv->getPort(TW::A);
}
//Cosmetic fixup: If our input is just a scrambled version of one bus, rearrange it
@ -155,7 +155,7 @@ void demorgan_worker(
}
//Push the new input signal back to the reduction (after bypassing/adding inverters)
cell->setPort(ID::A, insig);
cell->setPort(TW::A, insig);
//Change the cell type
if(cell->type == ID($reduce_and))
@ -165,10 +165,10 @@ void demorgan_worker(
//don't change XOR
//Add an inverter to the output
auto inverted_output = cell->getPort(ID::Y);
auto uninverted_output = m->addWire(NEW_ID);
auto inverted_output = cell->getPort(TW::Y);
auto uninverted_output = m->addWire(NEW_TWINE);
m->addNot(NEW_ID, RTLIL::SigSpec(uninverted_output), inverted_output);
cell->setPort(ID::Y, uninverted_output);
cell->setPort(TW::Y, uninverted_output);
}
struct OptDemorganPass : public Pass {

86
passes/opt/opt_dff.cc
View File

@ -77,29 +77,29 @@ struct OptDffWorker
SigSpec create_not(SigSpec a, bool is_fine) {
if (is_fine)
return module->NotGate(NEW_ID, a);
return module->NotGate(NEW_TWINE, a);
else
return module->Not(NEW_ID, a);
return module->Not(NEW_TWINE, a);
}
SigSpec create_and(SigSpec a, SigSpec b, bool is_fine) {
if (is_fine)
return module->AndGate(NEW_ID, a, b);
return module->AndGate(NEW_TWINE, a, b);
else
return module->And(NEW_ID, a, b);
return module->And(NEW_TWINE, a, b);
}
void create_mux_to_output(SigSpec a, SigSpec b, SigSpec sel, SigSpec y, bool pol, bool is_fine) {
if (is_fine) {
if (pol)
module->addMuxGate(NEW_ID, a, b, sel, y);
module->addMuxGate(NEW_TWINE, a, b, sel, y);
else
module->addMuxGate(NEW_ID, b, a, sel, y);
module->addMuxGate(NEW_TWINE, b, a, sel, y);
} else {
if (pol)
module->addMux(NEW_ID, a, b, sel, y);
module->addMux(NEW_TWINE, a, b, sel, y);
else
module->addMux(NEW_ID, b, a, sel, y);
module->addMux(NEW_TWINE, b, a, sel, y);
}
}
@ -124,7 +124,7 @@ struct OptDffWorker
for (auto cell : module->cells()) {
if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_))) {
RTLIL::SigSpec sig_y = sigmap(cell->getPort(ID::Y));
RTLIL::SigSpec sig_y = sigmap(cell->getPort(TW::Y));
for (int i = 0; i < GetSize(sig_y); i++)
bit2mux[sig_y[i]] = cell_int_t(cell, i);
}
@ -163,9 +163,9 @@ struct OptDffWorker
return ret; // D not driven by MUX / MUX drives multiple loads
cell_int_t mbit = bit2mux.at(d);
RTLIL::SigSpec sig_a = sigmap(mbit.first->getPort(ID::A));
RTLIL::SigSpec sig_b = sigmap(mbit.first->getPort(ID::B));
RTLIL::SigSpec sig_s = sigmap(mbit.first->getPort(ID::S));
RTLIL::SigSpec sig_a = sigmap(mbit.first->getPort(TW::A));
RTLIL::SigSpec sig_b = sigmap(mbit.first->getPort(TW::B));
RTLIL::SigSpec sig_s = sigmap(mbit.first->getPort(TW::S));
int width = GetSize(sig_a), index = mbit.second;
// Traverse MUX tree
@ -173,9 +173,9 @@ struct OptDffWorker
if (path.count(sig_s[i]) && path.at(sig_s[i])) {
ret = find_muxtree_feedback_patterns(sig_b[i*width + index], q, path);
if (sig_b[i*width + index] == q) {
RTLIL::SigSpec s = sigmap(mbit.first->getPort(ID::B));
RTLIL::SigSpec s = sigmap(mbit.first->getPort(TW::B));
s[i*width + index] = RTLIL::Sx;
mbit.first->setPort(ID::B, s);
mbit.first->setPort(TW::B, s);
}
return ret;
@ -197,9 +197,9 @@ struct OptDffWorker
ret.insert(pat);
if (sig_b[i*width + index] == q) {
RTLIL::SigSpec s = sigmap(mbit.first->getPort(ID::B));
RTLIL::SigSpec s = sigmap(mbit.first->getPort(TW::B));
s[i*width + index] = RTLIL::Sx;
mbit.first->setPort(ID::B, s);
mbit.first->setPort(TW::B, s);
}
}
@ -208,9 +208,9 @@ struct OptDffWorker
ret.insert(pat);
if (sig_a[index] == q) {
RTLIL::SigSpec s = sigmap(mbit.first->getPort(ID::A));
RTLIL::SigSpec s = sigmap(mbit.first->getPort(TW::A));
s[index] = RTLIL::Sx;
mbit.first->setPort(ID::A, s);
mbit.first->setPort(TW::A, s);
}
return ret;
@ -232,8 +232,8 @@ struct OptDffWorker
s2.append(it.second);
}
RTLIL::SigSpec y = module->addWire(NEW_ID);
RTLIL::Cell *c = module->addNe(NEW_ID, s1, s2, y);
RTLIL::SigSpec y = module->addWire(NEW_TWINE);
RTLIL::Cell *c = module->addNe(NEW_TWINE, s1, s2, y);
maybe_simplemap(c, make_gates);
or_input.append(y);
}
@ -249,8 +249,8 @@ struct OptDffWorker
if (GetSize(or_input) == 0) return ctrl_t(State::S1, true);
if (GetSize(or_input) == 1) return ctrl_t(or_input, true);
RTLIL::SigSpec y = module->addWire(NEW_ID);
RTLIL::Cell *c = module->addReduceAnd(NEW_ID, or_input, y);
RTLIL::SigSpec y = module->addWire(NEW_TWINE);
RTLIL::Cell *c = module->addReduceAnd(NEW_TWINE, or_input, y);
maybe_simplemap(c, make_gates);
return ctrl_t(y, true);
}
@ -273,10 +273,10 @@ struct OptDffWorker
or_input.append(create_not(item.first, make_gates));
}
RTLIL::SigSpec y = module->addWire(NEW_ID);
RTLIL::SigSpec y = module->addWire(NEW_TWINE);
RTLIL::Cell *c = final_pol
? module->addReduceOr(NEW_ID, or_input, y)
: module->addReduceAnd(NEW_ID, or_input, y);
? module->addReduceOr(NEW_TWINE, or_input, y)
: module->addReduceAnd(NEW_TWINE, or_input, y);
maybe_simplemap(c, make_gates);
return ctrl_t(y, final_pol);
}
@ -309,9 +309,9 @@ struct OptDffWorker
if (!ff.pol_clr)
module->connect(ff.sig_q[i], ff.sig_clr[i]);
else if (ff.is_fine)
module->addNotGate(NEW_ID, ff.sig_clr[i], ff.sig_q[i]);
module->addNotGate(NEW_TWINE, ff.sig_clr[i], ff.sig_q[i]);
else
module->addNot(NEW_ID, ff.sig_clr[i], ff.sig_q[i]);
module->addNot(NEW_TWINE, ff.sig_clr[i], ff.sig_q[i]);
log("Handling always-active SET at position %d on %s (%s) from module %s (changing to combinatorial circuit).\n",
i, cell, cell->type.unescape(), module);
sr_removed = true;
@ -406,22 +406,22 @@ struct OptDffWorker
SigSpec tmp;
if (ff.is_fine) {
tmp = ff.pol_set
? module->MuxGate(NEW_ID, ff.sig_ad, State::S1, ff.sig_set)
: module->MuxGate(NEW_ID, State::S1, ff.sig_ad, ff.sig_set);
? module->MuxGate(NEW_TWINE, ff.sig_ad, State::S1, ff.sig_set)
: module->MuxGate(NEW_TWINE, State::S1, ff.sig_ad, ff.sig_set);
if (ff.pol_clr)
module->addMuxGate(NEW_ID, tmp, State::S0, ff.sig_clr, ff.sig_q);
module->addMuxGate(NEW_TWINE, tmp, State::S0, ff.sig_clr, ff.sig_q);
else
module->addMuxGate(NEW_ID, State::S0, tmp, ff.sig_clr, ff.sig_q);
module->addMuxGate(NEW_TWINE, State::S0, tmp, ff.sig_clr, ff.sig_q);
} else {
tmp = ff.pol_set
? module->Or(NEW_ID, ff.sig_ad, ff.sig_set)
: module->Or(NEW_ID, ff.sig_ad, module->Not(NEW_ID, ff.sig_set));
? module->Or(NEW_TWINE, ff.sig_ad, ff.sig_set)
: module->Or(NEW_TWINE, ff.sig_ad, module->Not(NEW_TWINE, ff.sig_set));
if (ff.pol_clr)
module->addAnd(NEW_ID, tmp, module->Not(NEW_ID, ff.sig_clr), ff.sig_q);
module->addAnd(NEW_TWINE, tmp, module->Not(NEW_TWINE, ff.sig_clr), ff.sig_q);
else
module->addAnd(NEW_ID, tmp, ff.sig_clr, ff.sig_q);
module->addAnd(NEW_TWINE, tmp, ff.sig_clr, ff.sig_q);
}
} else if (ff.has_arst) {
create_mux_to_output(ff.sig_ad, ff.val_arst, ff.sig_arst, ff.sig_q, ff.pol_arst, ff.is_fine);
@ -566,12 +566,12 @@ struct OptDffWorker
while (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) {
cell_int_t mbit = bit2mux.at(ff.sig_d[i]);
if (GetSize(mbit.first->getPort(ID::S)) != 1)
if (GetSize(mbit.first->getPort(TW::S)) != 1)
break;
SigBit s = sigmap(mbit.first->getPort(ID::S));
SigBit a = sigmap(mbit.first->getPort(ID::A)[mbit.second]);
SigBit b = sigmap(mbit.first->getPort(ID::B)[mbit.second]);
SigBit s = sigmap(mbit.first->getPort(TW::S));
SigBit a = sigmap(mbit.first->getPort(TW::A)[mbit.second]);
SigBit b = sigmap(mbit.first->getPort(TW::B)[mbit.second]);
if ((a == State::S0 || a == State::S1) && (b == State::S0 || b == State::S1))
break;
@ -649,12 +649,12 @@ struct OptDffWorker
while (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) {
cell_int_t mbit = bit2mux.at(ff.sig_d[i]);
if (GetSize(mbit.first->getPort(ID::S)) != 1)
if (GetSize(mbit.first->getPort(TW::S)) != 1)
break;
SigBit s = sigmap(mbit.first->getPort(ID::S));
SigBit a = sigmap(mbit.first->getPort(ID::A)[mbit.second]);
SigBit b = sigmap(mbit.first->getPort(ID::B)[mbit.second]);
SigBit s = sigmap(mbit.first->getPort(TW::S));
SigBit a = sigmap(mbit.first->getPort(TW::A)[mbit.second]);
SigBit b = sigmap(mbit.first->getPort(TW::B)[mbit.second]);
if (a == ff.sig_q[i]) {
enables.insert(ctrl_t(s, true));

74
passes/opt/opt_expr.cc
View File

@ -243,7 +243,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
continue;
int group_size = GetSize(per_kind[kind]);
RTLIL::SigSpec new_y = patcher.addWire(NEW_ID, group_size);
RTLIL::SigSpec new_y = patcher.addWire(NEW_TWINE, group_size);
RTLIL::SigSpec new_a, new_b;
int slot = 0;
@ -295,9 +295,9 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
else if (new_a[j] == State::S0 || new_a[j] == State::S1) {
undef_a.append(new_a[j]);
if (cell->type == ID($xor))
undef_b.append(new_a[j] == State::S1 ? patcher.Not(NEW_ID, new_b[j]).as_bit() : new_b[j]);
undef_b.append(new_a[j] == State::S1 ? patcher.Not(NEW_TWINE, new_b[j]).as_bit() : new_b[j]);
else if (cell->type == ID($xnor))
undef_b.append(new_a[j] == State::S1 ? new_b[j] : patcher.Not(NEW_ID, new_b[j]).as_bit());
undef_b.append(new_a[j] == State::S1 ? new_b[j] : patcher.Not(NEW_TWINE, new_b[j]).as_bit());
else log_abort();
undef_y.append(new_y[j]);
}
@ -324,7 +324,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
new_y = std::move(def_y);
}
RTLIL::Cell *c = patcher.addCell(NEW_ID, cell->type);
RTLIL::Cell *c = patcher.addCell(NEW_TWINE, cell->type);
c->setPort(TW::A, new_a);
c->parameters[ID::A_WIDTH] = new_a.size();
@ -687,7 +687,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
sig_y.append(RTLIL::Const(State::S0, width-1));
patcher.patch(cell, TW::Y, sig_y, "xor_buffer");
} else {
SigSpec sig_y = is_gate ? (SigSpec)patcher.NotGate(NEW_ID, sig_a) : patcher.Not(NEW_ID, sig_a);
SigSpec sig_y = is_gate ? (SigSpec)patcher.NotGate(NEW_TWINE, sig_a) : patcher.Not(NEW_TWINE, sig_a);
sig_y.append(RTLIL::Const(State::S0, width-1));
patcher.patch(cell, TW::Y, sig_y, "xor_buffer");
}
@ -699,7 +699,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
sig_y.append(RTLIL::Const(State::S1, width-1));
patcher.patch(cell, TW::Y, sig_y, "xnor_buffer");
} else {
SigSpec sig_y = is_gate ? (SigSpec)patcher.NotGate(NEW_ID, sig_a) : patcher.Not(NEW_ID, sig_a);
SigSpec sig_y = is_gate ? (SigSpec)patcher.NotGate(NEW_TWINE, sig_a) : patcher.Not(NEW_TWINE, sig_a);
sig_y.append(RTLIL::Const(State::S1, width-1));
patcher.patch(cell, TW::Y, sig_y, "xnor_buffer");
}
@ -771,7 +771,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (!b_group_1.empty()) y_new_1 = b_group_1;
if (!b_group_x.empty()) {
if (keepdc)
y_new_x = patcher.And(NEW_ID, Const(State::Sx, GetSize(b_group_x)), b_group_x);
y_new_x = patcher.And(NEW_TWINE, Const(State::Sx, GetSize(b_group_x)), b_group_x);
else
y_new_x = Const(State::S0, GetSize(b_group_x));
}
@ -780,16 +780,16 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (!b_group_1.empty()) y_new_1 = Const(State::S1, GetSize(b_group_1));
if (!b_group_x.empty()) {
if (keepdc)
y_new_x = patcher.Or(NEW_ID, Const(State::Sx, GetSize(b_group_x)), b_group_x);
y_new_x = patcher.Or(NEW_TWINE, Const(State::Sx, GetSize(b_group_x)), b_group_x);
else
y_new_x = Const(State::S1, GetSize(b_group_x));
}
} else if (cell->type.in(ID($xor), ID($xnor))) {
if (!b_group_0.empty()) y_new_0 = b_group_0;
if (!b_group_1.empty()) y_new_1 = patcher.Not(NEW_ID, b_group_1);
if (!b_group_1.empty()) y_new_1 = patcher.Not(NEW_TWINE, b_group_1);
if (!b_group_x.empty()) {
if (keepdc)
y_new_x = patcher.Xor(NEW_ID, Const(State::Sx, GetSize(b_group_x)), b_group_x);
y_new_x = patcher.Xor(NEW_TWINE, Const(State::Sx, GetSize(b_group_x)), b_group_x);
else // This should be fine even with keepdc, but opt_expr_xor.ys wants to keep the xor
y_new_x = Const(State::Sx, GetSize(b_group_x));
}
@ -849,11 +849,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
RTLIL::SigSpec y_new_0, y_new_1;
if (flip) {
if (!b_group_0.empty()) y_new_0 = patcher.And(NEW_ID, b_group_0, patcher.Not(NEW_ID, s_group_0));
if (!b_group_1.empty()) y_new_1 = patcher.Or(NEW_ID, b_group_1, s_group_1);
if (!b_group_0.empty()) y_new_0 = patcher.And(NEW_TWINE, b_group_0, patcher.Not(NEW_TWINE, s_group_0));
if (!b_group_1.empty()) y_new_1 = patcher.Or(NEW_TWINE, b_group_1, s_group_1);
} else {
if (!b_group_0.empty()) y_new_0 = patcher.And(NEW_ID, b_group_0, s_group_0);
if (!b_group_1.empty()) y_new_1 = patcher.Or(NEW_ID, b_group_1, patcher.Not(NEW_ID, s_group_1));
if (!b_group_0.empty()) y_new_0 = patcher.And(NEW_TWINE, b_group_0, s_group_0);
if (!b_group_1.empty()) y_new_1 = patcher.Or(NEW_TWINE, b_group_1, patcher.Not(NEW_TWINE, s_group_1));
}
RTLIL::SigSpec new_sig_y(width);
@ -1059,12 +1059,12 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
RTLIL::SigBit a = sig_a[i];
if (b == ((bi ^ ci) ? State::S1 : State::S0)) {
module->connect(sig_y[i], a);
module->connect(sig_x[i], ci ? module->Not(NEW_ID, a).as_bit() : a);
module->connect(sig_x[i], ci ? module->Not(NEW_TWINE, a).as_bit() : a);
module->connect(sig_co[i], ci ? State::S1 : State::S0);
}
else if (a == (ci ? State::S1 : State::S0)) {
module->connect(sig_y[i], bi ? module->Not(NEW_ID, b).as_bit() : b);
module->connect(sig_x[i], (bi ^ ci) ? module->Not(NEW_ID, b).as_bit() : b);
module->connect(sig_y[i], bi ? module->Not(NEW_TWINE, b).as_bit() : b);
module->connect(sig_x[i], (bi ^ ci) ? module->Not(NEW_TWINE, b).as_bit() : b);
module->connect(sig_co[i], ci ? State::S1 : State::S0);
}
else
@ -1486,7 +1486,7 @@ skip_fine_alu:
/* sub, b is 0 */
RTLIL::SigSpec a = cell->getPort(TW::A);
a.extend_u0(y_width, is_signed);
new_x = patcher.Not(NEW_ID, a);
new_x = patcher.Not(NEW_TWINE, a);
new_co = RTLIL::Const(State::S1, y_width);
a_port = cell->getPort(TW::A);
a_port_signed = a_signed;
@ -1503,8 +1503,8 @@ skip_fine_alu:
}
IdString new_type = arith_inverse ? ID($neg) : ID($pos);
SigSpec new_y = patcher.addWire(NEW_ID, y_width);
Cell *new_cell = patcher.addCell(NEW_ID, new_type);
SigSpec new_y = patcher.addWire(NEW_TWINE, y_width);
Cell *new_cell = patcher.addCell(NEW_TWINE, new_type);
new_cell->setPort(TW::A, a_port);
new_cell->setPort(TW::Y, new_y);
new_cell->setParam(ID::A_WIDTH, a_port_width);
@ -1805,8 +1805,8 @@ skip_identity:
OptExprPatcher patcher(module, &assign_map);
int a_width = cell->parameters[ID::A_WIDTH].as_int();
SigSpec y_wire = patcher.addWire(NEW_ID, y_size);
Cell *mul = patcher.addCell(NEW_ID, ID($mul));
SigSpec y_wire = patcher.addWire(NEW_TWINE, y_size);
Cell *mul = patcher.addCell(NEW_TWINE, ID($mul));
mul->setPort(TW::A, Const(bit_idx, a_width));
mul->setPort(TW::B, cell->getPort(TW::B));
mul->setPort(TW::Y, y_wire);
@ -1816,8 +1816,8 @@ skip_identity:
mul->parameters[ID::B_SIGNED] = cell->parameters[ID::B_SIGNED];
mul->parameters[ID::Y_WIDTH] = y_size;
SigSpec new_y = patcher.addWire(NEW_ID, y_size);
patcher.addShl(NEW_ID, Const(State::S1, 1), y_wire, new_y);
SigSpec new_y = patcher.addWire(NEW_TWINE, y_size);
patcher.addShl(NEW_TWINE, Const(State::S1, 1), y_wire, new_y);
patcher.patch(cell, TW::Y, new_y, "pow_to_mul_shl");
goto next_cell;
@ -1954,13 +1954,13 @@ skip_identity:
// Truncating division is the same as flooring division, except when
// the result is negative and there is a remainder - then trunc = floor + 1
if (is_truncating && a_signed && GetSize(sig_a) != 0 && exp != 0) {
Wire *flooring = module->addWire(NEW_ID, sig_y.size());
Wire *flooring = module->addWire(NEW_TWINE, sig_y.size());
cell->setPort(TW::Y, flooring);
SigSpec a_sign = sig_a[sig_a.size()-1];
SigSpec rem_nonzero = module->ReduceOr(NEW_ID, sig_a.extract(0, exp));
SigSpec should_add = module->And(NEW_ID, a_sign, rem_nonzero);
module->addAdd(NEW_ID, flooring, should_add, sig_y);
SigSpec rem_nonzero = module->ReduceOr(NEW_TWINE, sig_a.extract(0, exp));
SigSpec should_add = module->And(NEW_TWINE, a_sign, rem_nonzero);
module->addAdd(NEW_TWINE, flooring, should_add, sig_y);
}
cell->check();
@ -1980,8 +1980,8 @@ skip_identity:
SigSpec truncating = sig_a.extract(0, exp);
SigSpec a_sign = sig_a[sig_a.size()-1];
SigSpec rem_nonzero = patcher.ReduceOr(NEW_ID, sig_a.extract(0, exp));
SigSpec extend_bit = patcher.And(NEW_ID, a_sign, rem_nonzero);
SigSpec rem_nonzero = patcher.ReduceOr(NEW_TWINE, sig_a.extract(0, exp));
SigSpec extend_bit = patcher.And(NEW_TWINE, a_sign, rem_nonzero);
truncating.append(extend_bit);
SigSpec new_y = truncating;
@ -2071,11 +2071,11 @@ skip_identity:
int sz = cur - prev;
bool last = cur == GetSize(sig_y);
SigSpec slice_y = patcher.addWire(NEW_ID, sz);
SigSpec slice_x = patcher.addWire(NEW_ID, sz);
SigSpec slice_co = patcher.addWire(NEW_ID, sz);
SigSpec slice_y = patcher.addWire(NEW_TWINE, sz);
SigSpec slice_x = patcher.addWire(NEW_TWINE, sz);
SigSpec slice_co = patcher.addWire(NEW_TWINE, sz);
RTLIL::Cell *c = patcher.addCell(NEW_ID, cell->type);
RTLIL::Cell *c = patcher.addCell(NEW_TWINE, cell->type);
c->setPort(TW::A, sig_a.extract(prev, sz));
c->setPort(TW::B, sig_b.extract(prev, sz));
c->setPort(TW::BI, sig_bi);
@ -2248,14 +2248,14 @@ skip_alu_split:
{
condition = stringf("unsigned X<%s", log_signal(const_sig));
replacement = stringf("!X[%d:%d]", var_width - 1, const_bit_hot);
replace_sig[0] = patcher.LogicNot(NEW_ID, var_high_sig).as_bit();
replace_sig[0] = patcher.LogicNot(NEW_TWINE, var_high_sig).as_bit();
replace = true;
}
if (cmp_type == ID($ge))
{
condition = stringf("unsigned X>=%s", log_signal(const_sig));
replacement = stringf("|X[%d:%d]", var_width - 1, const_bit_hot);
replace_sig[0] = patcher.ReduceOr(NEW_ID, var_high_sig).as_bit();
replace_sig[0] = patcher.ReduceOr(NEW_TWINE, var_high_sig).as_bit();
replace = true;
}
}
@ -2297,7 +2297,7 @@ skip_alu_split:
{
condition = "signed X>=0";
replacement = stringf("X[%d]", var_width - 1);
replace_sig[0] = patcher.LogicNot(NEW_ID, var_sig[var_width - 1]).as_bit();
replace_sig[0] = patcher.LogicNot(NEW_TWINE, var_sig[var_width - 1]).as_bit();
replace = true;
}
}

14
passes/opt/opt_ffinv.cc
View File

@ -84,12 +84,12 @@ struct OptFfInvWorker
}
ff.flip_rst_bits({0});
ff.sig_d = d_inv->getPort(ID::A);
ff.sig_d = d_inv->getPort(TW::A);
for (Cell *lut: q_luts) {
if (lut->type == ID($lut)) {
int flip_mask = 0;
SigSpec sig_a = lut->getPort(ID::A);
SigSpec sig_a = lut->getPort(TW::A);
for (int i = 0; i < GetSize(sig_a); i++) {
if (index.sigmap(sig_a[i]) == index.sigmap(ff.sig_q[0])) {
flip_mask |= 1 << i;
@ -101,14 +101,14 @@ struct OptFfInvWorker
new_mask_builder.push_back(mask[j ^ flip_mask]);
Const new_mask = new_mask_builder.build();
if (GetSize(sig_a) == 1 && new_mask.as_int() == 2) {
module->connect(lut->getPort(ID::Y), ff.sig_q);
module->connect(lut->getPort(TW::Y), ff.sig_q);
module->remove(lut);
} else {
lut->setParam(ID::LUT, new_mask);
}
} else {
// it was an inverter
module->connect(lut->getPort(ID::Y), ff.sig_q);
module->connect(lut->getPort(TW::Y), ff.sig_q);
module->remove(lut);
}
}
@ -173,7 +173,7 @@ struct OptFfInvWorker
if (!q_inv) return false;
ff.flip_rst_bits({0});
ff.sig_q = q_inv->getPort(ID::Y);
ff.sig_q = q_inv->getPort(TW::Y);
module->remove(q_inv);
if (d_lut->type == ID($lut)) {
@ -188,12 +188,12 @@ struct OptFfInvWorker
Const new_mask = new_mask_builder.build();
d_lut->setParam(ID::LUT, new_mask);
if (d_lut->getParam(ID::WIDTH) == 1 && new_mask.as_int() == 2) {
module->connect(ff.sig_d, d_lut->getPort(ID::A));
module->connect(ff.sig_d, d_lut->getPort(TW::A));
module->remove(d_lut);
}
} else {
// it was an inverter
module->connect(ff.sig_d, d_lut->getPort(ID::A));
module->connect(ff.sig_d, d_lut->getPort(TW::A));
module->remove(d_lut);
}

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