mirror of https://github.com/YosysHQ/yosys.git
patch: don't gc signorm cells
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@ -90,7 +90,9 @@ struct SrcCollector {
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void Patch::gc(Cell* old_cell) {
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log_debug("gc %s\n", old_cell->name);
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std::vector<Cell*> inputs = {};
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if (old_cell->type.in(ID($input_port), ID($output_port), ID($public)))
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return;
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pool<Cell*> inputs;
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for (auto [port_name, sig] : old_cell->connections()) {
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auto dir = old_cell->port_dir(port_name);
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log_assert(dir != PD_UNKNOWN);
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@ -112,7 +114,7 @@ void Patch::gc(Cell* old_cell) {
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log_assert(in_wire);
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log_debug("\twire %s\n", in_wire->name);
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if (in_wire->known_driver() && !leaves.count(in_wire))
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inputs.push_back(in_wire->driverCell());
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inputs.insert(in_wire->driverCell());
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}
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}
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}
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