patch: infer leaves for gc

kernel/unstable/patch.cc

@@ -156,6 +156,18 @@ void Patch::patch(Cell* old_cell, IdString old_port, SigSpec new_sig) {
 	if (map)
 		map->add(old_sig, new_sig);
 
+	// Inefficient
+	for (auto& cell : cells_) {
+		for (auto& [port_name, sig] : cell->connections()) {
+			auto dir = cell->port_dir(port_name);
+			if (dir == PD_INPUT || dir == PD_INOUT) {
+				for (auto bit : sig)
+					if (bit.is_wire() && bit.wire->module)
+						leaves.insert(bit.wire);
+			}
+		}
+	}
+
 	for (auto& cell: cells_) {
 		cell->set_src_attribute(src_str);
 		cell->fixup_parameters();

kernel/unstable/patch.h

@@ -19,12 +19,13 @@ protected:
 	Cell* commit_cell(std::unique_ptr<Cell> cell);
 	Wire* commit_wire(std::unique_ptr<Wire> wire);
 
+	pool<Wire*> leaves = {};
+
 public:
 	Module* mod;
 	SigMap* map;
 	vector<std::unique_ptr<Wire>> wires_ = {};
 	vector<std::unique_ptr<Cell>> cells_ = {};
-	pool<Wire*> leaves = {};
 
 	void connect(const RTLIL::SigSig &conn);
 	void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);
@@ -39,6 +40,8 @@ public:
 
 	RTLIL::Cell* addDffsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
 		RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src);
+
+	Patch(Module* mod, SigMap* map = nullptr) : mod(mod), map(map) {}
 };
 
 YOSYS_NAMESPACE_END

passes/cmds/test_patch.cc

@@ -23,7 +23,7 @@ struct TestPatchPass : public Pass {
 					log_assert(add->getPort(ID::B).known_driver());
 					auto neg = add->getPort(ID::B)[0].wire->driverCell();
 					log_assert(neg->type == ID($not));
-					RTLIL::Patch patcher = {{}, module, nullptr};
+					RTLIL::Patch patcher(module, nullptr);
 					int width = cell->getPort(ID::A).size();
 					auto sub = patcher.addSub(NEW_ID,
 						neg->getPort(ID::A),
@@ -32,8 +32,6 @@ struct TestPatchPass : public Pass {
 					auto new_out_wire = patcher.addWire(NEW_ID, width);
 					auto new_cell = patcher.addNeg(NEW_ID, sub->getPort(ID::Y), new_out_wire);
 					log_cell(new_cell);
-					patcher.leaves.insert(neg->getPort(ID::A).as_wire());
-					patcher.leaves.insert(add->getPort(ID::A).as_wire());
 					patcher.patch(add, ID::Y, new_out_wire);
 				}
 			}

passes/opt/opt_expr.cc

@@ -628,16 +628,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 					if (sig_b == State::S0) {
 						replace_cell(assign_map, module, cell, "xor_buffer", ID::Y, sig_a);
 					} else {
-						RTLIL::Patch patcher = {{}, module, &assign_map};
+						RTLIL::Patch patcher(module, &assign_map);
 						Wire* y = patcher.addWire(NEW_ID, 1);
 						Cell* new_cell = cell->type == ID($xor) ? patcher.addNot(NEW_ID, sig_a, y) : patcher.addNotGate(NEW_ID, sig_a, y);
 						SigSpec sig_y = y;
 						int width = cell->type == ID($xor) ? cell->getParam(ID::Y_WIDTH).as_int() : 1;
 						sig_y.append(RTLIL::Const(State::S0, width-1));
 						(void)new_cell;
-						for (auto chunk : cell->getPort(port_a).chunks())
-							if (chunk.wire)
-								patcher.leaves.insert(chunk.wire);
 						patcher.patch(cell, ID::Y, sig_y);
 					}
 					goto next_cell;