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WIP

This commit is contained in:
Emil J. Tywoniak 2026-05-29 11:59:27 +02:00
parent dab9a386cc
commit c3457e2e5c
35 changed files with 204 additions and 63 deletions
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2
backends/aiger/aiger.cc
View File

@ -337,7 +337,7 @@ struct AigerWriter
continue;
}
if (cell->type == ID($scopeinfo) || cell->type == ID($input_port))
if (cell->type.in(ID($scopeinfo), ID($input_port), ID($output_port), ID($public)))
continue;
log_error("Unsupported cell type: %s (%s)\n", cell->type.unescape(), cell);

2
backends/aiger2/aiger.cc
View File

@ -109,7 +109,7 @@ struct Index {
int pos = index_wires(info, m);
for (auto cell : m->cells()) {
if (known_ops(cell->type) || cell->type.in(ID($scopeinfo), ID($specify2), ID($specify3), ID($input_port)))
if (known_ops(cell->type) || cell->type.in(ID($scopeinfo), ID($specify2), ID($specify3), ID($input_port), ID($output_port), ID($public)))
continue;
Module *submodule = m->design->module(cell->type);

2
backends/cxxrtl/cxxrtl_backend.cc
View File

@ -1518,7 +1518,7 @@ struct CxxrtlWorker {
f << (cell->getParam(ID::CLR_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n";
}
// Internal cells
} else if (cell->type == ID($input_port)) {
} else if (cell->type.in(ID($input_port), ID($output_port), ID($public))) {
} else if (is_internal_cell(cell->type)) {
log_cmd_error("Unsupported internal cell `%s'.\n", cell->type);
// User cells

2
backends/verilog/verilog_backend.cc
View File

@ -1542,7 +1542,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true;
}
if (cell->type == ID($input_port))
if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
return true;
if (cell->type == ID($connect))

2
kernel/celltypes.h
View File

@ -113,6 +113,8 @@ struct CellTypes
setup_type(ID($future_ff), {ID::A}, {ID::Y});
setup_type(ID($scopeinfo), {}, {});
setup_type(ID($input_port), {}, {ID::Y});
setup_type(ID($output_port), {ID::A}, {});
setup_type(ID($public), {ID::A}, {});
setup_type(ID($connect), {ID::A, ID::B}, {});
}

2
kernel/constids.inc
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@ -253,12 +253,14 @@ X($not)
X($or)
X($original_tag)
X($output)
X($output_port)
X($overwrite_tag)
X($pending)
X($pmux)
X($pos)
X($pow)
X($print)
X($public)
X($recrem)
X($reduce_and)
X($reduce_bool)

2
kernel/newcelltypes.h
View File

@ -90,6 +90,8 @@ struct CellTableBuilder {
setup_type(ID($future_ff), {ID::A}, {ID::Y}, features);
setup_type(ID($scopeinfo), {}, {}, features);
setup_type(ID($input_port), {}, {ID::Y}, features);
setup_type(ID($output_port), {ID::A}, {}, features);
setup_type(ID($public), {ID::A}, {}, features);
setup_type(ID($connect), {ID::A, ID::B}, {}, features);
}
constexpr void setup_internals_eval()

6
kernel/rtlil.cc
View File

@ -2539,6 +2539,12 @@ namespace {
check_expected();
return;
}
if (cell->type.in(ID($output_port), ID($public))) {
param(ID::WIDTH);
port(ID::A, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type.in(ID($connect))) {
param(ID::WIDTH);
port(ID::A, param(ID::WIDTH));

69
kernel/rtlil_bufnorm.cc
View File

@ -54,6 +54,7 @@ struct RTLIL::SigNormIndex
module->fixup_ports();
setup_module_inputs();
setup_driven_wires();
setup_module_outputs_and_publics();
setup_fanout();
}
@ -110,6 +111,72 @@ struct RTLIL::SigNormIndex
}
}
// Creates $output_port cells consuming each pure-output module port wire
// and $public cells consuming each public-named wire that isn't already
// covered by an $input_port or $output_port. These act as fanout sentinels
// so local GC (e.g. in Patch) won't remove driver cells whose only purpose
// is to feed a port or a user-visible wire.
void setup_module_outputs_and_publics() {
std::vector<Cell *> cells_to_remove;
dict<Wire *, Cell *> output_port_cells;
dict<Wire *, Cell *> public_cells;
for (auto cell : module->cells()) {
if (cell->type != ID($output_port) && cell->type != ID($public))
continue;
auto const &sig_a = cell->getPort(ID::A);
Wire *wire = nullptr;
if (!sig_a.is_wire()) {
cells_to_remove.push_back(cell);
continue;
}
wire = sig_a.as_wire();
if (cell->type == ID($output_port)) {
if (wire->port_output && !wire->port_input && !output_port_cells.count(wire))
output_port_cells.emplace(wire, cell);
else
cells_to_remove.push_back(cell);
} else { // $public
bool is_pure_input = wire->port_input && !wire->port_output;
bool is_pure_output = wire->port_output && !wire->port_input;
if (wire->name.isPublic() && !is_pure_input && !is_pure_output && !public_cells.count(wire))
public_cells.emplace(wire, cell);
else
cells_to_remove.push_back(cell);
}
}
for (auto cell : cells_to_remove)
module->remove(cell);
for (auto portname : module->ports) {
Wire *wire = module->wire(portname);
if (wire->port_output && !wire->port_input && !output_port_cells.count(wire)) {
Cell *cell = module->addCell(NEW_ID, ID($output_port));
cell->setParam(ID::WIDTH, GetSize(wire));
cell->setPort(ID::A, wire);
output_port_cells.emplace(wire, cell);
}
}
for (auto &it : module->wires_) {
Wire *wire = it.second;
if (!wire->name.isPublic())
continue;
bool is_pure_input = wire->port_input && !wire->port_output;
bool is_pure_output = wire->port_output && !wire->port_input;
if (is_pure_input || is_pure_output)
continue;
if (public_cells.count(wire))
continue;
Cell *cell = module->addCell(NEW_ID, ID($public));
cell->setParam(ID::WIDTH, GetSize(wire));
cell->setPort(ID::A, wire);
public_cells.emplace(wire, cell);
}
}
void setup_driven_wires() {
for (auto cell : module->cells()) {
xlog("setup_driven_wires cell %s %s\n", cell->type, cell->name);
@ -352,7 +419,7 @@ void RTLIL::Design::sigNormalize(bool enable)
// TODO inefficient?
std::vector<Cell*> cells_snapshot = module->cells();
for (auto cell : cells_snapshot) {
if (cell->type == ID($input_port))
if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
module->remove(cell);
}
}

2
kernel/satgen.cc
View File

@ -1399,7 +1399,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
return true;
}
if (cell->type == ID($scopeinfo) || cell->type == ID($input_port))
if (cell->type.in(ID($scopeinfo), ID($input_port), ID($output_port), ID($public)))
{
return true;
}

7
kernel/unstable/patch.cc
View File

@ -178,6 +178,13 @@ void Patch::patch(Cell* old_cell, IdString old_port, SigSpec new_sig) {
for (auto& wire: wires_)
commit_wire(std::move(wire));
// Flush pending sigmap updates (from the mod->connect above) into the
// fanout index so gc() sees the updated fanout for cells whose outputs
// were the patched wires. Without this, downstream consumers like the
// $output_port / $public sentinels still appear in the OLD wire's fanout
// instead of the new representative.
mod->sigNormalize();
gc(old_cell);
cells_.clear();
wires_.clear();

2
passes/cmds/abstract.cc
View File

@ -265,7 +265,7 @@ unsigned int abstract_value(Module* mod, EnableLogic enable, const std::vector<S
unsigned int changed = 0;
std::vector<Cell*> cells_snapshot = mod->cells();
for (auto cell : cells_snapshot) {
if (cell->type == ID($input_port))
if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
continue;
for (auto conn : cell->connections())
if (cell->output(conn.first)) {

2
passes/cmds/check.cc
View File

@ -358,7 +358,7 @@ struct CheckPass : public Pass {
pool<Cell *> coarsened_cells;
for (auto cell : module->cells())
{
if (cell->type == ID($input_port))
if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
continue;
if (mapped && cell->type.begins_with("$") && design->module(cell->type) == nullptr) {

2
passes/cmds/portarcs.cc
View File

@ -125,7 +125,7 @@ struct PortarcsPass : Pass {
for (auto cell : m->cells())
// Ignore all bufnorm helper cells
if (!cell->type.in(ID($buf), ID($input_port), ID($connect), ID($tribuf))) {
if (!cell->type.in(ID($buf), ID($input_port), ID($output_port), ID($public), ID($connect), ID($tribuf))) {
auto tdata = tinfo.find(cell->type);
if (tdata == tinfo.end())
log_cmd_error("Missing timing data for module '%s'.\n", cell->type.unescape());

4
passes/equiv/equiv_make.cc
View File

@ -115,7 +115,7 @@ struct EquivMakeWorker
if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
cell_names.insert(it->name);
gold_clone->rename(it, it->name.str() + "_gold");
if (it->type == ID($input_port))
if (it->type.in(ID($input_port), ID($output_port), ID($public)))
gold_clone->remove(it);
}
@ -129,7 +129,7 @@ struct EquivMakeWorker
if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
cell_names.insert(it->name);
gate_clone->rename(it, it->name.str() + "_gate");
if (it->type == ID($input_port))
if (it->type.in(ID($input_port), ID($output_port), ID($public)))
gate_clone->remove(it);
}

2
passes/equiv/equiv_miter.cc
View File

@ -143,7 +143,7 @@ struct EquivMiterWorker
for (auto w : miter_wires)
miter_module->addWire(w->name, w->width);
for (auto c : miter_cells) {
if (c->type == ID($input_port))
if (c->type.in(ID($input_port), ID($output_port), ID($public)))
continue;
auto mc = miter_module->addCell(c->name, c);
for (auto &conn : mc->connections())

2
passes/fsm/fsm_detect.cc
View File

@ -99,6 +99,8 @@ static bool check_state_users(RTLIL::SigSpec sig)
RTLIL::Cell *cell = cellport.first;
if (muxtree_cells.count(cell) > 0)
continue;
if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
continue;
if (cell->type == ID($logic_not) && assign_map(cell->getPort(ID::A)) == sig)
continue;
if (cellport.second != ID::A && cellport.second != ID::B)

2
passes/hierarchy/flatten.cc
View File

@ -178,7 +178,7 @@ struct FlattenWorker
}
for (auto tpl_cell : tpl->cells()) {
if (tpl_cell->type == ID($input_port))
if (tpl_cell->type.in(ID($input_port), ID($output_port), ID($public)))
continue;
RTLIL::Cell *new_cell = module->addCell(map_name(cell, tpl_cell, separator), tpl_cell);
map_attributes(cell, new_cell, tpl_cell->name);

14
passes/opt/opt_clean/cells_temp.cc
View File

@ -50,9 +50,9 @@ bool trim_buf(RTLIL::Cell* cell, ShardedVector<RTLIL::SigSig>& new_connections,
}
bool remove(ShardedVector<RTLIL::Cell*>& cells, RTLIL::Module* mod, bool verbose) {
// Removing $connect and $input_port doesn't count as "doing something"
// since they get rebuilt in signorm
// and don't enable further opt
// Removing $connect, $input_port, $output_port and $public doesn't count
// as "doing something" since they get rebuilt in signorm and don't enable
// further opt
bool did_something = false;
for (RTLIL::Cell *cell : cells) {
if (verbose) {
@ -62,6 +62,12 @@ bool remove(ShardedVector<RTLIL::Cell*>& cells, RTLIL::Module* mod, bool verbose
} else if (cell->type == ID($input_port)) {
log_debug(" removing input port marker cell `%s': %s\n", cell->name,
log_signal(cell->getPort(ID::Y)));
} else if (cell->type == ID($output_port)) {
log_debug(" removing output port marker cell `%s': %s\n", cell->name,
log_signal(cell->getPort(ID::A)));
} else if (cell->type == ID($public)) {
log_debug(" removing public wire marker cell `%s': %s\n", cell->name,
log_signal(cell->getPort(ID::A)));
} else {
did_something = true;
log_debug(" removing buffer cell `%s': %s = %s\n", cell->name,
@ -93,7 +99,7 @@ void remove_temporary_cells(RTLIL::Module *module, ParallelDispatchThreadPool::S
std::swap(a, b);
new_connections.insert(ctx, {a, b});
delcells.insert(ctx, cell);
} else if (cell->type.in(ID($input_port)) && !cell->has_keep_attr()) {
} else if (cell->type.in(ID($input_port), ID($output_port), ID($public)) && !cell->has_keep_attr()) {
delcells.insert(ctx, cell);
}
}

2
passes/opt/opt_merge_inc.cc
View File

@ -52,6 +52,8 @@ static constexpr MergeableTypes build_mergeable_types(bool nomux) {
c.set_id(ID($allconst), false);
c.set_id(ID($connect), false);
c.set_id(ID($input_port), false);
c.set_id(ID($output_port), false);
c.set_id(ID($public), false);
if (nomux) {
c.set_id(ID($mux), false);
c.set_id(ID($pmux), false);

5
passes/opt/opt_share.cc
View File

@ -363,10 +363,13 @@ struct OptSharePass : public Pass {
dict<RTLIL::SigBit, int> bit_users;
for (auto cell : module->cells())
for (auto cell : module->cells()) {
if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
continue;
for (auto conn : cell->connections())
for (auto bit : conn.second)
bit_users[sigmap(bit)]++;
}
for (auto wire : module->wires())
if (wire->port_id != 0)

3
passes/sat/sim.cc
View File

@ -602,6 +602,9 @@ struct SimInstance
if (cell->type == ID($print))
return;
if (cell->type.in(ID($input_port), ID($output_port), ID($public), ID($connect)))
return;
log_error("Unsupported cell type: %s (%s.%s)\n", cell->type.unescape(), module, cell);
}

5
passes/techmap/arith_tree.cc
View File

@ -29,11 +29,14 @@ struct Traversal {
dict<SigBit, int> fanout;
Traversal(Module *module) : sigmap(module)
{
for (auto cell : module->cells())
for (auto cell : module->cells()) {
if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
continue;
for (auto &conn : cell->connections())
if (cell->input(conn.first))
for (auto bit : sigmap(conn.second))
bit_consumers[bit].insert(cell);
}
for (auto &pair : bit_consumers)
fanout[pair.first] = pair.second.size();

18
techlibs/common/simlib.v
View File

@ -3250,3 +3250,21 @@ parameter WIDTH = 0;
inout [WIDTH-1:0] Y;
endmodule
// --------------------------------------------------------
//* group wire
module \$output_port (A);
parameter WIDTH = 0;
input [WIDTH-1:0] A;
endmodule
// --------------------------------------------------------
//* group wire
module \$public (A);
parameter WIDTH = 0;
input [WIDTH-1:0] A;
endmodule

18
techlibs/common/techmap.v
View File

@ -637,3 +637,21 @@ parameter WIDTH = 0;
inout [WIDTH-1:0] Y; // This cell is just a maker, so we leave Y undriven
endmodule
(* techmap_celltype = "$output_port" *)
module \$output_port (A);
parameter WIDTH = 0;
input [WIDTH-1:0] A; // This cell is just a marker for module output ports
endmodule
(* techmap_celltype = "$public" *)
module \$public (A);
parameter WIDTH = 0;
input [WIDTH-1:0] A; // This cell is just a marker for public-named wires
endmodule

4
tests/opt/bug1758.ys
View File

@ -8,11 +8,11 @@ copy gold fine
cd coarse
opt_expr
select -assert-none c:* t:$input_port %d
select -assert-none c:* t:$*_port %d t:$public %d
cd fine
opt_expr
select -assert-none c:* t:$input_port %d
select -assert-none c:* t:$*_port %d t:$public %d
cd
miter -equiv -flatten -make_assert -make_outputs coarse fine miter
sat -verify -prove-asserts -show-ports miter

14
tests/opt/opt_dff_dffmux.ys
View File

@ -9,7 +9,7 @@ proc
equiv_opt -assert opt
design -load postopt
select -assert-count 1 t:$dffe r:WIDTH=2 %i
select -assert-count 0 t:$dffe %% t:* %D t:$input_port %d
select -assert-count 0 t:$dffe %% t:* %D t:$*_port %d t:$public %d
####################
@ -25,7 +25,7 @@ equiv_opt -assert opt
design -load postopt
wreduce
select -assert-count 1 t:$dffe r:WIDTH=2 %i
select -assert-count 0 t:$dffe %% t:* %D t:$input_port %d
select -assert-count 0 t:$dffe %% t:* %D t:$*_port %d t:$public %d
###################
@ -40,7 +40,7 @@ proc
equiv_opt -assert opt
design -load postopt
select -assert-count 1 t:$dffe r:WIDTH=2 %i
select -assert-count 0 t:$dffe %% t:* %D t:$input_port %d
select -assert-count 0 t:$dffe %% t:* %D t:$*_port %d t:$public %d
###################
@ -56,7 +56,7 @@ equiv_opt -assert opt
design -load postopt
dump
select -assert-count 1 t:$dffe r:WIDTH=4 %i
select -assert-count 0 t:$dffe %% t:* %D t:$input_port %d
select -assert-count 0 t:$dffe %% t:* %D t:$*_port %d t:$public %d
####################
@ -72,7 +72,7 @@ equiv_opt -assert opt
design -load postopt
wreduce
select -assert-count 1 t:$sdffe r:WIDTH=2 %i
select -assert-count 0 t:$sdffe %% t:* %D t:$input_port %d
select -assert-count 0 t:$sdffe %% t:* %D t:$*_port %d t:$public %d
####################
@ -91,7 +91,7 @@ equiv_opt -assert opt
design -load postopt
wreduce
select -assert-count 1 t:$sdffe r:WIDTH=2 %i
select -assert-count 0 t:$sdffe %% t:* %D t:$input_port %d
select -assert-count 0 t:$sdffe %% t:* %D t:$*_port %d t:$public %d
####################
@ -127,4 +127,4 @@ sat -tempinduct -verify -prove-asserts -show-ports miter
design -load gate
select -assert-count 1 t:$sdffe r:WIDTH=3 %i
select -assert-count 0 t:$sdffe %% t:* %D t:$input_port %d
select -assert-count 0 t:$sdffe %% t:* %D t:$*_port %d t:$public %d

16
tests/opt/opt_expr_alu.ys
View File

@ -8,7 +8,7 @@ alumacc
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 1 t:$pos
select -assert-none t:$pos t:* %D t:$input_port %d
select -assert-none t:$pos t:* %D t:$*_port %d t:$public %d
design -reset
@ -20,7 +20,7 @@ EOT
alumacc
select -assert-count 1 t:$alu
select -assert-none t:$alu t:* %D t:$input_port %d
select -assert-none t:$alu t:* %D t:$*_port %d t:$public %d
design -reset
@ -33,7 +33,7 @@ EOT
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 1 t:$pos
select -assert-none t:$pos t:* %D t:$input_port %d
select -assert-none t:$pos t:* %D t:$*_port %d t:$public %d
design -reset
@ -46,7 +46,7 @@ EOT
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 1 t:$pos
select -assert-none t:$pos t:* %D t:$input_port %d
select -assert-none t:$pos t:* %D t:$*_port %d t:$public %d
design -reset
@ -60,7 +60,7 @@ alumacc
equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 1 t:$not
select -assert-none t:$not %% t:* %D t:$input_port %d
select -assert-none t:$not %% t:* %D t:$*_port %d t:$public %d
design -reset
@ -76,7 +76,7 @@ design -load postopt
select -assert-count 1 t:$alu
select -assert-count 1 t:$alu r:Y_WIDTH=3 %i
select -assert-count 1 t:$not
select -assert-none t:$alu t:$not t:* %D %D t:$input_port %d
select -assert-none t:$alu t:$not t:* %D %D t:$*_port %d t:$public %d
design -reset
@ -93,7 +93,7 @@ dump
select -assert-count 2 t:$alu
select -assert-count 1 t:$alu r:Y_WIDTH=2 %i
select -assert-count 1 t:$alu r:Y_WIDTH=3 %i
select -assert-none t:$alu t:* %D t:$input_port %d
select -assert-none t:$alu t:* %D t:$*_port %d t:$public %d
design -reset
@ -108,7 +108,7 @@ equiv_opt -assert opt -fine
design -load postopt
select -assert-count 2 t:$alu
select -assert-count 2 t:$alu r:Y_WIDTH=3 %i
select -assert-none t:$alu t:* %D t:$input_port %d
select -assert-none t:$alu t:* %D t:$*_port %d t:$public %d
design -reset

16
tests/opt/opt_expr_and.ys
View File

@ -12,12 +12,12 @@ copy gold fine_keepdc
cd coarse
opt_expr
select -assert-none c:* t:$input_port %d
select -assert-none c:* t:$*_port %d t:$public %d
cd fine
simplemap
opt_expr
select -assert-none c:* t:$input_port %d
select -assert-none c:* t:$*_port %d t:$public %d
cd
miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x gold coarse miter
@ -27,12 +27,12 @@ sat -verify -prove-asserts -show-ports -enable_undef miter2
cd coarse_keepdc
opt_expr -keepdc
select -assert-count 1 c:* t:$input_port %d
select -assert-count 1 c:* t:$*_port %d t:$public %d
cd fine_keepdc
simplemap
opt_expr -keepdc
select -assert-count 1 c:* t:$input_port %d
select -assert-count 1 c:* t:$*_port %d t:$public %d
cd
miter -equiv -flatten -make_assert -make_outputs gold coarse_keepdc miter3
@ -56,12 +56,12 @@ copy gold fine_keepdc
cd coarse
opt_expr -fine
select -assert-none c:* t:$input_port %d
select -assert-none c:* t:$*_port %d t:$public %d
cd fine
simplemap
opt_expr
select -assert-none c:* t:$input_port %d
select -assert-none c:* t:$*_port %d t:$public %d
cd
miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x gold coarse miter
@ -71,12 +71,12 @@ sat -verify -prove-asserts -show-ports -enable_undef miter2
cd coarse_keepdc
opt_expr -fine -keepdc
select -assert-count 1 c:* t:$input_port %d
select -assert-count 1 c:* t:$*_port %d t:$public %d
cd fine_keepdc
simplemap
opt_expr -keepdc
select -assert-count 2 c:* t:$input_port %d
select -assert-count 2 c:* t:$*_port %d t:$public %d
cd
miter -equiv -flatten -make_assert -make_outputs gold coarse_keepdc miter3

8
tests/opt/opt_expr_more.ys
View File

@ -50,7 +50,7 @@ opt_expr -fine
# The division by zero should be removed
select -assert-count 0 t:$div
# No cells should be left as it's replaced with constant undef
select -assert-none t:* t:$input_port %d
select -assert-none t:* t:$*_port %d t:$public %d
design -reset
read_verilog <<EOT
@ -64,7 +64,7 @@ design -load postopt
# The mux should be removed completely
select -assert-count 0 t:$mux
# No additional cells needed - direct connection
select -assert-none t:* t:$input_port %d
select -assert-none t:* t:$*_port %d t:$public %d
design -reset
read_verilog <<EOT
@ -110,7 +110,7 @@ design -load postopt
# The comparison of different constants should be replaced with constant 0
select -assert-count 0 t:$eq
# No other cells should be present (just the constant driver)
select -assert-none t:* t:$input_port %d
select -assert-none t:* t:$*_port %d t:$public %d
# opt.opt_expr.invert.double
@ -131,7 +131,7 @@ design -load postopt
opt_clean -purge
select -assert-count 0 t:$not
# No other cells should be present
select -assert-none t:* t:$input_port %d
select -assert-none t:* t:$*_port %d t:$public %d
# opt.opt_expr.reduce_xnor_not

16
tests/opt/opt_expr_or.ys
View File

@ -12,12 +12,12 @@ copy gold fine_keepdc
cd coarse
opt_expr
select -assert-none c:* t:$input_port %d
select -assert-none c:* t:$*_port %d t:$public %d
cd fine
simplemap
opt_expr
select -assert-none c:* t:$input_port %d
select -assert-none c:* t:$*_port %d t:$public %d
cd
miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x gold coarse miter
@ -27,12 +27,12 @@ sat -verify -prove-asserts -show-ports -enable_undef miter2
cd coarse_keepdc
opt_expr -keepdc
select -assert-count 1 c:* t:$input_port %d
select -assert-count 1 c:* t:$*_port %d t:$public %d
cd fine_keepdc
simplemap
opt_expr -keepdc
select -assert-count 1 c:* t:$input_port %d
select -assert-count 1 c:* t:$*_port %d t:$public %d
cd
miter -equiv -flatten -make_assert -make_outputs gold coarse_keepdc miter3
@ -56,12 +56,12 @@ copy gold fine_keepdc
cd coarse
opt_expr -fine
select -assert-none c:* t:$input_port %d
select -assert-none c:* t:$*_port %d t:$public %d
cd fine
simplemap
opt_expr
select -assert-none c:* t:$input_port %d
select -assert-none c:* t:$*_port %d t:$public %d
cd
miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x gold coarse miter
@ -71,12 +71,12 @@ sat -verify -prove-asserts -show-ports -enable_undef miter2
cd coarse_keepdc
opt_expr -fine -keepdc
select -assert-count 1 c:* t:$input_port %d
select -assert-count 1 c:* t:$*_port %d t:$public %d
cd fine_keepdc
simplemap
opt_expr -keepdc
select -assert-count 2 c:* t:$input_port %d
select -assert-count 2 c:* t:$*_port %d t:$public %d
cd
miter -equiv -flatten -make_assert -make_outputs gold coarse_keepdc miter3

2
tests/opt/opt_expr_xnor.ys
View File

@ -27,7 +27,7 @@ sat -verify -prove-asserts -show-ports -enable_undef miter2
cd coarse_keepdc
opt_expr -keepdc
select -assert-count 1 c:* t:$input_port %d
select -assert-count 1 c:* t:$*_port %d t:$public %d
cd fine_keepdc
simplemap

8
tests/opt/opt_expr_xor.ys
View File

@ -66,12 +66,12 @@ copy gold fine_keepdc
cd coarse
opt_expr
select -assert-none c:* t:$input_port %d
select -assert-none c:* t:$*_port %d t:$public %d
cd fine
simplemap
opt_expr
select -assert-none c:* t:$input_port %d
select -assert-none c:* t:$*_port %d t:$public %d
cd
miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x gold coarse miter
@ -81,12 +81,12 @@ sat -verify -prove-asserts -show-ports -enable_undef miter2
cd coarse_keepdc
opt_expr -keepdc
select -assert-count 1 c:* t:$input_port %d
select -assert-count 1 c:* t:$*_port %d t:$public %d
cd fine_keepdc
simplemap
opt_expr -keepdc
select -assert-count 1 c:* t:$input_port %d
select -assert-count 1 c:* t:$*_port %d t:$public %d
cd
miter -equiv -flatten -make_assert -make_outputs gold coarse_keepdc miter3

2
tests/techmap/clockgate.tcl
View File

@ -196,7 +196,7 @@ select -module dffe_10 -assert-count 1 t:\$_NOT_
select -module dffe_11 -assert-count 0 t:\$_NOT_
# $sdffe is not gated
select -module sdffe -assert-count 0 sdffe t:* t:\$sdffe %d t:\$input_port %d
select -module sdffe -assert-count 0 sdffe t:* t:\$sdffe %d t:\$*_port %d t:\$public %d
#------------------------------------------------------------------------------

2
tests/various/rename_scramble_name.ys
View File

@ -28,4 +28,4 @@ hierarchy -top top
rename -seed 2 -scramble-name c:bar
select -assert-none c:bar
select -assert-count 1 c:$_*_
select -assert-none c:$_*_ w:* foo/c:$add$<<EOF:2$1 %% %n
select -assert-none c:$_*_ w:* foo/t:$add %% %n