rtlil: set Module::design before name at all construction sites

frontends/aiger/aigerparse.cc

@@ -222,6 +222,7 @@ AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString
 	: design(design), f(f), clk_name(clk_name), map_filename(map_filename), wideports(wideports), aiger_autoidx(autoidx++)
 {
 	module = new RTLIL::Module;
+	module->design = design;
 	module->name = module_name;
 	if (design->module(module->name))
 		log_error("Duplicate definition of module %s!\n", module->name.unescape());

frontends/ast/ast.cc

@@ -1953,6 +1953,7 @@ RTLIL::Module *AstModule::clone() const
 RTLIL::Module *AstModule::clone(RTLIL::Design *dst, bool src_id_verbatim) const
 {
 	AstModule *new_mod = new AstModule;
+	new_mod->design = dst;
 	new_mod->name = name;
 	dst->add(new_mod);
 	cloneInto(new_mod, src_id_verbatim);

frontends/blif/blifparse.cc

@@ -167,6 +167,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
 				if (module != nullptr)
 					goto error;
 				module = new RTLIL::Module;
+				module->design = design;
 				lastcell = nullptr;
 				char *name = strtok(NULL, " \t\r\n");
 				if (name == nullptr)

frontends/json/jsonparse.cc

@@ -311,6 +311,7 @@ void json_import(Design *design, string &modname, JsonNode *node)
 	log("Importing module %s from JSON tree.\n", modname);
 
 	Module *module = new RTLIL::Module;
+	module->design = design;
 	module->name = RTLIL::escape_id(modname.c_str());
 
 	if (design->module(module->name))

frontends/liberty/liberty.cc

@@ -606,6 +606,7 @@ struct LibertyFrontend : public Frontend {
 			parse_type_map(type_map, cell);
 
 			RTLIL::Module *module = new RTLIL::Module;
+			module->design = design;
 			std::string cell_name = RTLIL::escape_id(cell->args.at(0));
 			module->name = cell_name;
 

frontends/rtlil/rtlil_frontend.cc

@@ -444,6 +444,7 @@ struct RTLILFrontendWorker {
 		}
 
 		current_module = new RTLIL::Module;
+		current_module->design = design;
 		current_module->name = std::move(module_name);
 		if (delete_current_module) {
 			// Module is about to be discarded — drop its src attribute

frontends/verific/verific.cc

@@ -1492,6 +1492,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 	}
 
 	module = new RTLIL::Module;
+	module->design = design;
 	module->name = module_name;
 	design->add(module);
 

passes/hierarchy/hierarchy.cc

@@ -119,6 +119,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
 		log_assert(indices.empty());
 
 		RTLIL::Module *mod = new RTLIL::Module;
+		mod->design = design;
 		mod->name = celltype;
 		mod->attributes[ID::blackbox] = RTLIL::Const(1);
 		design->add(mod);

passes/hierarchy/submod.cc

@@ -116,6 +116,7 @@ struct SubmodWorker
 		}
 
 		RTLIL::Module *new_mod = new RTLIL::Module;
+		new_mod->design = design;
 		new_mod->name = submod.full_name;
 		design->add(new_mod);
 		int auto_name_counter = 1;

passes/sat/miter.cc

@@ -131,6 +131,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
 	log("Creating miter cell \"%s\" with gold cell \"%s\" and gate cell \"%s\".\n", miter_name.unescape(), gold_name.unescape(), gate_name.unescape());
 
 	RTLIL::Module *miter_module = new RTLIL::Module;
+	miter_module->design = design;
 	miter_module->name = miter_name;
 	design->add(miter_module);
 

passes/techmap/extract.cc

@@ -716,6 +716,7 @@ struct ExtractPass : public Pass {
 				}
 
 				RTLIL::Module *newMod = new RTLIL::Module;
+				newMod->design = map;
 				newMod->name = stringf("\\needle%05d_%s_%dx", needleCounter++, haystack_map.at(result.graphId)->name.unescape(), result.totalMatchesAfterLimits);
 				map->add(newMod);