mirror of https://github.com/YosysHQ/yosys.git
patch: gc collects src from every removed cell; ff.cc routes through Patch
This commit is contained in:
Emil J. Tywoniak
parent
e583da906d
commit
61b0dfd3bf
95
kernel/ff.cc
95
kernel/ff.cc
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@ -18,19 +18,10 @@
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*/
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#include "kernel/ff.h"
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#include "kernel/unstable/patch.h"
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USING_YOSYS_NAMESPACE
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namespace {
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// Pull the FF's src attribute so we can propagate it to intermediate
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// cells created during unmap / conversion — otherwise downstream tools
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// lose source provenance for the unmapped logic.
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std::string ff_src(const FfData &ff) {
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auto it = ff.attributes.find(ID::src);
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return it == ff.attributes.end() ? std::string() : it->second.decode_string();
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}
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}
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// sorry
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template<typename InputType, typename OutputType, typename = std::enable_if_t<std::is_base_of_v<FfTypeData, OutputType>>>
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void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
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@ -494,64 +485,65 @@ void FfData::aload_to_sr() {
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log_assert(!has_sr);
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has_sr = true;
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has_aload = false;
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std::string src = ff_src(*this);
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RTLIL::Patch patcher(module);
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if (!is_fine) {
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pol_clr = false;
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pol_set = true;
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if (pol_aload) {
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sig_clr = module->Mux(NEW_ID, Const(State::S1, width), sig_ad, sig_aload, src);
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sig_set = module->Mux(NEW_ID, Const(State::S0, width), sig_ad, sig_aload, src);
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sig_clr = patcher.Mux(NEW_ID, Const(State::S1, width), sig_ad, sig_aload);
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sig_set = patcher.Mux(NEW_ID, Const(State::S0, width), sig_ad, sig_aload);
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} else {
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sig_clr = module->Mux(NEW_ID, sig_ad, Const(State::S1, width), sig_aload, src);
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sig_set = module->Mux(NEW_ID, sig_ad, Const(State::S0, width), sig_aload, src);
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sig_clr = patcher.Mux(NEW_ID, sig_ad, Const(State::S1, width), sig_aload);
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sig_set = patcher.Mux(NEW_ID, sig_ad, Const(State::S0, width), sig_aload);
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}
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} else {
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pol_clr = pol_aload;
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pol_set = pol_aload;
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if (pol_aload) {
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sig_clr = module->AndnotGate(NEW_ID, sig_aload, sig_ad, src);
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sig_set = module->AndGate(NEW_ID, sig_aload, sig_ad, src);
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sig_clr = patcher.AndnotGate(NEW_ID, sig_aload, sig_ad);
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sig_set = patcher.AndGate(NEW_ID, sig_aload, sig_ad);
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} else {
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sig_clr = module->OrGate(NEW_ID, sig_aload, sig_ad, src);
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sig_set = module->OrnotGate(NEW_ID, sig_aload, sig_ad, src);
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sig_clr = patcher.OrGate(NEW_ID, sig_aload, sig_ad);
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sig_set = patcher.OrnotGate(NEW_ID, sig_aload, sig_ad);
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}
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}
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patcher.commit_inheriting_src(cell);
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}
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void FfData::convert_ce_over_srst(bool val) {
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if (!has_ce || !has_srst || ce_over_srst == val)
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return;
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std::string src = ff_src(*this);
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RTLIL::Patch patcher(module);
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if (val) {
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// sdffe to sdffce
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if (!is_fine) {
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if (pol_ce) {
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if (pol_srst) {
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sig_ce = module->Or(NEW_ID, sig_ce, sig_srst, false, src);
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sig_ce = patcher.Or(NEW_ID, sig_ce, sig_srst);
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} else {
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SigSpec tmp = module->Not(NEW_ID, sig_srst, false, src);
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sig_ce = module->Or(NEW_ID, sig_ce, tmp, false, src);
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SigSpec tmp = patcher.Not(NEW_ID, sig_srst);
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sig_ce = patcher.Or(NEW_ID, sig_ce, tmp);
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}
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} else {
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if (pol_srst) {
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SigSpec tmp = module->Not(NEW_ID, sig_srst, false, src);
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sig_ce = module->And(NEW_ID, sig_ce, tmp, false, src);
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SigSpec tmp = patcher.Not(NEW_ID, sig_srst);
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sig_ce = patcher.And(NEW_ID, sig_ce, tmp);
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} else {
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sig_ce = module->And(NEW_ID, sig_ce, sig_srst, false, src);
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sig_ce = patcher.And(NEW_ID, sig_ce, sig_srst);
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}
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}
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} else {
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if (pol_ce) {
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if (pol_srst) {
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sig_ce = module->OrGate(NEW_ID, sig_ce, sig_srst, src);
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sig_ce = patcher.OrGate(NEW_ID, sig_ce, sig_srst);
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} else {
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sig_ce = module->OrnotGate(NEW_ID, sig_ce, sig_srst, src);
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sig_ce = patcher.OrnotGate(NEW_ID, sig_ce, sig_srst);
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}
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} else {
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if (pol_srst) {
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sig_ce = module->AndnotGate(NEW_ID, sig_ce, sig_srst, src);
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sig_ce = patcher.AndnotGate(NEW_ID, sig_ce, sig_srst);
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} else {
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sig_ce = module->AndGate(NEW_ID, sig_ce, sig_srst, src);
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sig_ce = patcher.AndGate(NEW_ID, sig_ce, sig_srst);
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}
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}
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}
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@ -560,35 +552,36 @@ void FfData::convert_ce_over_srst(bool val) {
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if (!is_fine) {
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if (pol_srst) {
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if (pol_ce) {
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sig_srst = cell->module->And(NEW_ID, sig_srst, sig_ce, false, src);
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sig_srst = patcher.And(NEW_ID, sig_srst, sig_ce);
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} else {
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SigSpec tmp = module->Not(NEW_ID, sig_ce, false, src);
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sig_srst = cell->module->And(NEW_ID, sig_srst, tmp, false, src);
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SigSpec tmp = patcher.Not(NEW_ID, sig_ce);
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sig_srst = patcher.And(NEW_ID, sig_srst, tmp);
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}
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} else {
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if (pol_ce) {
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SigSpec tmp = module->Not(NEW_ID, sig_ce, false, src);
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sig_srst = cell->module->Or(NEW_ID, sig_srst, tmp, false, src);
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SigSpec tmp = patcher.Not(NEW_ID, sig_ce);
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sig_srst = patcher.Or(NEW_ID, sig_srst, tmp);
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} else {
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sig_srst = cell->module->Or(NEW_ID, sig_srst, sig_ce, false, src);
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sig_srst = patcher.Or(NEW_ID, sig_srst, sig_ce);
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}
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}
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} else {
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if (pol_srst) {
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if (pol_ce) {
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sig_srst = cell->module->AndGate(NEW_ID, sig_srst, sig_ce, src);
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sig_srst = patcher.AndGate(NEW_ID, sig_srst, sig_ce);
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} else {
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sig_srst = cell->module->AndnotGate(NEW_ID, sig_srst, sig_ce, src);
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sig_srst = patcher.AndnotGate(NEW_ID, sig_srst, sig_ce);
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}
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} else {
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if (pol_ce) {
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sig_srst = cell->module->OrnotGate(NEW_ID, sig_srst, sig_ce, src);
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sig_srst = patcher.OrnotGate(NEW_ID, sig_srst, sig_ce);
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} else {
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sig_srst = cell->module->OrGate(NEW_ID, sig_srst, sig_ce, src);
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sig_srst = patcher.OrGate(NEW_ID, sig_srst, sig_ce);
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}
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}
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}
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}
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patcher.commit_inheriting_src(cell);
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ce_over_srst = val;
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}
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@ -599,18 +592,19 @@ void FfData::unmap_ce() {
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if (has_srst && ce_over_srst)
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unmap_srst();
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std::string src = ff_src(*this);
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RTLIL::Patch patcher(module);
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if (!is_fine) {
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if (pol_ce)
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sig_d = module->Mux(NEW_ID, sig_q, sig_d, sig_ce, src);
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sig_d = patcher.Mux(NEW_ID, sig_q, sig_d, sig_ce);
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else
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sig_d = module->Mux(NEW_ID, sig_d, sig_q, sig_ce, src);
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sig_d = patcher.Mux(NEW_ID, sig_d, sig_q, sig_ce);
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} else {
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if (pol_ce)
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sig_d = module->MuxGate(NEW_ID, sig_q, sig_d, sig_ce, src);
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sig_d = patcher.MuxGate(NEW_ID, sig_q, sig_d, sig_ce);
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else
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sig_d = module->MuxGate(NEW_ID, sig_d, sig_q, sig_ce, src);
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sig_d = patcher.MuxGate(NEW_ID, sig_d, sig_q, sig_ce);
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}
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patcher.commit_inheriting_src(cell);
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has_ce = false;
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}
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@ -620,18 +614,19 @@ void FfData::unmap_srst() {
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if (has_ce && !ce_over_srst)
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unmap_ce();
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std::string src = ff_src(*this);
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RTLIL::Patch patcher(module);
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if (!is_fine) {
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if (pol_srst)
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sig_d = module->Mux(NEW_ID, sig_d, val_srst, sig_srst, src);
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sig_d = patcher.Mux(NEW_ID, sig_d, val_srst, sig_srst);
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else
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sig_d = module->Mux(NEW_ID, val_srst, sig_d, sig_srst, src);
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sig_d = patcher.Mux(NEW_ID, val_srst, sig_d, sig_srst);
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} else {
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if (pol_srst)
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sig_d = module->MuxGate(NEW_ID, sig_d, val_srst[0], sig_srst, src);
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sig_d = patcher.MuxGate(NEW_ID, sig_d, val_srst[0], sig_srst);
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else
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sig_d = module->MuxGate(NEW_ID, val_srst[0], sig_d, sig_srst, src);
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sig_d = patcher.MuxGate(NEW_ID, val_srst[0], sig_d, sig_srst);
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}
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patcher.commit_inheriting_src(cell);
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has_srst = false;
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}
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@ -45,50 +45,7 @@ RTLIL::Wire *RTLIL::Patch::addWire(RTLIL::IdString name, const RTLIL::Wire *othe
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return wire;
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}
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struct SrcCollector {
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pool<Cell*> to_do;
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pool<Cell*> done;
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pool<string> src;
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void collect_src(Cell* old_cell) {
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if (done.count(old_cell))
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return;
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done.insert(old_cell);
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log_debug("collect %s\n", old_cell->name);
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src.insert(old_cell->get_src_attribute());
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std::vector<Cell*> input_cells = {};
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for (auto [port_name, sig] : old_cell->connections()) {
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auto dir = old_cell->port_dir(port_name);
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log_assert(dir != PD_UNKNOWN);
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if (dir == PD_INPUT || dir == PD_INOUT) {
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if (sig.size() && sig.is_wire()) {
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Wire* in_wire = sig.as_wire();
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if (!in_wire->module)
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input_cells.push_back(in_wire->driverCell());
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// if (!leaves.count(in_wire))
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}
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}
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}
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for (auto input : input_cells)
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collect_src(input);
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}
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void collect_src(SigSpec old_sig) {
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log_debug("collect %s\n", log_signal(old_sig));
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for (auto bit : old_sig) {
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if (bit.is_wire() && bit.wire->module) {
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log_assert(bit.wire->driverCell_);
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to_do.insert(bit.wire->driverCell_);
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}
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}
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for (auto cell : to_do)
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collect_src(cell);
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}
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};
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void Patch::gc(Cell* old_cell, bool track) {
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void Patch::gc(Cell* old_cell, bool track, pool<string>* src_pool) {
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log_debug("gc %s\n", old_cell->name);
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if (old_cell->type.in(ID($input_port), ID($output_port), ID($public)))
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return;
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@ -128,9 +85,14 @@ void Patch::gc(Cell* old_cell, bool track) {
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// caller's current iteration variable and won't be re-encountered.
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if (track && removed_cells)
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removed_cells->insert(old_cell);
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// The cell about to be removed contributes its src so all the cells gc'd
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// in this patch (top-level + input cone) get merged into the new cells'
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// src — that's the "transfer src automatically" guarantee.
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if (src_pool)
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src_pool->insert(old_cell->get_src_attribute());
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old_cell->module->remove(old_cell);
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for (auto input : inputs)
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gc(input, /*track=*/true);
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gc(input, /*track=*/true, src_pool);
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}
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Wire* Patch::commit_wire(std::unique_ptr<Wire> wire) {
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@ -172,26 +134,6 @@ void Patch::patch(Cell* old_cell, const std::vector<std::pair<IdString, SigSpec>
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old_sigs.push_back(old_sig);
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}
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SrcCollector collector;
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for (auto &old_sig : old_sigs)
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collector.collect_src(old_sig);
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// The collector should only ever pick up old_cell — the cell whose
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// outputs are being patched. If a future change to collect_src ever
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// starts walking the fanout or input cone of foreign cells, this
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// assertion fires so we notice instead of silently smearing src
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// strings across unrelated cells.
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for (auto *c : collector.done)
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log_assert(c == old_cell);
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// For "merge into existing cell" patches (e.g. opt_merge), also pull
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// in the keep-cell's pre-existing src so the merged cell carries both
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// source locations.
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if (merge_src_into)
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collector.src.insert(merge_src_into->get_src_attribute());
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std::string src_str = AttrObject::strpool_attribute_to_str(collector.src);
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// Record leaves (existing wires consumed as inputs by the new cells) so
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// gc() stops at them. Detected via bit.wire->module being non-null:
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// uncommitted wires belong to no module yet.
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@ -208,19 +150,18 @@ void Patch::patch(Cell* old_cell, const std::vector<std::pair<IdString, SigSpec>
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}
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// Commit new cells/wires first so new_sig becomes a driven signal in the
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// signorm index before we merge.
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// signorm index before we merge. Track raw pointers so we can update
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// their src attribute after gc finishes collecting from removed cells.
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std::vector<Cell*> committed_new_cells;
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committed_new_cells.reserve(cells_.size());
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for (auto& cell: cells_) {
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cell->set_src_attribute(src_str);
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cell->fixup_parameters();
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commit_cell(std::move(cell));
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committed_new_cells.push_back(commit_cell(std::move(cell)));
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}
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for (auto& wire: wires_)
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commit_wire(std::move(wire));
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if (merge_src_into)
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merge_src_into->set_src_attribute(src_str);
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// Now drop old_cell's drivers so old_sigs are undriven, then merge each
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// into its new_sig. connect_incremental updates sigmap and re-normalizes
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// fanout consumers in place — no full sigNormalize needed.
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@ -233,10 +174,37 @@ void Patch::patch(Cell* old_cell, const std::vector<std::pair<IdString, SigSpec>
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mod->connect_incremental(old_sigs[i], new_sig);
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}
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gc(old_cell);
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// gc removes old_cell AND any newly-dead input-cone cells, contributing
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// each removed cell's src into the pool. The merged-into cell (e.g. an
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// opt_merge keep_cell) and any caller-bequeathed pool entries also get
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// folded in here.
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pool<string> src_pool;
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if (merge_src_into)
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src_pool.insert(merge_src_into->get_src_attribute());
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gc(old_cell, /*track=*/false, &src_pool);
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std::string src_str = AttrObject::strpool_attribute_to_str(src_pool);
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for (Cell* c : committed_new_cells)
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c->set_src_attribute(src_str);
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if (merge_src_into)
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merge_src_into->set_src_attribute(src_str);
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cells_.clear();
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wires_.clear();
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leaves.clear();
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}
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void Patch::commit_inheriting_src(Cell* src_source) {
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std::string src = src_source ? src_source->get_src_attribute() : std::string();
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for (auto& cell : cells_) {
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cell->set_src_attribute(src);
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cell->fixup_parameters();
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commit_cell(std::move(cell));
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}
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for (auto& wire : wires_)
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commit_wire(std::move(wire));
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cells_.clear();
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wires_.clear();
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}
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YOSYS_NAMESPACE_END
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@ -10,7 +10,7 @@ YOSYS_NAMESPACE_BEGIN
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struct RTLIL::Patch : public CellAdderMixin<RTLIL::Patch>
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{
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private:
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void gc(Cell* old_cell, bool track = false);
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void gc(Cell* old_cell, bool track = false, pool<std::string>* src_pool = nullptr);
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protected:
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void add(RTLIL::Wire *wire);
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@ -42,6 +42,14 @@ public:
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// merge_src_into. Any new cells in cells_ also receive the combined src.
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void patch(Cell* old_cell, IdString old_port, SigSpec new_sig, Cell* merge_src_into);
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void patch(Cell* old_cell, const std::vector<std::pair<IdString, SigSpec>> &port_replacements, Cell* merge_src_into);
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// Flush staged cells_ / wires_ into the module without doing any
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// connect_incremental or gc. Each committed cell's src attribute is
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// pulled from `src_source` (typically the cell that's being expanded /
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// unmapped into the staged helpers, so source-location tracking carries
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// through transparently). Pass nullptr for src_source if the staged
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// helpers have no natural ancestor.
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void commit_inheriting_src(Cell* src_source);
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RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);
|
||||
RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue