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opt_expr: cleanup
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5cdb189ea0
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@ -629,12 +629,9 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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replace_cell(assign_map, module, cell, "xor_buffer", ID::Y, sig_a);
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} else {
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RTLIL::Patch patcher(module, &assign_map);
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Wire* y = patcher.addWire(NEW_ID, 1);
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Cell* new_cell = cell->type == ID($xor) ? patcher.addNot(NEW_ID, sig_a, y) : patcher.addNotGate(NEW_ID, sig_a, y);
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SigSpec sig_y = y;
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SigSpec sig_y = cell->type == ID($xor) ? patcher.Not(NEW_ID, sig_a) : (SigSpec)patcher.NotGate(NEW_ID, sig_a);
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int width = cell->type == ID($xor) ? cell->getParam(ID::Y_WIDTH).as_int() : 1;
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sig_y.append(RTLIL::Const(State::S0, width-1));
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(void)new_cell;
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patcher.patch(cell, ID::Y, sig_y);
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}
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goto next_cell;
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