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15849 Commits

Author SHA1 Message Date
Akash Levy 027a4cec13
Merge branch 'YosysHQ:main' into main 2025-03-31 14:07:26 -07:00
Akash Levy d743a18ea3 Fix extract_reduce infinite loop 2025-03-31 12:36:43 -07:00
Emil J 3a1255546a
Merge pull request #4975 from YosysHQ/emil/opt_expr-cover-with-tests 
opt_expr: expand test coverage
 2025-03-31 20:13:16 +02:00
Emil J. Tywoniak 6194eb939d opt_expr: expand test coverage 2025-03-31 19:31:53 +02:00
Akash Levy f488b0e74c Add lut2bmux, annotate_unqcoef, and seed tests 2025-03-31 05:55:54 -07:00
Akash Levy 3f00e57076 Improve the naming for opt_reduce 2025-03-31 01:22:42 -07:00
Akash Levy f72d27fae0 Robustness fixes 2025-03-30 22:23:21 -07:00
Akash Levy 984c6357ba Add -word mode to lut2mux and improve the naming 2025-03-30 17:54:35 -07:00
Akash Levy 161ff0fa3f Add muxmode pass and tests 2025-03-30 17:54:18 -07:00
Akash Levy dacd882383 Remove selectconst 2025-03-28 17:40:40 -07:00
github-actions[bot] 314842d2a0 Bump version 2025-03-29 00:22:03 +00:00
Akash Levy 4d7581bc0b
Merge pull request #77 from williamzhu17/breaksop-tests 
Added breaksop tests
 2025-03-28 15:58:56 -07:00
williamzhu17 1628a22195 added extra test for multiple sops 2025-03-28 14:58:17 -07:00
Akash Levy 1a5415b5a2
Merge branch 'YosysHQ:main' into main 2025-03-28 14:56:36 -07:00
williamzhu17 a4a4544223 Merge branch 'breaksop-tests' of github.com:williamzhu17/yosys into breaksop-tests 2025-03-28 14:54:21 -07:00
williamzhu17 727c6a51be added comment about one test case 2025-03-28 14:54:00 -07:00
William Zhu ddb621d011
Merge branch 'Silimate:main' into breaksop-tests 2025-03-28 14:50:35 -07:00
williamzhu17 5987454eac added breaksop-tests 2025-03-28 14:50:02 -07:00
Akash Levy df8581a741
Merge pull request #76 from williamzhu17/breakreduce-tests 
Add breakreduce Tests
 2025-03-28 11:52:54 -07:00
williamzhu17 ebb7a1b548 added reduce XNOR test cases 2025-03-28 10:52:56 -07:00
williamzhu17 baaa90993e added breakreduce tests 2025-03-28 10:43:10 -07:00
Emil J 1b25e1cee0
Merge pull request #4942 from Anhijkt/fix-ice40dsp 
ice40_dsp: fix log_assert issue
 2025-03-28 13:32:17 +01:00
Emil J b2816b22c5
Merge pull request #4965 from YosysHQ/krys/gen_err_files 
More *.err files in test failures
 2025-03-28 13:08:44 +01:00
Emil J c672e442c5
Merge pull request #4966 from yrabbit/primitives 
Gowin. Remove unnecessary modules
 2025-03-28 13:07:09 +01:00
Emil J ec8b745929
Merge pull request #4733 from antmicro/fix-setundef-pass-for-params 
Fix setting bits of parameters in setundef pass
 2025-03-28 13:06:04 +01:00
Akash Levy 7bbd7ef3eb
Merge pull request #75 from williamzhu17/test-yosys-fix 
Fixes for the test-yosys
 2025-03-27 17:23:49 -07:00
williamzhu17 7208e05bdf fixes for the yosys test 2025-03-27 17:19:08 -07:00
Akash Levy 65c41e73cd
Merge pull request #74 from williamzhu17/mux-and-or-not 
Mux andnot + ornot optimization tests
 2025-03-27 17:14:28 -07:00
williamzhu17 770eecb4f7 code cleanup 2025-03-27 15:27:15 -07:00
William Zhu eefdcbfe81 added ornot tests 2025-03-27 15:23:18 -07:00
William Zhu 7f04cc6755 removed dump verilog 2025-03-27 15:14:28 -07:00
William Zhu 8666e9ae45 tests for mux_andnot 2025-03-27 15:13:57 -07:00
Akash Levy 61b0a5fad2
Merge pull request #73 from williamzhu17/opt_expand_test 
opt_expand test cases
 2025-03-27 13:54:47 -07:00
YRabbit c37db637c7 Gowin. Remove unnecessary modules 
Primitives that are not planned for implementation for reasons of
belonging to old unsupported chips or representing composite complex IPs
rather than primitives are removed.
Also latches and large MUXes not planned for implementation.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-03-28 06:34:26 +10:00
William Zhu d493a55025 forgot to add some things to previous commit 2025-03-27 12:40:41 -07:00
William Zhu 3b8330c44f reverted some extra unneccessary checks 2025-03-27 12:40:21 -07:00
William Zhu a03553b54e added some extra comments and checks 2025-03-27 12:36:15 -07:00
William Zhu cc4c9c4eba first tests for opt_expand 2025-03-27 12:31:37 -07:00
Akash Levy 3d13f7aae2 Bump to latest 2025-03-26 14:56:10 -07:00
KrystalDelusion 5b6b3d01bf
Update gen-tests-makefile.sh 
Keep file extensions so that e.g. tribuf.ys and tribuf.sh don't try to output to the same log file.
 2025-03-27 10:33:51 +13:00
KrystalDelusion 8a68ae6023
Update gen-tests-makefile.sh 2025-03-27 10:10:49 +13:00
Anhijkt cb03a1ec21 ice40_dsp: fix test 2025-03-26 15:13:05 +02:00
Emil J b9131853ff
Merge pull request #4954 from YosysHQ/krys/abstract_default_val 
Fixes for abstract.cc
 2025-03-26 10:40:37 +01:00
Akash Levy d2028feefe Set Verific flags via -cfg instead of in Yosys 2025-03-25 22:41:06 -07:00
github-actions[bot] d3aec12fe9 Bump version 2025-03-26 00:22:20 +00:00
Emil J ea74ad33a5
Merge pull request #4961 from YosysHQ/emil/cutpoint-typo 
cutpoint: fix typo
 2025-03-25 21:30:29 +01:00
Emil J af9ad51a0a
Merge pull request #4960 from stashcroft/fix-32-bit-builds 
Make 32-bit tests pass
 2025-03-25 18:44:44 +01:00
Emil J. Tywoniak 4991ed9d4b cutpoint: fix typo 2025-03-25 18:10:47 +01:00
Scott Ashcroft 518986d45c Make cxxrtl tests work on 32-bit by using __builtin_clzll when needed 2025-03-25 13:12:04 +00:00
Scott Ashcroft 04bbd4e7e2 Make all vector-size related integer params in $print sim model signed 
This fixes iverilog crashes on 32-bit, similar to 95944eb for $mem.
 2025-03-25 13:08:49 +00:00