mirror of https://github.com/YosysHQ/yosys.git
Improve the naming for opt_reduce
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f72d27fae0
commit
3f00e57076
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@ -128,13 +128,14 @@ struct OptReduceWorker
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if (this_s.size() > 1)
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{
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RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID, ID($reduce_or));
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RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID2_SUFFIX("reduce_or"), ID($reduce_or)); // SILIMATE: Improve the naming
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reduce_or_cell->setPort(ID::A, this_s);
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reduce_or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
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reduce_or_cell->parameters[ID::A_WIDTH] = RTLIL::Const(this_s.size());
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reduce_or_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
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reduce_or_cell->set_src_attribute(cell->get_src_attribute()); // SILIMATE: Improve the naming
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RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID);
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RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID2_SUFFIX("reduce_or_wire")); // SILIMATE: Improve the naming
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this_s = RTLIL::SigSpec(reduce_or_wire);
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reduce_or_cell->setPort(ID::Y, this_s);
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}
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