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Add -word mode to lut2mux and improve the naming

This commit is contained in:
Akash Levy 2025-03-30 17:54:35 -07:00
parent 161ff0fa3f
commit 984c6357ba
1 changed files with 26 additions and 14 deletions
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40
passes/techmap/lut2mux.cc
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@ -23,7 +23,7 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
int lut2mux(Cell *cell)
int lut2mux(Cell *cell, bool word_mode)
{
SigSpec sig_a = cell->getPort(ID::A);
SigSpec sig_y = cell->getPort(ID::Y);
@ -32,22 +32,28 @@ int lut2mux(Cell *cell)
if (GetSize(sig_a) == 1)
{
cell->module->addMuxGate(NEW_ID, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y);
if (!word_mode)
cell->module->addMuxGate(NEW_ID2, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y, cell->get_src_attribute()); // SILIMATE: Improve the naming
else
cell->module->addMux(NEW_ID2, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y, cell->get_src_attribute()); // SILIMATE: Improve the naming
}
else
{
SigSpec sig_a_hi = sig_a[GetSize(sig_a)-1];
SigSpec sig_a_lo = sig_a.extract(0, GetSize(sig_a)-1);
SigSpec sig_y1 = cell->module->addWire(NEW_ID);
SigSpec sig_y2 = cell->module->addWire(NEW_ID);
SigSpec sig_y1 = cell->module->addWire(NEW_ID2); // SILIMATE: Improve the naming
SigSpec sig_y2 = cell->module->addWire(NEW_ID2); // SILIMATE: Improve the naming
Const lut1 = lut.extract(0, GetSize(lut)/2);
Const lut2 = lut.extract(GetSize(lut)/2, GetSize(lut)/2);
count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y1, lut1));
count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y2, lut2));
count += lut2mux(cell->module->addLut(NEW_ID2, sig_a_lo, sig_y1, lut1), word_mode); // SILIMATE: Improve the naming
count += lut2mux(cell->module->addLut(NEW_ID2, sig_a_lo, sig_y2, lut2), word_mode); // SILIMATE: Improve the naming
cell->module->addMuxGate(NEW_ID, sig_y1, sig_y2, sig_a_hi, sig_y);
if (!word_mode)
cell->module->addMuxGate(NEW_ID2, sig_y1, sig_y2, sig_a_hi, sig_y, cell->get_src_attribute()); // SILIMATE: Improve the naming
else
cell->module->addMux(NEW_ID2, sig_y1, sig_y2, sig_a_hi, sig_y, cell->get_src_attribute()); // SILIMATE: Improve the naming
}
cell->module->remove(cell);
@ -55,26 +61,32 @@ int lut2mux(Cell *cell)
}
struct Lut2muxPass : public Pass {
Lut2muxPass() : Pass("lut2mux", "convert $lut to $_MUX_") { }
Lut2muxPass() : Pass("lut2mux", "convert $lut to $mux/$_MUX_") { }
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" lut2mux [options] [selection]\n");
log("\n");
log("This pass converts $lut cells to $_MUX_ gates.\n");
log("This pass converts $lut cells to $mux/$_MUX_ gates.\n");
log("\n");
log(" -word\n");
log(" Convert $lut cells with a single input to word-level $mux gates.\n");
log(" The default is to convert them to bit-level $_MUX_ gates.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing LUT2MUX pass (convert $lut to $_MUX_).\n");
log_header(design, "Executing LUT2MUX pass (convert $lut to $mux/$_MUX_).\n");
size_t argidx;
bool word_mode = false;
for (argidx = 1; argidx < args.size(); argidx++)
{
// if (args[argidx] == "-v") {
// continue;
// }
if (args[argidx] == "-word") {
word_mode = true;
continue;
}
break;
}
extra_args(args, argidx, design);
@ -83,7 +95,7 @@ struct Lut2muxPass : public Pass {
for (auto cell : module->selected_cells()) {
if (cell->type == ID($lut)) {
IdString cell_name = cell->name;
int count = lut2mux(cell);
int count = lut2mux(cell, word_mode);
log("Converted %s.%s to %d MUX cells.\n", log_id(module), log_id(cell_name), count);
}
}