mirror of https://github.com/YosysHQ/yosys.git
Add muxmode pass and tests
This commit is contained in:
Akash Levy
parent
dacd882383
commit
161ff0fa3f
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@ -290,8 +290,8 @@ inline std::string removeNumericSuffix(const std::string& str) {
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return str; // Return unchanged if no numeric suffix found
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}
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#define NEW_ID2 module->uniquify(removeNumericSuffix(cell->name.str()))
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#define NEW_ID2_SUFFIX(suffix) module->uniquify(cell->name.str() + "_" + suffix)
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#define NEW_ID2 cell->module->uniquify(removeNumericSuffix(cell->name.str()))
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#define NEW_ID2_SUFFIX(suffix) cell->module->uniquify(cell->name.str() + "_" + suffix)
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#define NEW_ID3 module->uniquify(cell_name.str())
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#define NEW_ID3_SUFFIX(suffix) module->uniquify(cell_name.str() + "_" + suffix)
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#define NEW_ID4 module->uniquify(name.str())
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@ -21,3 +21,14 @@ PEEPOPT_PATTERN = passes/silimate/peepopt_expand.pmg
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passes/silimate/peepopt_expand.h: passes/pmgen/pmgen.py $(PEEPOPT_PATTERN)
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$(P) mkdir -p $(dir $@) && $(PYTHON_EXECUTABLE) $< -o $@ -p peepopt $(filter-out $<,$^)
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OBJS += passes/silimate/muxmode.o
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GENFILES += passes/silimate/peepopt_muxmode.h
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passes/silimate/muxmode.o: passes/silimate/peepopt_muxmode.h
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$(eval $(call add_extra_objs,passes/silimate/peepopt_muxmode.h))
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PEEPOPT_PATTERN = passes/silimate/peepopt_muxmode.pmg
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PEEPOPT_PATTERN += passes/silimate/peepopt_muxinvprop.pmg
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passes/silimate/peepopt_muxmode.h: passes/pmgen/pmgen.py $(PEEPOPT_PATTERN)
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$(P) mkdir -p $(dir $@) && $(PYTHON_EXECUTABLE) $< -o $@ -p peepopt $(filter-out $<,$^)
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@ -0,0 +1,64 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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* Akash Levy <akash@silimate.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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bool did_something;
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#include "passes/silimate/peepopt_muxmode.h"
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struct MuxmodePass : public Pass {
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MuxmodePass() : Pass("muxmode", "convert primitives to muxes") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" muxmode [selection]\n");
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log("\n");
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log("This pass makes muxes of 1-bit primitives having an input coming from a mux.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing MUXMODE pass (make muxes from 1-bit primitives).\n");
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size_t argidx = 1;
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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did_something = true;
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for (int i = 0; did_something; i++)
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{
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log("ITERATION %d OF MUXMODE\n", i);
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did_something = false;
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peepopt_pm pm(module);
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pm.setup(module->selected_cells());
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pm.run_muxmode();
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pm.run_muxinvprop();
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}
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}
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}
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} PeepoptPass;
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PRIVATE_NAMESPACE_END
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@ -0,0 +1,60 @@
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pattern muxinvprop
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//
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// Authored by Akash Levy of Silimate, Inc. under ISC license.
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//
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// Propagate inverters from mux outputs to inputs
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//
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// ~ (S ? A : B) ==> S ? ~A : ~B
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//
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state <SigSpec> mux_a mux_b mux_y inv_a inv_y
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match mux_gate
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// Select mux
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select mux_gate->type.in($mux)
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set mux_a port(mux_gate, \A)
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set mux_b port(mux_gate, \B)
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set mux_y port(mux_gate, \Y)
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endmatch
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code
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// Fanout of each MUX gate Y bit should be 1 (no bit-split)
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if (nusers(mux_y) != 2)
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reject;
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endcode
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match inv_gate
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// Select inverter
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select inv_gate->type.in($not)
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set inv_a port(inv_gate, \A)
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set inv_y port(inv_gate, \Y)
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// Connection
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index <SigSpec> port(inv_gate, \A) === mux_y
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endmatch
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code mux_a mux_b mux_y inv_a inv_y
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// Disconnect all ports
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mux_gate->unsetPort(\A);
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mux_gate->unsetPort(\B);
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mux_gate->unsetPort(\Y);
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inv_gate->unsetPort(\A);
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inv_gate->unsetPort(\Y);
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// Set cell to mux_gate for naming
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Cell *cell = mux_gate;
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// Set new ports
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mux_gate->setPort(\A, module->Not(NEW_ID2_SUFFIX("not_a"), mux_a, false, mux_gate->get_src_attribute()));
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mux_gate->setPort(\B, module->Not(NEW_ID2_SUFFIX("not_b"), mux_b, false, mux_gate->get_src_attribute()));
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mux_gate->setPort(\Y, inv_y);
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// Rename MUX gate for formal
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module->rename(mux_gate, NEW_ID2_SUFFIX("not"));
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// Log, fixup, accept
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log("muxinvprop pattern in %s: mux=%s, not=%s\n", log_id(module), log_id(mux_gate), log_id(inv_gate));
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autoremove(inv_gate);
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did_something = true;
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accept;
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endcode
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@ -0,0 +1,77 @@
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pattern muxmode
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//
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// Authored by Akash Levy of Silimate, Inc. under ISC license.
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//
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// Make muxes of 1-bit primitives having an input coming from a mux
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//
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// A & B ==> A ? B : 0
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// A | B ==> A ? 1 : B
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// A ^ B ==> A ? ~B : B
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// A ^~ B ==> A ? B : ~B
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//
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state <SigSpec> mux_y prim_a prim_b
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match mux_gate
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// Select MUX that connects to one of the primitives' inputs
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select mux_gate->type.in($mux)
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filter param(mux_gate, \WIDTH) == 1
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set mux_y port(mux_gate, \Y)
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endmatch
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match prim_gate
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// Select AND/OR (not XOR/XNOR for now)
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select prim_gate->type.in($and, $or)
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filter param(prim_gate, \A_WIDTH) == 1
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filter param(prim_gate, \B_WIDTH) == 1
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// Set ports, allowing A and B to be swapped
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choice <IdString> A {\A, \B}
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define <IdString> B (A == \A ? \B : \A)
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set prim_a port(prim_gate, A)
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set prim_b port(prim_gate, B)
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// Connection
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index <SigSpec> port(prim_gate, B) === mux_y
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endmatch
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code mux_y prim_a prim_b
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// Unset ports/params of primitive
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prim_gate->unsetPort(\A);
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prim_gate->unsetPort(\B);
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prim_gate->unsetParam(\A_WIDTH);
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prim_gate->unsetParam(\A_SIGNED);
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prim_gate->unsetParam(\B_WIDTH);
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prim_gate->unsetParam(\B_SIGNED);
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prim_gate->unsetParam(\Y_WIDTH);
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// Set mux's S port to primitive's A port
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prim_gate->setPort(\S, prim_a);
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// Set cell to be prim_gate for naming
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Cell *cell = prim_gate;
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// Set mux inputs
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if (prim_gate->type == $and) {
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prim_gate->setPort(\A, State::S0);
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prim_gate->setPort(\B, prim_b);
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} else if (prim_gate->type == $or) {
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prim_gate->setPort(\A, prim_b);
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prim_gate->setPort(\B, State::S1);
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} else if (prim_gate->type == $xor) {
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prim_gate->setPort(\A, prim_b);
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prim_gate->setPort(\B, module->Not(NEW_ID2, prim_b, false, cell->get_src_attribute()));
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} else if (prim_gate->type == $xnor) {
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prim_gate->setPort(\A, module->Not(NEW_ID2, prim_b, false, cell->get_src_attribute()));
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prim_gate->setPort(\B, prim_b);
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} else {
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log_abort();
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}
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// Log, fixup type and parameters, accept
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log("muxmode pattern in %s: mux=%s, prim=%s, primtype=%s\n", log_id(module), log_id(mux_gate), log_id(prim_gate), log_id(prim_gate->type));
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prim_gate->type = $mux;
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prim_gate->fixup_parameters();
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did_something = true;
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accept;
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endcode
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@ -0,0 +1,77 @@
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log -header "Simple positive case with 4-long mux chain and 1 inverted component"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [3:0] s,
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input wire [3:0] b,
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input wire a,
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output wire y
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);
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assign y = s[0] ? b[0] : (s[1] ? b[1] : ~(s[2] ? b[2] : (s[3] ? b[3] : a)));
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endmodule
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EOF
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check -assert
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# # Show pre
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# autoname
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# write_json pre.json
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# exec -- netlistsvg pre.json -o pre.svg
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# Check equivalence after muxmode
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equiv_opt -assert muxmode
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 4 t:$mux
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select -assert-count 3 t:$not
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# # Show post
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# autoname
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# write_json post.json
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# exec -- netlistsvg post.json -o post.svg
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design -reset
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log -pop
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log -header "Simple negative case with 4-long mux chain and 1 inverted fo2 component"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [3:0] s,
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input wire [3:0] b,
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input wire a,
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output wire y,
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output wire y2
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);
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wire m;
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assign m = s[2] ? b[2] : (s[3] ? b[3] : a);
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assign y2 = m;
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assign y = s[0] ? b[0] : (s[1] ? b[1] : ~m);
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endmodule
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EOF
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check -assert
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# # Show pre
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# autoname
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# write_json pre.json
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# exec -- netlistsvg pre.json -o pre.svg
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# Check equivalence after muxmode
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equiv_opt -assert muxmode
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 4 t:$mux
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select -assert-count 1 t:$not
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# # Show post
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# autoname
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# write_json post.json
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# exec -- netlistsvg post.json -o post.svg
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design -reset
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log -pop
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@ -0,0 +1,362 @@
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log -header "Simple positive case with AND"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire s1,
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input wire s2,
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input wire a,
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input wire b,
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input wire c,
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input wire d,
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output wire x
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);
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wire m1, m2;
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assign m1 = s1 ? b : a;
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assign m2 = m1 & c;
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assign x = s2 ? m2 : d;
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endmodule
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EOF
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check -assert
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# # Show pre
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# autoname
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# write_json pre.json
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# exec -- netlistsvg pre.json -o pre.svg
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# Check equivalence after muxmode
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equiv_opt -assert muxmode
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 3 t:$mux
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# # Show post
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# autoname
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# write_json post.json
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# exec -- netlistsvg post.json -o post.svg
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design -reset
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log -pop
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log -header "Simple positive case with AND (order reversed)"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire s1,
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input wire s2,
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input wire a,
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input wire b,
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input wire c,
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input wire d,
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output wire x
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);
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wire m1, m2;
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assign m1 = s1 ? b : a;
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assign m2 = c & m1;
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assign x = s2 ? m2 : d;
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endmodule
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EOF
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check -assert
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# # Show pre
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# autoname
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# write_json pre.json
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# exec -- netlistsvg pre.json -o pre.svg
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# Check equivalence after muxmode
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equiv_opt -assert muxmode
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 3 t:$mux
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# # Show post
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# autoname
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# write_json post.json
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# exec -- netlistsvg post.json -o post.svg
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design -reset
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log -pop
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log -header "Simple positive case with OR"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire s1,
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input wire s2,
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input wire a,
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input wire b,
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input wire c,
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input wire d,
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output wire x
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);
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wire m1, m2;
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assign m1 = s1 ? b : a;
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assign m2 = m1 | c;
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assign x = s2 ? m2 : d;
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endmodule
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EOF
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check -assert
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# # Show pre
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# autoname
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# write_json pre.json
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# exec -- netlistsvg pre.json -o pre.svg
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# Check equivalence after muxmode
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equiv_opt -assert muxmode
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 3 t:$mux
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# # Show post
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# autoname
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# write_json post.json
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# exec -- netlistsvg post.json -o post.svg
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design -reset
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log -pop
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log -header "Simple positive case with OR (order reversed)"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire s1,
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input wire s2,
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input wire a,
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input wire b,
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input wire c,
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input wire d,
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output wire x
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);
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wire m1, m2;
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assign m1 = s1 ? b : a;
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assign m2 = c | m1;
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assign x = s2 ? m2 : d;
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endmodule
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EOF
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check -assert
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# # Show pre
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# autoname
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# write_json pre.json
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# exec -- netlistsvg pre.json -o pre.svg
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# Check equivalence after muxmode
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equiv_opt -assert muxmode
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 3 t:$mux
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# # Show post
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# autoname
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# write_json post.json
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# exec -- netlistsvg post.json -o post.svg
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design -reset
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log -pop
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log -header "Simple negative case with multi-bit AND"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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||||
input wire [1:0] s1,
|
||||
input wire [1:0] s2,
|
||||
input wire [1:0] a,
|
||||
input wire [1:0] b,
|
||||
input wire [1:0] c,
|
||||
input wire [1:0] d,
|
||||
output wire [1:0] x
|
||||
);
|
||||
wire m1, m2;
|
||||
|
||||
assign m1 = s1 ? b : a;
|
||||
assign m2 = m1 & c;
|
||||
assign x = s2 ? m2 : d;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# # Show pre
|
||||
# autoname
|
||||
# write_json pre.json
|
||||
# exec -- netlistsvg pre.json -o pre.svg
|
||||
|
||||
# Check equivalence after muxmode
|
||||
equiv_opt -assert muxmode
|
||||
|
||||
# Check final design has correct number of gates
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$and
|
||||
select -assert-count 2 t:$mux
|
||||
|
||||
# # Show post
|
||||
# autoname
|
||||
# write_json post.json
|
||||
# exec -- netlistsvg post.json -o post.svg
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "Simple negative case with multi-bit AND (order reversed)"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [1:0] s1,
|
||||
input wire [1:0] s2,
|
||||
input wire [1:0] a,
|
||||
input wire [1:0] b,
|
||||
input wire [1:0] c,
|
||||
input wire [1:0] d,
|
||||
output wire [1:0] x
|
||||
);
|
||||
wire m1, m2;
|
||||
|
||||
assign m1 = s1 ? b : a;
|
||||
assign m2 = c & m1;
|
||||
assign x = s2 ? m2 : d;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# # Show pre
|
||||
# autoname
|
||||
# write_json pre.json
|
||||
# exec -- netlistsvg pre.json -o pre.svg
|
||||
|
||||
# Check equivalence after muxmode
|
||||
equiv_opt -assert muxmode
|
||||
|
||||
# Check final design has correct number of gates
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$and
|
||||
select -assert-count 2 t:$mux
|
||||
|
||||
# # Show post
|
||||
# autoname
|
||||
# write_json post.json
|
||||
# exec -- netlistsvg post.json -o post.svg
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "Simple negative case with OR"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [1:0] s1,
|
||||
input wire [1:0] s2,
|
||||
input wire [1:0] a,
|
||||
input wire [1:0] b,
|
||||
input wire [1:0] c,
|
||||
input wire [1:0] d,
|
||||
output wire [1:0] x
|
||||
);
|
||||
wire m1, m2;
|
||||
|
||||
assign m1 = s1 ? b : a;
|
||||
assign m2 = m1 | c;
|
||||
assign x = s2 ? m2 : d;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# # Show pre
|
||||
# autoname
|
||||
# write_json pre.json
|
||||
# exec -- netlistsvg pre.json -o pre.svg
|
||||
|
||||
# Check equivalence after muxmode
|
||||
equiv_opt -assert muxmode
|
||||
|
||||
# Check final design has correct number of gates
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$or
|
||||
select -assert-count 2 t:$mux
|
||||
|
||||
# # Show post
|
||||
# autoname
|
||||
# write_json post.json
|
||||
# exec -- netlistsvg post.json -o post.svg
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "Simple negative case with multi-bit OR (order reversed)"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [1:0] s1,
|
||||
input wire [1:0] s2,
|
||||
input wire [1:0] a,
|
||||
input wire [1:0] b,
|
||||
input wire [1:0] c,
|
||||
input wire [1:0] d,
|
||||
output wire [1:0] x
|
||||
);
|
||||
wire m1, m2;
|
||||
|
||||
assign m1 = s1 ? b : a;
|
||||
assign m2 = c | m1;
|
||||
assign x = s2 ? m2 : d;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# # Show pre
|
||||
# autoname
|
||||
# write_json pre.json
|
||||
# exec -- netlistsvg pre.json -o pre.svg
|
||||
|
||||
# Check equivalence after muxmode
|
||||
equiv_opt -assert muxmode
|
||||
|
||||
# Check final design has correct number of gates
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$or
|
||||
select -assert-count 2 t:$mux
|
||||
|
||||
# # Show post
|
||||
# autoname
|
||||
# write_json post.json
|
||||
# exec -- netlistsvg post.json -o post.svg
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
Loading…
Reference in New Issue