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Robustness fixes

This commit is contained in:
Akash Levy 2025-03-30 22:23:21 -07:00
parent 984c6357ba
commit f72d27fae0
2 changed files with 8 additions and 6 deletions
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11
passes/silimate/peepopt_muxmode.pmg
View File

@ -22,8 +22,6 @@ endmatch
match prim_gate
// Select AND/OR (not XOR/XNOR for now)
select prim_gate->type.in($and, $or)
filter param(prim_gate, \A_WIDTH) == 1
filter param(prim_gate, \B_WIDTH) == 1
// Set ports, allowing A and B to be swapped
choice <IdString> A {\A, \B}
@ -36,6 +34,12 @@ match prim_gate
endmatch
code mux_y prim_a prim_b
// Set cell to be prim_gate for naming
Cell *cell = prim_gate;
if (prim_gate->type == $mux)
reject;
// Unset ports/params of primitive
prim_gate->unsetPort(\A);
prim_gate->unsetPort(\B);
@ -48,9 +52,6 @@ code mux_y prim_a prim_b
// Set mux's S port to primitive's A port
prim_gate->setPort(\S, prim_a);
// Set cell to be prim_gate for naming
Cell *cell = prim_gate;
// Set mux inputs
if (prim_gate->type == $and) {
prim_gate->setPort(\A, State::S0);

3
passes/techmap/extract_reduce.cc
View File

@ -75,7 +75,8 @@ struct ExtractReducePass : public Pass
inline bool IsSingleBit(Cell* cell)
{
return (cell->hasParam(ID::WIDTH) && cell->getParam(ID::WIDTH).as_int() == 1) ||
(cell->getParam(ID::A_WIDTH).as_int() == 1 &&
(cell->hasParam(ID::A_WIDTH) &&
cell->getParam(ID::A_WIDTH).as_int() == 1 &&
cell->getParam(ID::B_WIDTH).as_int() == 1 &&
cell->getParam(ID::Y_WIDTH).as_int() == 1);
}