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Merge pull request #75 from williamzhu17/test-yosys-fix 

Fixes for the test-yosys
This commit is contained in:
Akash Levy 2025-03-27 17:23:49 -07:00 committed by GitHub
parent 65c41e73cd 7208e05bdf
commit 7bbd7ef3eb
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GPG Key ID: B5690EEEBB952194
2 changed files with 5 additions and 5 deletions
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8
tests/memlib/generate.py
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@ -1428,7 +1428,7 @@ endmodule
for (testname, reset_gate, rdwr, clk_en, add_logic) in [
("no_reset", "", "old", False, 0),
("gclken", "rst", "old", False, 0),
("ungated", "ungated", "old", False, 1), # muxes wren with rst
("ungated", "ungated", "old", False, 2), # muxes wren with rst
("gclken_ce", "rst", "old", True, 3), # AND to simulate CLK_EN
("grden", "rden && rst", "old", False, 1), # selects _clken, simulates _rden
("grden_ce", "rden && rst", "old", True, 4), # both of the above
@ -1473,9 +1473,9 @@ end"""
for (testname, reset_gate, defs, rdwr, add_logic) in [
("wr_byte", "", ["USE_SRST_BLOCKING"], "old", 0),
("trans_byte", "", ["USE_SRST_BLOCKING"], "new", 0),
("wr_rst_byte", "rst", ["USE_SRST"], "old", 2), # expected mux to emulate blocking
("rst_wr_byte", "rst", ["USE_SRST_BLOCKING"], "old", 2), # should use hardware blocking, doesn't
("rdenrst_wr_byte", "rden && rst", ["USE_SRST"], "old", 3),
("wr_rst_byte", "rst", ["USE_SRST"], "old", 3), # expected mux to emulate blocking
("rst_wr_byte", "rst", ["USE_SRST_BLOCKING"], "old", 3), # should use hardware blocking, doesn't
("rdenrst_wr_byte", "rden && rst", ["USE_SRST"], "old", 4),
]:
wordsloop = "for (i=0; i<WORDS; i=i+1)"
if rdwr == "old":

2
tests/various/check_4.ys
View File

@ -1,6 +1,6 @@
# loop involving the asynchronous reset on a memory port
design -reset
read -vlog2k <<EOF
read_verilog <<EOF
module top(input wire clk, input wire [3:0] addr, output reg [3:0] data);
reg [3:0] mem [15:0];
reg [5:0] i;