mirror of https://github.com/YosysHQ/yosys.git
first tests for opt_expand
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William Zhu
parent
3d13f7aae2
commit
cc4c9c4eba
1
Makefile
1
Makefile
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@ -946,6 +946,7 @@ SH_TEST_DIRS += tests/blif
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SH_TEST_DIRS += tests/memfile
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SH_TEST_DIRS += tests/fmt
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# SH_TEST_DIRS += tests/cxxrtl
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SH_TEST_DIRS += tests/silimate
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ifeq ($(ENABLE_FUNCTIONAL_TESTS),1)
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SH_TEST_DIRS += tests/functional
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endif
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@ -0,0 +1,225 @@
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log -header "Simple positive case"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire b,
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input wire c,
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output wire x
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);
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wire m;
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assign m = a | b;
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assign x = m & c;
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endmodule
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EOF
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check -assert
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equiv_opt -assert opt_expand
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design -load postopt
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select -assert-count 2 t:$and
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select -assert-count 1 t:$or
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design -reset
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log -pop
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log -header "No intermediate wire: (a | b) & c"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire b,
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input wire c,
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output wire x
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);
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assign x = (a | b) & c;
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endmodule
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EOF
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check -assert
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equiv_opt -assert opt_expand
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design -load postopt
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select -assert-count 2 t:$and
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select -assert-count 1 t:$or
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design -reset
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log -pop
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log -header "No intermediate wire flipped: c & (a | b)"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire b,
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input wire c,
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output wire x
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);
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assign x = c & (a | b);
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endmodule
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EOF
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check -assert
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equiv_opt -assert opt_expand
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design -load postopt
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select -assert-count 2 t:$and
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select -assert-count 1 t:$or
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design -reset
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log -pop
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log -header "Fanout from intermediate wire"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire b,
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input wire c,
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output wire m,
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output wire x
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);
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assign m = a | b;
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assign x = c & m;
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endmodule
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EOF
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check -assert
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equiv_opt -assert opt_expand
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design -load postopt
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select -assert-count 1 t:$and
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select -assert-count 1 t:$or
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design -reset
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log -pop
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log -header "Nested AND gate: ((a & b) | c) & d"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire b,
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input wire c,
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input wire d,
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output wire x
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);
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assign x = ((a & b) | c) & d;
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endmodule
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EOF
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check -assert
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equiv_opt -assert opt_expand
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design -load postopt
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select -assert-count 3 t:$and
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select -assert-count 1 t:$or
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design -reset
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log -pop
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log -header "Nested OR gate: ((a | b) | c) & d"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire b,
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input wire c,
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input wire d,
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output wire x
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);
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assign x = ((a | b) | c) & d;
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endmodule
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EOF
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check -assert
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equiv_opt -assert opt_expand
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design -load postopt
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select -assert-count 3 t:$and
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select -assert-count 2 t:$or
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design -reset
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log -pop
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log -header "With inverter: (~a | b) & c"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire b,
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input wire c,
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output wire x
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);
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assign x = (~a | b) & c;
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endmodule
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EOF
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check -assert
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equiv_opt -assert opt_expand
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design -load postopt
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select -assert-count 2 t:$and
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select -assert-count 1 t:$or
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design -reset
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log -pop
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log -header "Deeper nesting: ((a | b) & (c | d)) & e"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire b,
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input wire c,
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input wire d,
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input wire e,
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output wire x
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);
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assign x = ((a | b) & (c | d)) & e;
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endmodule
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EOF
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check -assert
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equiv_opt -assert opt_expand
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design -load postopt
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select -assert-count 4 t:$and
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select -assert-count 2 t:$or
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design -reset
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log -pop
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log -header "More inputs and nesting: ((a | b | c) & (d | e)) & f"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire b,
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input wire c,
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input wire d,
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input wire e,
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input wire f,
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output wire x
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);
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assign x = ((a | b | c) & (d | e)) & f;
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endmodule
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EOF
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check -assert
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equiv_opt -assert opt_expand
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design -load postopt
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select -assert-count 4 t:$and
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select -assert-count 3 t:$or
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design -reset
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log -pop
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@ -0,0 +1,6 @@
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#!/usr/bin/env bash
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set -e
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for x in *.ys; do
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echo "Running $x.."
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../../yosys -ql ${x%.ys}.log $x
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done
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