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added comment about one test case

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williamzhu17 2025-03-28 14:54:00 -07:00
parent 5987454eac
commit 727c6a51be
1 changed files with 3 additions and 0 deletions
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tests/silimate/breaksop.ys
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@ -114,6 +114,9 @@ select -assert-count 1 t:$sop
equiv_opt -assert breaksop
# Check final design has correct number of gates
# We only have one AND gate since breaksop turns the OR gate into an AND gate
# The inputs to this gate are inverted and the outputs are also inverted, so with
# DeMorgan's law, they are equivalent
design -load postopt
opt # Run opt to remove unneeded OR gate
select -assert-count 1 t:$reduce_and