mirror of https://github.com/YosysHQ/yosys.git
forgot to add some things to previous commit
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@ -15,10 +15,15 @@ module top (
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endmodule
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EOF
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check -assert
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# Check equivalence after opt_expand
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equiv_opt -assert opt_expand
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 2 t:$and
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select -assert-count 1 t:$or
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design -reset
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log -pop
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@ -38,7 +43,11 @@ module top (
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endmodule
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EOF
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check -assert
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# Check equivalence after opt_expand
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equiv_opt -assert opt_expand
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 2 t:$and
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select -assert-count 1 t:$or
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@ -62,7 +71,11 @@ module top (
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endmodule
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EOF
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check -assert
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# Check equivalence after opt_expand
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equiv_opt -assert opt_expand
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 2 t:$and
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select -assert-count 1 t:$or
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@ -89,7 +102,11 @@ module top (
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endmodule
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EOF
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check -assert
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# Check equivalence after opt_expand
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equiv_opt -assert opt_expand
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 1 t:$and
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select -assert-count 1 t:$or
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@ -114,7 +131,11 @@ module top (
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endmodule
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EOF
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check -assert
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# Check equivalence after opt_expand
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equiv_opt -assert opt_expand
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 3 t:$and
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select -assert-count 1 t:$or
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@ -139,7 +160,11 @@ module top (
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endmodule
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EOF
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check -assert
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# Check equivalence after opt_expand
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equiv_opt -assert opt_expand
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 3 t:$and
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select -assert-count 2 t:$or
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@ -163,7 +188,11 @@ module top (
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endmodule
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EOF
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check -assert
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# Check equivalence after opt_expand
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equiv_opt -assert opt_expand
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 2 t:$and
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select -assert-count 1 t:$or
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@ -189,7 +218,11 @@ module top (
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endmodule
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EOF
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check -assert
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# Check equivalence after opt_expand
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equiv_opt -assert opt_expand
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 4 t:$and
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select -assert-count 2 t:$or
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@ -216,7 +249,11 @@ module top (
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endmodule
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EOF
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check -assert
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# Check equivalence after opt_expand
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equiv_opt -assert opt_expand
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 4 t:$and
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select -assert-count 3 t:$or
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