mirror of https://github.com/YosysHQ/yosys.git
reverted some extra unneccessary checks
This commit is contained in:
parent
a03553b54e
commit
3b8330c44f
|
|
@ -15,19 +15,10 @@ module top (
|
|||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Ensure original design only has correct number of gates
|
||||
select -assert-count 1 t:$and
|
||||
select -assert-count 1 t:$or
|
||||
|
||||
# Check equivalence after opt_expand
|
||||
equiv_opt -assert opt_expand
|
||||
|
||||
# Check final design has correct number of gates
|
||||
design -load postopt
|
||||
select -assert-count 2 t:$and
|
||||
select -assert-count 1 t:$or
|
||||
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
|
@ -47,15 +38,7 @@ module top (
|
|||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Ensure original design only has correct number of gates
|
||||
select -assert-count 1 t:$and
|
||||
select -assert-count 1 t:$or
|
||||
|
||||
# Check equivalence after opt_expand
|
||||
equiv_opt -assert opt_expand
|
||||
|
||||
# Check final design has correct number of gates
|
||||
design -load postopt
|
||||
select -assert-count 2 t:$and
|
||||
select -assert-count 1 t:$or
|
||||
|
|
@ -79,15 +62,7 @@ module top (
|
|||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Ensure original design only has correct number of gates
|
||||
select -assert-count 1 t:$and
|
||||
select -assert-count 1 t:$or
|
||||
|
||||
# Check equivalence after opt_expand
|
||||
equiv_opt -assert opt_expand
|
||||
|
||||
# Check final design has correct number of gates
|
||||
design -load postopt
|
||||
select -assert-count 2 t:$and
|
||||
select -assert-count 1 t:$or
|
||||
|
|
@ -114,15 +89,7 @@ module top (
|
|||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Ensure original design only has correct number of gates
|
||||
select -assert-count 1 t:$and
|
||||
select -assert-count 1 t:$or
|
||||
|
||||
# Check equivalence after opt_expand
|
||||
equiv_opt -assert opt_expand
|
||||
|
||||
# Check final design has correct number of gates
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$and
|
||||
select -assert-count 1 t:$or
|
||||
|
|
@ -147,15 +114,7 @@ module top (
|
|||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Ensure original design only has correct number of gates
|
||||
select -assert-count 2 t:$and
|
||||
select -assert-count 1 t:$or
|
||||
|
||||
# Check equivalence after opt_expand
|
||||
equiv_opt -assert opt_expand
|
||||
|
||||
# Check final design has correct number of gates
|
||||
design -load postopt
|
||||
select -assert-count 3 t:$and
|
||||
select -assert-count 1 t:$or
|
||||
|
|
@ -180,15 +139,7 @@ module top (
|
|||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Ensure original design only has correct number of gates
|
||||
select -assert-count 1 t:$and
|
||||
select -assert-count 2 t:$or
|
||||
|
||||
# Check equivalence after opt_expand
|
||||
equiv_opt -assert opt_expand
|
||||
|
||||
# Check final design has correct number of gates
|
||||
design -load postopt
|
||||
select -assert-count 3 t:$and
|
||||
select -assert-count 2 t:$or
|
||||
|
|
@ -212,15 +163,7 @@ module top (
|
|||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Ensure original design only has correct number of gates
|
||||
select -assert-count 1 t:$and
|
||||
select -assert-count 1 t:$or
|
||||
|
||||
# Check equivalence after opt_expand
|
||||
equiv_opt -assert opt_expand
|
||||
|
||||
# Check final design has correct number of gates
|
||||
design -load postopt
|
||||
select -assert-count 2 t:$and
|
||||
select -assert-count 1 t:$or
|
||||
|
|
@ -246,15 +189,7 @@ module top (
|
|||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Ensure original design only has correct number of gates
|
||||
select -assert-count 2 t:$and
|
||||
select -assert-count 2 t:$or
|
||||
|
||||
# Check equivalence after opt_expand
|
||||
equiv_opt -assert opt_expand
|
||||
|
||||
# Check final design has correct number of gates
|
||||
design -load postopt
|
||||
select -assert-count 4 t:$and
|
||||
select -assert-count 2 t:$or
|
||||
|
|
@ -281,15 +216,7 @@ module top (
|
|||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
|
||||
# Ensure original design only has correct number of gates
|
||||
select -assert-count 2 t:$and
|
||||
select -assert-count 3 t:$or
|
||||
|
||||
# Check equivalence after opt_expand
|
||||
equiv_opt -assert opt_expand
|
||||
|
||||
# Check final design has correct number of gates
|
||||
design -load postopt
|
||||
select -assert-count 4 t:$and
|
||||
select -assert-count 3 t:$or
|
||||
|
|
|
|||
Loading…
Reference in New Issue