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0_examples_top.sch
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added poweramp_lcc
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2022-10-17 13:35:01 +02:00 |
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LCC_instances.sch
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"@path" will be expanded in symbols with the hierarchy path, so a fully qualified instance name is obtained with @path@name
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2022-11-01 12:54:43 +01:00 |
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LCC_instances.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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LM5134A.sch
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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LM5134A.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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MSA-2643.sch
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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Q1.sch
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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Q1.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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Q2.sch
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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Q2.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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TwoStageAmp.sch
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Added various procedures to select flat / hierarchical instances and re-route a terminal to a different net. reroute_inst -> change a pin connection, reroute_net -> change net updating all connected components. "xschem instances_to_net", "xschem instance_nodemap", "xschem instance_pin_coord" new query commands added. "xschem get expandlabel node" renamed to "xschem expandlabel node".
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2020-11-26 03:46:55 +01:00 |
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an2.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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and.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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ao21.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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buf.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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bus_keeper.sch
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annotation of voltage and currents in (nested) LCC instances
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2022-10-16 13:08:52 +02:00 |
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classD_amp.sch
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eliminated hide=true attribute for backannotation current/voltage texts (will be hidden anyway if no sim data is loaded)
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2022-10-24 17:28:39 +02:00 |
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classD_amp.sym
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added class D amplifier example
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2022-02-15 17:20:15 +01:00 |
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cmos_example.sch
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example update for op backannotation
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2022-10-22 11:05:30 +02:00 |
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cmos_example.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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cmos_inv.sch
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annotation of voltage and currents in (nested) LCC instances
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2022-10-16 13:08:52 +02:00 |
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cmos_inv.sym
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new find_inst_to_be_redrawn() implementation to recalculate area to be redrawn with/without show net names on symbol pins, simplified new_window() call in callback `x` command, code formatting in globals.c, added xschem get [xy]origin commands
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2021-12-03 19:15:07 +01:00 |
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diode_1.sch
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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diode_1.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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dlatch.sch
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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dlatch.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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doublepin.sch
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better check_unique_names() and hash_all_names() implementation (do not skip label instances or instances with no format attr). Button click focuses main drawing window even if autofocus_mainwindow is set to 0, to avoid losing keyboard focus forever if TAB is pressed.
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2022-10-12 11:56:02 +02:00 |
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doublepin.sym
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refactoring of netlister code
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2022-10-07 23:29:42 +02:00 |
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flop.sch
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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flop.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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greycnt.sch
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fix repeated character in RE, fix changed syntax in verilog example
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2020-11-28 20:08:40 +01:00 |
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greycnt.sym
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enable "preserve unchanged props" checkbutton in text edit prop dialog box
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2020-08-24 16:21:50 +02:00 |
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inv_bsource.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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lightning.sch
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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lm317.sch
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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lm317.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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lm324.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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lm337.sch
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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lm337.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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loading.sch
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look for inutile stimuli files in schematic directory instead of in simulation directory
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2022-09-13 18:53:17 +02:00 |
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loading.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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loading.vhdl
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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mos_power_ampli.sch
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avoid tcleval() of strings returned by translate2(), show currents of resistors and diodes when annotating.
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2022-11-04 13:35:06 +01:00 |
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mos_power_ampli.sym
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changed @schname to @schname_ext and added @schname that expands to the schematic name containing the instance, with no extension (no .sch)
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2022-08-10 08:38:49 +02:00 |
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mos_power_ampli_extracted.sch
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add test_extracted_netlist circuit example
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2022-02-18 15:11:44 +01:00 |
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mos_power_ampli_extracted.sym
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add test_extracted_netlist circuit example
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2022-02-18 15:11:44 +01:00 |
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nand.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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nand2.sch
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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nand2.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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nand3.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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nd2-1.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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ne555.sym
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doc updates (tutorial_use_existing_subckt.html)
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2022-10-22 22:52:55 +02:00 |
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not.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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nr2-1.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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or2.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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osc.sch
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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osc.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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plot_manipulation.sch
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graph axes in engineering notation (20u, 10p, 3k), fix an issue in graph panning with button1 mouse; ngspice:: get_current, get_voltage, get_diff_voltage, get_node embedded into xschem.tcl, to_eng tcl procedure to convert number to engineering form.
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2022-09-28 19:14:31 +02:00 |
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plot_manipulation.sym
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added plot_manipulation.sch example showing how to manually create an ngspice plot collecting data from multiple operating point sims. the syntax is so difficult to remember so i keep a working example available here.
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2020-12-09 13:53:32 +01:00 |
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poweramp.sch
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allow spice multipliers in numbers (20u, 10k, 20p) in graph expressions
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2022-09-22 21:12:40 +02:00 |
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poweramp.sym
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do a tcl evaluation of the "schematic" attribute of a symbol if the attribute is within a tcleval(...) expression. This way tcl variables/expressions can be used to determine the schematic to descend into when traversing/netlisting. example: schematic=tcleval(poweramp_${::mode}.sch).
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2021-06-17 00:25:39 +02:00 |
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poweramp_lcc.sch
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avoid tcleval() of strings returned by translate2(), show currents of resistors and diodes when annotating.
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2022-11-04 13:35:06 +01:00 |
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poweramp_lcc.sym
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added poweramp_lcc
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2022-10-17 13:35:01 +02:00 |
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poweramp_xyce.sch
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example schematics formatting
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2022-02-16 01:08:16 +01:00 |
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poweramp_xyce.sym
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xyce quircks/integration for ac analysis, refuse to stretch unscalable images, more example schematics
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2022-02-03 00:40:59 +01:00 |
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pump.sch
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look for inutile stimuli files in schematic directory instead of in simulation directory
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2022-09-13 18:53:17 +02:00 |
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pump.sym
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snap and grid entries will not annoyingly receive keyboard focus with TAB key
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2020-08-19 15:08:35 +02:00 |
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rcline.sch
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fix correct version syntax when saving in file
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2020-12-17 02:01:38 +01:00 |
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rcline.sym
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get_tok_value: even if called with "with_quotes=2" do not skip unescaped backslashes that are outside "quotes". Added dynamic netlisting test circuit in examples
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2020-10-23 23:17:55 +02:00 |
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real_capa.sch
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look for inutile stimuli files in schematic directory instead of in simulation directory
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2022-09-13 18:53:17 +02:00 |
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real_capa.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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rlc.sch
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remove "m=1" in xyce spice netlists as xyce does not handle m param. Translate spice_probe ".save" to xyce ".print tran", handle different hierarchical expansion of voltage/current nodes in xyce for hierarchical ammeter/spice_probe probes
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2020-12-17 18:26:46 +01:00 |
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rlc.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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sr_flop.sch
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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sr_flop.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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stimuli.greycnt
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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switch_rreal.sch
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look for inutile stimuli files in schematic directory instead of in simulation directory
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2022-09-13 18:53:17 +02:00 |
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switch_rreal.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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tesla.sch
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xyce quircks/integration for ac analysis, refuse to stretch unscalable images, more example schematics
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2022-02-03 00:40:59 +01:00 |
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tesla.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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test.sch
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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test2.sch
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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test_ac.sch
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fix a bug when loading multiple AC sim datasets (wrong nvars calculation, has to be doubled due to Im/Re complex components)
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2022-12-20 01:01:58 +01:00 |
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test_ac.sym
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ac analysis in graphs (mag + phase, log axis)
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2022-02-02 18:33:16 +01:00 |
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test_ac_xyce.sch
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xyce quircks/integration for ac analysis, refuse to stretch unscalable images, more example schematics
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2022-02-03 00:40:59 +01:00 |
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test_ac_xyce.sym
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xyce quircks/integration for ac analysis, refuse to stretch unscalable images, more example schematics
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2022-02-03 00:40:59 +01:00 |
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test_backannotated_subckt.sch
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improve test_backannotated_subckt.sch example, remove dbg messages
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2022-08-23 10:44:00 +02:00 |
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test_backannotated_subckt.sym
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get_tok_value: even if called with "with_quotes=2" do not skip unescaped backslashes that are outside "quotes". Added dynamic netlisting test circuit in examples
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2020-10-23 23:17:55 +02:00 |
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test_doublepin.sch
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make examples/test_doublepin.sch compile with no errors with ngspice, ghdl and iverilog, this is a test schematic to validate pass-through symbols
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2022-10-11 14:25:58 +02:00 |
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test_doublepin.sym
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add another missing symbol file in examples
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2022-02-17 02:35:41 +01:00 |
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test_extracted_netlist.sch
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updated test schematics to use new xschem annotate_op instead of ngspice::annotate
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2022-09-21 18:38:53 +02:00 |
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test_extracted_netlist.sym
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add test_extracted_netlist circuit example
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2022-02-18 15:11:44 +01:00 |
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test_lm324.sch
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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test_lm324.sym
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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test_ne555.sch
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doc updates (tutorial_use_existing_subckt.html)
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2022-10-22 22:52:55 +02:00 |
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test_ne555.sym
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images (rotated,flipped as the symbol) in symbols
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2022-01-24 22:58:30 +01:00 |
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xcross.sch
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better check_unique_names() and hash_all_names() implementation (do not skip label instances or instances with no format attr). Button click focuses main drawing window even if autofocus_mainwindow is set to 0, to avoid losing keyboard focus forever if TAB is pressed.
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2022-10-12 11:56:02 +02:00 |
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xcross.sym
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persists highlights on instances: remove highlighted instance from hash if user selects and presses ctrl-k as it is done for nets. Avoid instance highlight to also highlight net with identical name (example instance x1 and net x1). Verilog and Vhdl netlists handle duplicated (pass-through) pins
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2022-10-11 13:12:17 +02:00 |
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xnor.sch
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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xnor.sym
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added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements)
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2021-01-02 20:33:34 +01:00 |
9fa05afad9