doc updates (tutorial_use_existing_subckt.html)
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Stefan Frederik
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<!DOCTYPE html>
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<html>
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<head>
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<title>XSCHEM TUTORIAL: CREATE A SYMBOL AND USE AN EXISTING NETLIST</title>
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<link rel="stylesheet" type="text/css" href="xschem_man.css" />
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<style type="text/css">
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/* Local styling goes here */
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p{padding: 15px 30px 10px;}
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</style>
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</head>
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<body>
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<!-- start of slide -->
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<div class="content">
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<!-- navigation buttons -->
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<a href="xschem_man.html" class="home">UP</a>
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<!-- slide title -->
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<h1> TUTORIAL: CREATE A SYMBOL AND USE AN EXISTING NETLIST</h1>
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<p>
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In some cases you have an existing netlist for a circuit block, perhaps from a previous design or
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from a layout parasitic netlist extraction.
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In order to use this netlist in your design you might consider creating a symbol for it in xschem.
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This symbol should match the I/O interface and name of the block netlist and does not need to have
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a corresponding schematic since we want to use the existing netlist.
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One such example in the standard xschem distribution is the test_ne555.sch circuit.
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The test schematic contains a symbol for the popular NE555 timer. The symbol does not provide any
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implementation, the implementation is included in the top design as a .subckt netlist.
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</p>
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<img src="tutorial_use_existing_subckt00.png">
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<p>
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The symbol is implemented in the following way:
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the symbol attributes are:
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</p>
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<img src="tutorial_use_existing_subckt01.png">
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<pre class="code">
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type=primitive
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format="@name @pinlist @symname"
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template="name=x1"
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</pre>
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<p>
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the <kbd>primitive</kbd> value for the <kbd>type</kbd> attribute (instead of the more used
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<kbd>subcircuit</kbd> for symbols with a corresponding implementation schematic) tells xschem
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to generate only the instance calls (the X lines for spice netlists) and not descend into the
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symbol and not generate a .subckt for it.
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</p>
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<p>
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The <kbd>@pinlist</kbd> is expanded into the netlist to the list of I/O ports. The order of the ports in
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this case is the order these pins are created in the symbol. If you click a pin (the small red square box)
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a "<kbd> n = <number></kbd>" appears in the status line. This is the index of the pin. The first
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created pin starts from 0.<br>
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</p>
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<img src="tutorial_use_existing_subckt02.png">
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<ol>
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<li>
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<h3> Changing the pin ordering by altering the object sequence number</h3>
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<p>
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You can change the order the pins are stored into the .sym file.
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Start by clicking the pin that you want to have first in the
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netlist, then press <kbd>Shift-s</kbd>, set the number to 0.
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</p>
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<img src="tutorial_use_existing_subckt03.png">
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<p>
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This will put the selected pin in first position.
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Then move to the pin you want in second position, repeat above steps and assing to it index number 1,
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and so on for all the symbol pins. At the end save your symbol and this will be the pin
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ordering in netlists.
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When netlist is produced this order will be used.
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If left pins in above example have sequence numbers of (starting from the top) 0, 1, 2, 3 and
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right pins have sequence numbers (starting from the bottom) 4, 5, 6, 7 the instance line in
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the netlist will be (check the net names with the schematc in the first image above):
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</p>
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<pre class="code">
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x1 VSS TRIG OUT VSUPPLY CTRL TRIG DIS VSUPPLY ne555
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</pre>
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<p>
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Then move on the pin you want in second position and set its index number to 1 and so on.
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</p>
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</li>
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<li>
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<h3> Changing the pin ordering by using the <kbd>sim_pinnumber</kbd> attribute</h3>
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<p>
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If all symbol pins have a <kbd>sim_pinnumber</kbd> attribute
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this symbol will be netlisted (in all
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netlist formats) with pins sorted in ascending order according to <kbd>sim_pinnumber</kbd> value.
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Start value of sim_pinnumber does not matter (may start at 1 or 0) , it is used as the sort key.
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You can assign the sim_pinnumber attribute directly in the symbol...
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</p>
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<img src="tutorial_use_existing_subckt04.png">
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<p>
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... Or you can assign these in the schematic pins, if you use the
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<kbd>Make symbol from schematic</kbd> function ('a' key) these attributes
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will be transferred to the symbol.
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The <kbd>sim_pinnumber</kbd> attributes that determine the netlist port ordering are
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those defined in the symbol.
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</p>
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<img src="tutorial_use_existing_subckt05.png">
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<p>
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For sorting to happen all symbol pins must have a sim_pinnumber attribute.
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If some pins miss this attribute no sorting is done and pin ordering will be unchanged,
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the stored order of symbol pins will be used (first created pin netlisted first).
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If there are duplicate sim_pinnumber attributes (but all pins have this attribute)
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sorting will happen but relative ordering or pins with identical sim_pinnumber is undefined.<br>
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As an example you may give <kbd>sim_pinnumber=9999</kbd> on a symbol output and
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<kbd>sim_pinnumber=1</kbd> on
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all other pins if you only require the output pin to be netlisted at the end
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and don't care about the other pin ordering.
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</p>
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</li>
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<li>
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<h3> Explicitly specify port ordering in <kbd>format</kbd>
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(or <kbd>verilog_format</kbd> or <kbd>vhdl_format</kbd>) string</h3>
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<p>
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Instead of the following format string that defines the netlist instance line syntax:
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</p>
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<pre class="code">
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format="@name @pinlist @symname"
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</pre>
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<p>
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You can use the following:
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</p>
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<pre class="code">
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format="@name @@GND @@TRIG @@OUT @@RESETB @@CTRL @@THRES @@DIS @@VCC @symname"
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</pre>
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</p>
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In this case you specify the port order one by one explicitly. This can be used for spice
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primitive devices, spice subcircuits (like this example), VHDL and Verilog primitives.
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This method can NOT be used for VHDL and verilog subcircuits since for these you
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do not provide a <kbd>vhdl_format</kbd> or <kbd>verilog_format</kbd> string.
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For these use one of the first two methods.
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In general for VHDL and Verilog port order is not important since port-net association
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is <b>named</b> and not <b>positional</b>.
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</p>
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</li>
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</ol>
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<h2>Specifying subcircuit netlist</h2>
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<ol>
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<li><h3>Add a <kbd>.include <file></kbd> line in the top level</h3>
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<p>
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The first method is to declare the symbol as <kbd>type=primitive</kbd> (this is the case in all
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images above) and simply add a <kbd>.include /path/to/subcircuit.spice</kbd> in the top level netlist:
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</p>
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<img src="tutorial_use_existing_subckt06.png">
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</li>
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<li><h3>Use a <kbd>spice_sym_def=".include <file>"</kbd> line in the symbol</h3>
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<p>
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The second method is to declare the symbol <kbd>type</kbd> as <kbd>subcircuit</kbd> and
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add a <kbd>spice_sym_def</kbd> attribute
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in the symbol. the value of this attribute will be copied verbatim to the netlist, so
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for the example shown here this should do the job:<br>
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<kbd>spice_sym_def=".include model_test_ne555.txt"</kbd><br>
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</p>
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<img src="tutorial_use_existing_subckt07.png">
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<p>
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The produced netlist will be:
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</p>
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<pre class="code">
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** sch_path: /home/schippes/xschem-repo/trunk/xschem_library/examples/test_ne555.sch
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**.subckt test_ne555
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x1 VSS TRIG OUT VSUPPLY CTRL TRIG DIS VSUPPLY ne555
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...
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...
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* expanding symbol: ne555.sym # of pins=8
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** sym_path: /home/schippes/xschem-repo/trunk/xschem_library/examples/ne555.sym
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.include model_test_ne555.txt
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.end
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</pre>
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<p>
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The advantage of this method is that the reference of the subcircuit is embedded in the symbol
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and if the symbol is reused in another design the .include line travels with the symbol and you
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don't have to add the line in the top level.
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</p>
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<!-- end of slide -->
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<div class="filler"></div>
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</div>
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<!-- frame footer -->
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<iframe seamless src="xschem_footer.html" class="footer_iframe" >
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</body>
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</html>
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@ -1,6 +1,10 @@
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v {xschem version=2.9.5_RC5 file_version=1.1}
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G {type=primitive
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format="@name @pinlist @symname"
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v {xschem version=3.1.0 file_version=1.2
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}
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G {}
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K {type=subcircuit
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xformat="@name @pinlist @symname"
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format="@name @@GND @@TRIG @@OUT @@RESETB @@CTRL @@THRES @@DIS @@VCC @symname"
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spice_sym_def=".include model_test_ne555.txt"
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template="name=x1"
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}
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@ -1,9 +1,30 @@
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v {xschem version=3.0.0 file_version=1.2 }
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v {xschem version=3.1.0 file_version=1.2
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}
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G {}
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K {}
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V {}
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S {}
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E {}
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B 2 730 -720 1530 -320 {flags=graph
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y1=-0.052
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y2=5
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ypos1=0
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ypos2=2
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divy=5
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subdivy=1
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unity=1
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x1=0.000177095
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x2=0.00025416
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divx=5
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subdivx=1
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node="out
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trig"
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color="4 15"
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dataset=-1
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unitx=1
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logx=0
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logy=0
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}
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T {NE555 TIMER IC EXAMPLE} 360 -490 0 0 0.4 0.4 {}
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N 130 -150 200 -150 {lab=TRIG}
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C {code.sym} 710 -190 0 0 {
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@ -16,10 +37,14 @@ vvss vss 0 dc 0
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** models are generally not free: you must download
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** SPICE models for active devices and put them into the below
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** referenced file in netlist/simulation directory.
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.include \\"model_test_ne555.txt\\"
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.save all
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.temp 30
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.tran 0.1u 1m uic
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* .include \\"model_test_ne555.txt\\"
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.control
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save all
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tran 0.1u 1m uic
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write test_ne555.raw
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.endc
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"}
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C {ne555.sym} 490 -220 0 0 {name=x1}
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C {res.sym} 130 -180 0 0 {name=r3 m=1 value=2k}
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@ -41,3 +66,7 @@ C {lab_pin.sym} 570 -260 0 1 {name=p17 lab=DIS}
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C {res.sym} 130 -240 0 0 {name=r5 m=1 value=2k}
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C {lab_pin.sym} 130 -210 0 0 {name=p18 lab=DIS}
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C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
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C {launcher.sym} 790 -290 0 0 {name=h5
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descr="load waves"
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tclcommand="xschem raw_read $netlist_dir/test_ne555.raw tran"
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}
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