Commit Graph

1250 Commits

Author SHA1 Message Date
Stefan Frederik 98d59cd8e9 better handle xyce nodes in ngspice:: functions 2022-11-02 11:17:22 +01:00
Stefan Frederik 4bb321af68 add @path attribute for spice/verilog/vhdl/tedax backends 2022-11-02 00:47:59 +01:00
Stefan Frederik fe0dc46c81 remove debug msgs 2022-11-01 12:57:29 +01:00
Stefan Frederik b0a88325e7 "@path" will be expanded in symbols with the hierarchy path, so a fully qualified instance name is obtained with @path@name 2022-11-01 12:54:43 +01:00
Stefan Frederik dc6e9e2d9c (JL) update abs_sym_path such that using network drive (ie. //192.168.1.102/test) will return as is, (JL) add example for network drive to add to XSCHEM_LIBRARY_PATH 2022-10-31 23:48:34 +01:00
Stefan Frederik 153929806b fill attribute on rectangles to override layer fill style: fill=false will not fill 2022-10-29 23:49:00 +02:00
Stefan Frederik 04c05a5703 proc set_paths will set initial dirs (set_initial_dirs) so no need to press Home button after reconfiguring XSCHEM_LIBRARY_PATH and running set_paths 2022-10-29 21:17:13 +02:00
Stefan Frederik ed0924e6ca drill_hilight(): propagate only selected bits of bus nets 2022-10-29 11:06:46 +02:00
Stefan Frederik 9c5fc0b266 add option add_all_windows_drives 2022-10-28 08:54:52 +02:00
Stefan Frederik 5fb452f37f Further hardening of source_user_tcl_files against files containing strange characters including ". 2022-10-27 19:32:46 +02:00
Stefan Frederik 6e43afaa46 drill_hilight() refactoring 2022-10-27 12:43:18 +02:00
Stefan Schippers aa213cc103 formatting changes in drill_hilight() 2022-10-26 19:00:05 +02:00
Stefan Frederik 066a65bfef removed some static hashtable declarations in netlisting code 2022-10-25 23:37:28 +02:00
Stefan Frederik 2c9151ea92 set up a tcl event handler if xschem is run without other event loops (no tk event loop, -x option, no tclreadline event loop, -r option) so xschem will respond to tcp connections 2022-10-25 01:00:51 +02:00
Stefan Frederik a236918f5c do not trigger modify status if enter_text dialog box closed with no changes 2022-10-24 16:07:13 +02:00
Stefan Frederik d1aa8a9e42 global properties dialog box: close if clicking outside or pressing Shift-Return 2022-10-24 14:11:34 +02:00
Stefan Frederik a8689becd6 shift-enter/clicking outside ends text insert widget. Entry widget for text properties string replaced with multiline text widget 2022-10-24 13:05:32 +02:00
Stefan Frederik d20ef12b15 put cairo variable declaration inside #if HAS_CAIRO to avoid compiler warnings. 2022-10-23 00:26:43 +02:00
Stefan Frederik cb652adb5f skip NULL or empty texts in draw_symbol, translate2() skip @@... and @#... tokens (return empty) 2022-10-21 17:48:54 +02:00
Stefan Frederik 4e05fe1bab comment some unneeded dbg messages, update install html page 2022-10-21 12:54:02 +02:00
Stefan Frederik a6dc3d47c3 cache embed attribute of instances for faster lookup 2022-10-21 11:04:20 +02:00
Stefan Frederik e34211368f translate2() fix recursive param substitution 2022-10-20 23:31:02 +02:00
Stefan Frederik bc33261f90 better parsing xxx='<expr>' or xxx={expr} patterns in flatten.awk. Doc upcates, test circuit updates. 2022-10-20 20:25:49 +02:00
Stefan Frederik 506cf627cd use rel_sym_path + find_file to place components (pins, labels) in the schematic 2022-10-20 14:23:18 +02:00
Stefan Frederik 0f25befe31 recursive attribute substitution. use also template attribute of parents if not found in instance prop_ptr 2022-10-20 10:30:48 +02:00
Stefan Frederik 59fb225a36 fix potential string overflow. Thanks JL 2022-10-18 08:38:09 +02:00
Stefan Frederik e8e9afb488 match_file. better file list concatenating 2022-10-18 00:48:29 +02:00
Stefan Frederik edd1e3a370 improved find_file proc, added match_file 2022-10-18 00:02:10 +02:00
Stefan Frederik 33d9afd3a1 avoid hardcoded (relative) paths for label/pins searching, use more general find_file method 2022-10-17 17:20:40 +02:00
Stefan Frederik dad83010f0 perf. improvements in plot_raw_custom_data() / ravg_store() 2022-10-17 15:17:47 +02:00
Stefan Frederik b0359d880a use sim_pinnumber for port ordering in simulation netlists and leave pinnumber for package pin position. These two collide, for example in spice port ordering vs (transistor problem) device package pinnumbers. Dont load graphs in lcc symbols 2022-10-17 12:05:54 +02:00
Stefan Frederik cecd205ff7 Faster implementation of previous change 2022-10-17 00:30:20 +02:00
Stefan Frederik 63a27e410e Engineering notation in wave measurement tooltip 2022-10-17 00:26:28 +02:00
Stefan Frederik f6207070d0 translate() --> @spice_get_current(): find last hier.separator occurrentce with strrchr() 2022-10-16 23:57:07 +02:00
Stefan Frederik 78ca99e4bf save symbol with ordered pins if pinnumber is present in all pins 2022-10-16 22:26:35 +02:00
Stefan Frederik 407bac461d sort symbol pins: remove useless debug messages 2022-10-16 16:23:00 +02:00
Stefan Frederik fc576f69ac sort symbol pins if key pinnumber is present on all of them 2022-10-16 16:18:38 +02:00
Stefan Frederik e8b2385f24 update xschemtest hashes, uniquify allocation IDs 2022-10-16 14:21:22 +02:00
Stefan Frederik 91ba5fd1d3 annotation of voltage and currents in (nested) LCC instances 2022-10-16 13:08:52 +02:00
Stefan Frederik 0e6c35f598 translate2(): return @spice_get_voltage* strings unchanged; get rid of "@#..." tokens in translate2 (return empty) 2022-10-15 22:50:18 +02:00
Stefan Frederik 93fe5bf414 fix handling empty return value of translate2() in load_sym_def() 2022-10-15 11:16:36 +02:00
Stefan Frederik 3adb192936 @spice_get_voltage(net) error checking 2022-10-15 10:52:07 +02:00
Stefan Frederik 56b63df2fc added @spice_get_voltage(net) recognize in translate() for voltage value update inside LCC schematics 2022-10-15 10:08:58 +02:00
Stefan Frederik adf477fbcc optimization in translate(): @spice_get_voltage will use the "lab" attribute (if existing) to build up the net name to look up in raw file, before reverting to a call to net_name() to get the net from the attached net 2022-10-15 08:55:32 +02:00
Stefan Frederik 1482279224 better tcl evaluate command dialog 2022-10-14 18:43:10 +02:00
Stefan Frederik 41c62134a2 change_layer() now works also for text objects 2022-10-14 00:08:46 +02:00
Stefan Frederik 3c4d9e99fb allow changing start color in rainbow multi-dataset graphs 2022-10-13 19:33:30 +02:00
Stefan Frederik 4833f126f7 fix axis start label positioning (axis_start() and axis_within_range()) 2022-10-13 17:36:42 +02:00
Stefan Frederik 7c60f37f54 better atof_spice() suffix checking, set xctx->current_dirname to $PWD when creating an empty new tab (untitled schematic) 2022-10-13 16:45:27 +02:00
Stefan Frederik f7738329a5 my_fgets() 2022-10-13 13:43:01 +02:00
Stefan Frederik 86e8ee2aae added rainbow checkbutton for multicolor waves in case of multiple datasets 2022-10-13 01:00:55 +02:00
Stefan Frederik 7a7b49f383 removed debug message in verilog_netlist.c 2022-10-12 18:21:28 +02:00
Stefan Frederik c065996057 fix some unfreed pointers -b vhdl_netlist.c 2022-10-12 17:04:29 +02:00
Stefan Frederik 3729a4b3d1 inst_hilight_hash_lookup(): fix wrong format string in debug message 2022-10-12 16:50:09 +02:00
Stefan Frederik e14c8b9a11 wire labels: default name set to p1 instead of l1, so it will not clash with typical inductor names 2022-10-12 16:36:56 +02:00
Stefan Frederik a820cc2e3f removed (now) duplicated inst_hash_lookup: use int_hash_lookup. Search function does not highlight nets if searching for something that is not "lab" 2022-10-12 13:14:48 +02:00
Stefan Frederik 7a1fbb4809 better check_unique_names() and hash_all_names() implementation (do not skip label instances or instances with no format attr). Button click focuses main drawing window even if autofocus_mainwindow is set to 0, to avoid losing keyboard focus forever if TAB is pressed. 2022-10-12 11:56:02 +02:00
Stefan Frederik 7d016eab28 small netlist syntax fix in token.c (correctly skip VHDL time attributes), tedax backend: avoid printing mapping comments for duplicated pins 2022-10-12 09:32:37 +02:00
Stefan Frederik 4664202d9d hilight.c: remove a couple of redundant lines 2022-10-12 01:26:33 +02:00
Stefan Frederik 662c14143d update xschemtest, more robust spice flatten.awk netlist flattener, specifically when translating expressions containing electrical nodes and parameters, all these need to be translated/substituted. 2022-10-12 01:16:23 +02:00
Stefan Frederik 3f627123b2 persists highlights on instances: remove highlighted instance from hash if user selects and presses ctrl-k as it is done for nets. Avoid instance highlight to also highlight net with identical name (example instance x1 and net x1). Verilog and Vhdl netlists handle duplicated (pass-through) pins 2022-10-11 13:12:17 +02:00
Stefan Frederik 137ca971d3 add cmdline option --preinit <commands> to execute given commands before executing xschemrc file. This can be used to switch library search paths depending on a variable setting. 2022-10-11 00:26:06 +02:00
Stefan Frederik b93c9af97c flatten.awk: allow to specify additional custom devices node number with metacomments inserted in the netlist, like *.nodes[W] = 2, or *. nodes["W"]=2 2022-10-10 17:45:56 +02:00
Stefan Frederik 118e937e7f flatten.awk: derive element pattern list ^[EGHFCMDQRGIV] from nodes[] array, to facilitate addition of new devices. 2022-10-10 15:36:50 +02:00
Stefan Frederik 68bf5e4640 netlister code rewrite to allow any combination of pass-through symbols 2022-10-10 14:54:32 +02:00
Stefan Frederik 150c2663b9 added netlist_options as list of symbols not to load in schematics-as-symbol instances, load_file_dialog: make remember last dir work again 2022-10-09 23:49:28 +02:00
Stefan Frederik c5e7e3be29 cleaner get_unnamed_node() function 2022-10-08 22:16:27 +02:00
Stefan Frederik 03d2e685fe code cleanup 2022-10-08 10:07:59 +02:00
Stefan Frederik 4e6513e713 typo fix 2022-10-08 09:52:54 +02:00
Stefan Frederik 5c2b14ebb8 add generic pointer hash table 2022-10-08 09:46:30 +02:00
Stefan Frederik 6be0fc392b refactoring of netlister code 2022-10-07 23:29:42 +02:00
Stefan Frederik 945a26c8f6 handle pass-through symbols chained with wires and no labels attached to wires 2022-10-06 11:48:22 +02:00
Stefan Frederik c5e91f209e allow to use @pinlist in format string even for symbols with duplicated ports. Duplicated entries will be skipped. Add component_browser_on_top tcl variable in xschemrc (default setting: enabled (1) to enable or disable component browser window always on top 2022-10-05 16:47:34 +02:00
Stefan Frederik 0c590e4f0a allow negative integers in expandlabel() ( xx[6:5:-2:3] ) 2022-10-05 15:34:38 +02:00
Stefan Frederik 47fb2085ff update send_net_to graph() and send_current_to_graph() to use sch_waves_loaded() as the hierarchy level where raw file was loaded, to skip upper path designators 2022-10-05 12:06:37 +02:00
Stefan Frederik 9dbe4343e2 added label notation EN[0:3:6:5]: EN[start🔚offset:repetitions], it will expand to a 20 bit bus: a[0],a[1],a[2],a[3],a[6],a[7],a[8],a[9],a[12],a[13],a[14],a[15],a[18],a[19],a[20],a[21],a[24],a[25],a[26],a[27] 2022-10-05 02:23:37 +02:00
Stefan Frederik 5fe2f1586b refactor str_hash_* and int_hash_* functions 2022-10-05 01:18:45 +02:00
Stefan Frederik 1c407e5dd6 faster implementation of name_pass_through_nets() so almost zero overhead when netlisting big circuits with no pass-thru symbols 2022-10-04 15:39:45 +02:00
Stefan Frederik 9c29324c8a allow nets with no label pass thru symbols with duplicated pins. named nets will propagate through duplicated pins 2022-10-04 12:34:09 +02:00
Stefan Frederik 06fc742e60 doc updates about {verilog,vhdl,spice}_sym_def, fix regression (possible crash) in verilog_block_netlist (thanks to Joanne), fix regression (wrong verilog test netlist) in print_verilog_primitive() (thanks to Joanne) 2022-10-04 00:37:09 +02:00
Stefan Frederik 29d6655a01 use limiting mylog()/mylog10() functions in expression calculator 2022-10-03 18:29:36 +02:00
Stefan Frederik 4bbed85d23 faster jump table in plot_raw_custom_data(), added simulation->add waveform reload launcher 2022-10-03 11:15:14 +02:00
Stefan Frederik 64d947a9dd fix extra and verilog_extra handling in instance lines (verilog netlists) 2022-10-03 09:10:58 +02:00
Stefan Frederik d174306880 added verilog_extra attribute for list of implicit node connections to symbol in verilog netlists. extra attribute still used in verilog as a list of attributes NOT use as component attributes / symbol parameters. 2022-10-03 01:20:33 +02:00
Stefan Frederik 28c644fba7 doc updates (new graph functions) 2022-10-02 20:52:17 +02:00
Stefan Frederik 9acbf3fb41 added prev(), del() function in graph processing. Extend calculation 1 or 2 point beyond viewport for exact deriv/integ/prev/del calculation at left edge 2022-10-02 11:05:29 +02:00
Stefan Frederik 5a39f7be40 cleanups in plot_raw_custom_data() 2022-10-01 10:38:27 +02:00
Stefan Frederik db94f9fb25 @pinlist will be comma separated in verilog netlists 2022-10-01 09:46:58 +02:00
Stefan Frederik d06310deae cleanups and faster branch tables in scheduler.c 2022-09-30 18:12:17 +02:00
Stefan Frederik 08aff09cf9 scheduler.c cleanup 2022-09-30 13:08:53 +02:00
Stefan Frederik fc16997d0c switch dispatcher instead of if-else in scheduler.c 2022-09-30 00:19:27 +02:00
Stefan Frederik f26d082389 cleanups(2) in scheduler.c 2022-09-29 22:52:15 +02:00
Stefan Frederik b20ca9b501 cleanups in scheduler.c 2022-09-29 22:35:44 +02:00
Stefan Frederik f45278ebe3 cleanups in scheduler.c 2022-09-29 19:16:03 +02:00
Stefan Frederik 6296bbc1c6 compile option for 2nd order 3-point backward derivative calculation formulaes for graph expressions 2022-09-29 18:22:55 +02:00
Stefan Frederik 6b4ce14e7d some refactoring of tcl globals, engineering format in cursor display (on unscaled axes) 2022-09-29 14:22:33 +02:00
Stefan Frederik b7c7c336dd added vhdl_sym_def, spice_sym_def, verilog_sym_def attributes for symbols. If defined and not empty the corresponding netlister will insert the content of the attribute instead of the subcircuit schematic implementation. Typically used to include a definition file. Updated documentation 2022-09-29 11:59:43 +02:00
Stefan Frederik ae4b74f2d8 graph axes in engineering notation (20u, 10p, 3k), fix an issue in graph panning with button1 mouse; ngspice:: get_current, get_voltage, get_diff_voltage, get_node embedded into xschem.tcl, to_eng tcl procedure to convert number to engineering form. 2022-09-28 19:14:31 +02:00
Stefan Frederik 9d9a4826fc (Joanne) update to be clearer on how to compile xschem (from scratch vs using XSchemWin.sln) on Windows using VS2022. font.sch micro edits 2022-09-28 11:33:48 +02:00
Stefan Frederik 6d17797d0b add Highlight->Select overlapped instances command 2022-09-27 18:35:42 +02:00