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added verilog_extra attribute for list of implicit node connections to symbol in verilog netlists. extra attribute still used in verilog as a list of attributes NOT use as component attributes / symbol parameters.

This commit is contained in:
Stefan Frederik 2022-10-03 01:20:33 +02:00
parent 28c644fba7
commit d174306880
7 changed files with 44 additions and 20 deletions
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28
doc/xschem_man/symbol_property_syntax.html
View File

@ -204,7 +204,7 @@ type=nmos
This is necessary for some spice commands that need to be placed before the rest of the netlist.
</p>
<li><kbd>generic_type</kbd></li>
<p><kbd>generic_type</kbd> defines the type of parameters passed to VHDL components. Consider the following
<p><kbd>generic_type</kbd> defines the type of parameters passed to VHDL/Verilog components. Consider the following
MOS symbol definition; the <kbd>model</kbd> attribute is declared as <kbd>string</kbd> and it will be
quoted in VHDL netlists.
</p>
@ -264,8 +264,7 @@ verilog_stop=true
x2 G_y G_a G_b G_c VCC VSS lvnand3 wn=1.8u ln=0.18u wp=1u lp=0.18u m=1
**.ends
* expanding symbol: customlogicLib/lvnand3 # of pins=4
.subckt lvnand3 y a b c VCCPIN VSSPIN
wn=30u ln=2.4u wp=20u lp=2.4u
.subckt lvnand3 y a b c VCCPIN VSSPIN wn=30u ln=2.4u wp=20u lp=2.4u
*.opin y
*.ipin a
*.ipin b
@ -295,9 +294,7 @@ x2 G_y G_a G_b G_c VCC VSS lvnand3 wn=1.8u ln=0.18u wp=1u lp=0.18u m=1
* expanding symbol: customlogicLib/lvnand3 # of pins=4
.subckt lvnand3 y a b c
wn=30u ln=2.4u wp=20u lp=2.4u
VCCPIN=VCC VSSPIN=VSS
.subckt lvnand3 y a b c wn=30u ln=2.4u wp=20u lp=2.4u VCCPIN=VCC VSSPIN=VSS
*.opin y
*.ipin a
*.ipin b
@ -316,7 +313,24 @@ m5 net1 b net2 VSSPIN nlv w=wn l=ln geomod=0 m=1
.ends
</pre>
<p>
as you can see the VSSPIN and VCCPIN are listed as parameters and not as pins in the netlist.
as you can see the VSSPIN and VCCPIN are listed as parameters in addition as pins in the netlist.
</p>
<li><kbd>verilog_extra</kbd></li>
<p>
This attribute is similar to the <kbd>extra</kbd> attribute and is used for verilog netlist. Nodes
listed in this atrribute value will be used as additional pin connections.
</p>
<p class="important">
the <kbd>extra</kbd> attribute is still used in verilog netlist as a list of attributes NOT to pass as
symbol parameters
</p>
<p>
You may assign the following attributes to an instance: <kbd>name=X1 VPWR=VCC VGND=GND subckt=NOR2_1</kbd>
and you want to have VCC and GND connections to the symbol in the Verilog netlist but do not want
any of these attributes to be
passed as symbol parameters. In this case you set: <kbd>verilog_extra="VPWR VGND"</kbd> and
<kbd>extra="VPWR VGND subckt"</kbd> since <kbd>subckt</kbd> is probably a spice attribute and you don't
want it in verilog.
</p>
<li><kbd>dir</kbd></li>
<p>

7
src/save.c
View File

@ -395,6 +395,13 @@ static int read_dataset(FILE *fd, const char *type)
else if(!strncmp(line, "No. Variables:", 14)) {
n = sscanf(line, "No. Variables: %d", &nvars);
dbg(dbglev, "read_dataset(): nvars=%d\n", nvars);
if(xctx->graph_datasets > 0 && xctx->graph_nvars != nvars) {
dbg(0, "Xschem requires all datasets to be saved with identical and same number of variables\n");
dbg(0, "There is a mismatch, so this and following datasets will not be read\n");
return 1;
}
if(ac) nvars <<= 1;
if(n < 1) {
dbg(0, "read_dataset(): WAARNING: malformed raw file, aborting\n");

6
src/spice_netlist.c
View File

@ -507,11 +507,11 @@ void spice_block_netlist(FILE *fd, int i)
fprintf(fd, "%s\n", sym_def);
} else {
fprintf(fd, "** sch_path: %s\n", filename);
fprintf(fd, ".subckt %s",skip_dir(xctx->sym[i].name));
print_spice_subckt(fd, i);
fprintf(fd, ".subckt %s ",skip_dir(xctx->sym[i].name));
print_spice_subckt_nodes(fd, i);
my_strdup(387, &extra, get_tok_value(xctx->sym[i].prop_ptr,"extra",0) );
/* this is now done in print_spice_subckt */
/* this is now done in print_spice_subckt_nodes */
/*
* fprintf(fd, "%s ", extra ? extra : "" );
*/

13
src/token.c
View File

@ -1561,7 +1561,7 @@ void print_tedax_subckt(FILE *fd, int symbol)
}
void print_spice_subckt(FILE *fd, int symbol)
void print_spice_subckt_nodes(FILE *fd, int symbol)
{
int i=0, multip;
const char *str_ptr=NULL;
@ -1647,7 +1647,7 @@ void print_spice_subckt(FILE *fd, int symbol)
if(!strcmp(get_tok_value(prop, "name",0), token + 2)) break;
}
if(i<no_of_pins && strcmp(get_tok_value(prop,"spice_ignore",0), "true")) {
fprintf(fd, "%s", expandlabel(token+2, &multip));
fprintf(fd, "%s ", expandlabel(token+2, &multip));
}
}
/* reference by pin number instead of pin name, allows faster lookup of the attached net name 20180911 */
@ -1664,9 +1664,12 @@ void print_spice_subckt(FILE *fd, int symbol)
* specified by the format string. The 'extra' attribute is no more used to print extra nodes
* in spice_block_netlist(). */
else if(token[0] == '@') { /* given previous if() conditions not followed by @ or # */
fprintf(fd, "%s ", token + 1);
/* if token not followed by white space it is not an extra node */
if( ( (space || c == '%' || c == '@') && !escape ) ) {
fprintf(fd, "%s ", token + 1);
}
}
if(c!='%' && c!='@' && c!='\0' ) fputc(c,fd);
/* if(c!='%' && c!='@' && c!='\0' ) fputc(c,fd); */
if(c == '@' || c =='%') s--;
state=TOK_BEGIN;
}
@ -2527,7 +2530,7 @@ void print_verilog_element(FILE *fd, int inst)
my_free(1041, &name);
return;
}
my_strdup(1559, &extra, get_tok_value((xctx->inst[inst].ptr + xctx->sym)->prop_ptr, "extra", 0));
my_strdup(1559, &extra, get_tok_value((xctx->inst[inst].ptr + xctx->sym)->prop_ptr, "verilog_extra", 0));
my_strdup(506, &template, (xctx->inst[inst].ptr + xctx->sym)->templ);
no_of_pins= (xctx->inst[inst].ptr + xctx->sym)->rects[PINLAYER];

4
src/verilog_netlist.c
View File

@ -449,8 +449,8 @@ void verilog_block_netlist(FILE *fd, int i)
if(sym_def[0]) {
fprintf(fd, "%s\n", sym_def);
} else {
my_strdup(1040, &extra, get_tok_value((xctx->inst[i].ptr + xctx->sym)->prop_ptr, "extra", 0));
my_strdup(1563, &extra2, get_tok_value((xctx->inst[i].ptr + xctx->sym)->prop_ptr, "extra", 0));
my_strdup(1040, &extra, get_tok_value((xctx->inst[i].ptr + xctx->sym)->prop_ptr, "verilog_extra", 0));
my_strdup(1563, &extra2, get_tok_value((xctx->inst[i].ptr + xctx->sym)->prop_ptr, "verilog_extra", 0));
fprintf(fd, "// sch_path: %s\n", filename);
verilog_stop? load_schematic(0,filename, 0) : load_schematic(1,filename, 0);
/* print verilog timescale and preprocessor directives 10102004 */

2
src/xschem.h
View File

@ -1291,7 +1291,7 @@ extern const char *translate(int inst, const char* s);
extern const char* translate2(Lcc *lcc, int level, char* s);
extern void print_tedax_element(FILE *fd, int inst);
extern int print_spice_element(FILE *fd, int inst);
extern void print_spice_subckt(FILE *fd, int symbol);
extern void print_spice_subckt_nodes(FILE *fd, int symbol);
extern void print_tedax_subckt(FILE *fd, int symbol);
extern void print_vhdl_element(FILE *fd, int inst);
extern void print_verilog_element(FILE *fd, int inst);

4
tests/xschemtest.tcl
View File

@ -190,13 +190,13 @@ proc test_xschem_simulation {{f simulate_ff.sch}} {
proc netlist_test {} {
global netlist_dir
foreach {f t h} {
rom8k.sch spice 2922365852
rom8k.sch spice 1975420796
greycnt.sch verilog 3822198138
autozero_comp.sch spice 2275498269
loading.sch vhdl 584526899
mos_power_ampli.sch spice 1004049459
hierarchical_tedax.sch tedax 998070173
LCC_instances.sch spice 1046024056
LCC_instances.sch spice 103017336
pcb_test1.sch tedax 1925087189
simulate_ff.sch spice 1321596936
} {