luke
/
xschem
mirror of https://github.com/StefanSchippers/xschem.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

doc updates about {verilog,vhdl,spice}_sym_def, fix regression (possible crash) in verilog_block_netlist (thanks to Joanne), fix regression (wrong verilog test netlist) in print_verilog_primitive() (thanks to Joanne)

This commit is contained in:
Stefan Frederik 2022-10-04 00:37:09 +02:00
parent 29d6655a01
commit 06fc742e60
3 changed files with 6 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
doc/xschem_man/symbol_property_syntax.html
View File

@ -169,7 +169,8 @@ type=nmos
<li><kbd>spice_sym_def</kbd></li>
<li><kbd>verilog_sym_def</kbd></li>
<li><kbd>vhdl_sym_def</kbd></li>
<p> If any of these attributes are present and not empty the corresponding netlister will ignore the schematic subcircuit
<p> If any of these attributes are present and not empty and the symbol type is set to <kbd>subcircuit</kbd>
the corresponding netlister will ignore the schematic subcircuit
and dump into the netlist the content of this attribute. The typical usage is to include a file, example:<br>
<pre class="code">
verilog_sym_def="tcleval(`include \"[abs_sym_path verilog_include_file.v]\")"

4
src/token.c
View File

@ -2435,7 +2435,7 @@ static void print_verilog_primitive(FILE *fd, int inst) /* netlist switch level
for(i=0;i<no_of_pins;i++)
{
str_ptr = net_name(inst,i, &multip, 0, 1);
fprintf(fd, "----pin(%s)", str_ptr);
fprintf(fd, "----pin(%s) ", str_ptr);
if(i < no_of_pins - 1) fprintf(fd, " , ");
}
}
@ -2444,7 +2444,7 @@ static void print_verilog_primitive(FILE *fd, int inst) /* netlist switch level
char *prop = (xctx->inst[inst].ptr + xctx->sym)->rect[PINLAYER][i].prop_ptr;
if(!strcmp( get_tok_value(prop,"name",0), token+2)) {
str_ptr = net_name(inst,i, &multip, 0, 1);
fprintf(fd, "----pin(%s)", str_ptr);
fprintf(fd, "----pin(%s) ", str_ptr);
break;
}
}

4
src/verilog_netlist.c
View File

@ -449,8 +449,8 @@ void verilog_block_netlist(FILE *fd, int i)
if(sym_def[0]) {
fprintf(fd, "%s\n", sym_def);
} else {
my_strdup(1040, &extra, get_tok_value((xctx->inst[i].ptr + xctx->sym)->prop_ptr, "verilog_extra", 0));
my_strdup(1563, &extra2, get_tok_value((xctx->inst[i].ptr + xctx->sym)->prop_ptr, "verilog_extra", 0));
my_strdup(1040, &extra, get_tok_value(xctx->sym[i].prop_ptr, "verilog_extra", 0));
my_strdup(1563, &extra2, get_tok_value(xctx->sym[i].prop_ptr, "verilog_extra", 0));
fprintf(fd, "// sch_path: %s\n", filename);
verilog_stop? load_schematic(0,filename, 0) : load_schematic(1,filename, 0);
/* print verilog timescale and preprocessor directives 10102004 */