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small netlist syntax fix in token.c (correctly skip VHDL time attributes), tedax backend: avoid printing mapping comments for duplicated pins

This commit is contained in:
Stefan Frederik 2022-10-12 09:32:37 +02:00
parent 4664202d9d
commit 7d016eab28
3 changed files with 58 additions and 17 deletions
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28
src/token.c
View File

@ -2080,22 +2080,27 @@ void print_tedax_element(FILE *fd, int inst)
int net_mult;
int pin_mult;
int n;
Int_hashtable table={NULL, 0};
subcircuit = 1;
fprintf(fd, "__subcircuit__ %s %s\n", skip_dir(xctx->inst[inst].name), xctx->inst[inst].instname);
int_hash_init(&table, 37);
for(i=0;i<no_of_pins; i++) {
my_strdup2(531, &net, net_name(inst,i, &net_mult, 0, 1));
my_strdup2(1196, &pinname,
get_tok_value((xctx->inst[inst].ptr + xctx->sym)->rect[PINLAYER][i].prop_ptr,"name",0));
my_strdup2(1197, &pin, expandlabel(pinname, &pin_mult));
dbg(1, "#net=%s pinname=%s pin=%s net_mult=%d pin_mult=%d\n", net, pinname, pin, net_mult, pin_mult);
for(n = 0; n < net_mult; n++) {
my_strdup(1204, &netbit, find_nth(net, ",", n+1));
my_strdup(1205, &pinbit, find_nth(pin, ",", n+1));
fprintf(fd, "__map__ %s -> %s\n",
pinbit ? pinbit : "__UNCONNECTED_PIN__",
netbit ? netbit : "__UNCONNECTED_PIN__");
if(!int_hash_lookup(&table, pinname, 1, XINSERT_NOREPLACE)) {
dbg(1, "#net=%s pinname=%s pin=%s net_mult=%d pin_mult=%d\n", net, pinname, pin, net_mult, pin_mult);
for(n = 0; n < net_mult; n++) {
my_strdup(1204, &netbit, find_nth(net, ",", n+1));
my_strdup(1205, &pinbit, find_nth(pin, ",", n+1));
fprintf(fd, "__map__ %s -> %s\n",
pinbit ? pinbit : "__UNCONNECTED_PIN__",
netbit ? netbit : "__UNCONNECTED_PIN__");
}
}
}
int_hash_free(&table);
my_free(1199, &net);
my_free(1200, &pin);
my_free(1201, &pinname);
@ -2628,9 +2633,14 @@ void print_verilog_element(FILE *fd, int inst)
if(value[0] != '\0') /* token has a value */
{
if(strcmp(token,"spice_ignore") && strcmp(token,"vhdl_ignore") && strcmp(token,"tedax_ignore")) {
if(tmp == 0) {fprintf(fd, "#(\n---- start parameters\n");tmp++;tmp1=0;}
if(tmp1) fprintf(fd, " ,\n");
if(tmp == 0) {
fprintf(fd, "#(\n---- start parameters\n");
tmp++;
tmp1=0;
}
/* skip attributes of type time (delay="20 ns") that have VHDL syntax */
if( !generic_type || strcmp(get_tok_value(generic_type,token, 0), "time") ) {
if(tmp1) fprintf(fd, " ,\n");
if( generic_type && !strcmp(get_tok_value(generic_type,token, 0), "string") ) {
fprintf(fd, " .%s ( \"%s\" )", token, value);
} else {

34
xschem_library/examples/doublepin.sch
View File

@ -5,18 +5,40 @@ K {}
V {}
S {}
E {}
N 210 -300 250 -300 {
lab=CK}
N 250 -300 250 -220 {
lab=CK}
N 250 -220 340 -220 {
lab=CK}
N 210 -260 210 -240 {
lab=RST}
N 210 -240 340 -240 {
lab=RST}
N 210 -190 280 -190 {
lab=B}
N 280 -260 280 -190 {
lab=B}
N 280 -260 340 -260 {
lab=B}
N 210 -220 230 -220 {
lab=A[3:0]}
N 230 -280 230 -220 {
lab=A[3:0]}
N 230 -280 340 -280 {
lab=A[3:0]}
N 540 -280 580 -280 {
lab=Z,NC1,NC2,NC3}
C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
C {ipin.sym} 210 -220 0 0 {name=p1 lab=A[3:0]}
C {ipin.sym} 210 -190 0 0 {name=p3 lab=B}
C {opin.sym} 520 -240 0 0 {name=p4 lab=Z}
C {opin.sym} 690 -250 0 0 {name=p4 lab=Z}
C {ipin.sym} 210 -260 0 0 {name=p5 lab=RST}
C {ipin.sym} 210 -300 0 0 {name=p7 lab=CK}
C {noconn.sym} 210 -300 2 0 {name=l2}
C {noconn.sym} 210 -260 2 0 {name=l3}
C {noconn.sym} 210 -220 2 0 {name=l4}
C {noconn.sym} 210 -190 2 0 {name=l5}
C {noconn.sym} 520 -240 2 1 {name=l6}
C {noconn.sym} 690 -250 2 1 {name=l6}
C {use.sym} 380 -480 0 0 {------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;}
C {sync_reg.sym} 440 -250 0 0 {name=x1 width=4 del=400 delay="400 ps"}
C {lab_pin.sym} 580 -280 0 1 {name=l1 sig_type=std_logic lab=Z,NC1,NC2,NC3}

13
xschem_library/examples/xcross.sch
View File

@ -5,9 +5,18 @@ K {}
V {}
S {}
E {}
C {iopin.sym} 10 -80 0 0 {name=p1 lab=A}
C {iopin.sym} 10 -20 0 0 {name=p1 lab=B}
N 150 -80 190 -80 {
lab=A}
N 150 -20 190 -20 {
lab=B}
C {iopin.sym} 190 -80 0 0 {name=p1 lab=A}
C {iopin.sym} 190 -20 0 0 {name=p1 lab=B}
C {use.sym} 160 -240 0 0 {------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;}
C {res.sym} 150 -50 0 0 {name=R1
value=1k
footprint=1206
device=resistor
m=1}