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handle pass-through symbols chained with wires and no labels attached to wires

This commit is contained in:
Stefan Frederik 2022-10-06 11:48:22 +02:00
parent c5e91f209e
commit 945a26c8f6
4 changed files with 277 additions and 107 deletions
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3
src/hilight.c
View File

@ -1153,8 +1153,9 @@ void propagate_hilights(int set, int clear, int mode)
char *type;
int en_hi;
dbg(1, "propagate_hilights()\n");
dbg(1, "propagate_hilights() for %s\n", xctx->current_name);
en_hi = tclgetboolvar("en_hilight_conn_inst");
prepare_netlist_structs(0);
for(i = 0; i < xctx->instances; i++) {
if(xctx->inst[i].ptr < 0 ) {

125
src/netlist.c
View File

@ -565,7 +565,7 @@ int get_unnamed_node(int what, int mult,int node)
xctx->node_mult_size += CADCHUNKALLOC;
my_realloc(242, &xctx->node_mult, sizeof(int) * xctx->node_mult_size );
for (i=xctx->node_mult_size-CADCHUNKALLOC;i<xctx->node_mult_size;i++) xctx->node_mult[i]=0;
}
}
xctx->node_mult[xctx->new_node]=mult;
return xctx->new_node;
}
@ -625,9 +625,9 @@ int record_global_node(int what, FILE *fp, char *node)
/* name nets that are attached to symbols with duplicated pins.
* if another duplicated pin is attached to a named net/label/pin get name from there */
static void name_pass_through_nets()
static void name_pass_through_nets(int for_netlist)
{
int i, j, rects, rot, flip, sqx, sqy, changed = 0;
int i, j, k, rects, rot, flip, sqx, sqy, changed = 0;
double x0, y0, rx1, ry1;
char *type = NULL, *type2 = NULL;
xRect *rct;
@ -637,29 +637,43 @@ static void name_pass_through_nets()
int const instances = xctx->instances;
Str_hashtable table = {NULL, 0};
Str_hashentry *entry;
int *symtable = NULL;
const char *pin_name;
int *pt_symbol = NULL; /* pass-through symbols, symbols with duplicated ports */
int there_are_pt = 0;
int lev = 1;
dbg(1, "name_pass_through_nets() start...\n");
pt_symbol = my_calloc(973, xctx->symbols, sizeof(int));
for(i = 0; i < xctx->symbols; i++) {
symtable = my_calloc(1581, xctx->symbols, sizeof(int));
/* we can not loop over xctx->symbols since we keep symbols of parent circuit while netlisting */
for(i = 0; i < xctx->instances; i++) {
k = xctx->inst[i].ptr;
if( k < 0 || symtable[k] ) continue;
symtable[k] =1;
dbg(lev, "name_pass_through_nets(): inst=%s sym=%s\n", xctx->inst[i].instname, xctx->sym[k].name);
str_hash_init(&table, 37);
for(j = 0; j < xctx->sym[i].rects[PINLAYER]; j++) {
const char *pin_name = get_tok_value(xctx->sym[i].rect[PINLAYER][j].prop_ptr, "name", 0);
for(j = 0; j < xctx->sym[k].rects[PINLAYER]; j++) {
const char *pin_name = get_tok_value(xctx->sym[k].rect[PINLAYER][j].prop_ptr, "name", 0);
entry = str_hash_lookup(&table, pin_name, "1", XINSERT_NOREPLACE);
if(entry) {
pt_symbol[i] = 1;
dbg(lev, " pass thru symbol found\n");
pt_symbol[k] = 1;
there_are_pt = 1;
break;
}
}
str_hash_free(&table);
if(pt_symbol[i]) dbg(1, "duplicated pins: %s\n", xctx->sym[i].name);
if(pt_symbol[k]) dbg(1, "duplicated pins: %s\n", xctx->sym[i].name);
}
my_free(1582, &symtable);
if(!there_are_pt) { /* nothing to do: no pass through symbols */
my_free(1573, &pt_symbol);
return;
}
do { /* keep looping until propagation of nets occurs */
dbg(lev, "name_pass_through_nets(): do loop\n");
changed = 0;
for (i=0;i<instances;i++) {
dbg(1, "instance %d: %s\n", i, inst[i].instname);
@ -687,9 +701,33 @@ static void name_pass_through_nets()
if (touch(xctx->wire[wptr->n].x1, xctx->wire[wptr->n].y1,
xctx->wire[wptr->n].x2, xctx->wire[wptr->n].y2, x0,y0)) {
if(xctx->wire[wptr->n].node) {
dbg(1, "pin_name=%s, node=%s\n", pin_name, xctx->wire[wptr->n].node);
entry = str_hash_lookup(&table, pin_name, xctx->wire[wptr->n].node, XINSERT_NOREPLACE);
if(entry) signal_short(xctx->wire[wptr->n].node, entry->value);
dbg(1, "pin_name=%s, node=%s\n", pin_name, xctx->wire[wptr->n].node);
entry = str_hash_lookup(&table, pin_name, NULL, XLOOKUP);
if(entry) {
if(entry->value[0] != '#') {
if(xctx->wire[wptr->n].node[0] != '#') {
/* named net attached and another named net on duplicated pin -> check short */
if(for_netlist) signal_short(xctx->wire[wptr->n].node, entry->value);
}
} else { /* pin begins with '#' */
if(xctx->wire[wptr->n].node[0] != '#') {
/* named net has precedence over auto-named net */
str_hash_lookup(&table, pin_name, xctx->wire[wptr->n].node, XINSERT);
} else { /* pin and wire both begin with '#' */
int n, p;
sscanf(xctx->wire[wptr->n].node, "#net%d", &n);
sscanf(entry->value, "#net%d", &p);
if(n < p) { /* lower numbered #nets have precedence */
dbg(lev, "inst: %s pin %s <--- net %s\n",
inst[i].instname, entry->value, xctx->wire[wptr->n].node);
str_hash_lookup(&table, pin_name, xctx->wire[wptr->n].node, XINSERT);
}
}
}
} else {
/* pin unconnected. Assign from net */
entry = str_hash_lookup(&table, pin_name, xctx->wire[wptr->n].node, XINSERT);
}
}
}
wptr=wptr->next;
@ -709,10 +747,13 @@ static void name_pass_through_nets()
if ((iptr->x0==x0) && (iptr->y0==y0)) {
if(xctx->inst[iptr->n].node[0]) {
dbg(1, "pin_name=%s, node=%s\n", pin_name, xctx->inst[iptr->n].node[0]);
entry = str_hash_lookup(&table, pin_name, xctx->inst[iptr->n].node[0], XINSERT_NOREPLACE);
if(entry) signal_short(xctx->inst[iptr->n].node[0], entry->value);
entry = str_hash_lookup(&table, pin_name, xctx->inst[iptr->n].node[0], XLOOKUP);
if(entry && entry->value[0] != '#') {
if(for_netlist) signal_short(xctx->inst[iptr->n].node[0], entry->value);
} else {
str_hash_lookup(&table, pin_name, xctx->inst[iptr->n].node[0], XINSERT);
}
}
}
iptr=iptr->next;
}
@ -731,20 +772,45 @@ static void name_pass_through_nets()
wptr = xctx->wire_spatial_table[sqx][sqy];
pin_name = get_tok_value(rct[j].prop_ptr, "name", 0);
while(wptr) {
int assign = 0;
if (touch(xctx->wire[wptr->n].x1, xctx->wire[wptr->n].y1,
xctx->wire[wptr->n].x2, xctx->wire[wptr->n].y2, x0,y0)) {
if(!xctx->wire[wptr->n].node) { /* net is unnamed */
dbg(1, "lookup pin_name=%s\n", pin_name);
entry = str_hash_lookup(&table, pin_name, NULL, XLOOKUP);
if(entry) { /* found duplicated pin */
my_strdup(1568, &xctx->wire[wptr->n].node, entry->value);
my_strdup(1569, &xctx->wire[wptr->n].prop_ptr,
subst_token(xctx->wire[wptr->n].prop_ptr, "lab", entry->value));
wirecheck(wptr->n);
changed = 1;
}
entry = str_hash_lookup(&table, pin_name, NULL, XLOOKUP);
if(entry) {
if(xctx->wire[wptr->n].node) {
if(strcmp(xctx->wire[wptr->n].node, entry->value)) { /* net node name is different */
if(xctx->wire[wptr->n].node[0] == '#') { /* autonamed net */
if(entry->value[0] == '#') { /* autonamed pin */
int n, p;
sscanf(xctx->wire[wptr->n].node, "#net%d", &n);
sscanf(entry->value, "#net%d", &p);
dbg(lev, "2nd loop: net=%s pin=%s\n", xctx->wire[wptr->n].node, entry->value);
if(n > p) assign = 1; /* lower numbered #net names on pins have precedence */
} else { /* not autonamed pin */
assign = 1;
}
} else { /* not autonamed net */
if(entry->value[0] != '#') { /* not autonamed pin */
if(for_netlist) signal_short(xctx->wire[wptr->n].node, entry->value);
}
}
}
} else { /* wire .node is NULL */
assign = 1;
}
}
}
if(assign) {
dbg(lev, "inst %s pin %s(%s) --> net %s\n",
inst[i].instname, entry->token, entry->value,
xctx->wire[wptr->n].node ? xctx->wire[wptr->n].node : "<NULL>");
my_strdup(1568, &xctx->wire[wptr->n].node, entry->value);
my_strdup(1569, &xctx->wire[wptr->n].prop_ptr,
subst_token(xctx->wire[wptr->n].prop_ptr, "lab", entry->value));
wirecheck(wptr->n);
changed = 1;
}
} /* if(touch...) */
wptr=wptr->next;
}
} /* for (j=0;j<rects;j++) */
@ -756,6 +822,7 @@ static void name_pass_through_nets()
my_free(1570, &type);
my_free(1571, &type2);
my_free(1572, &pt_symbol);
dbg(lev, "name_pass_through_nets() end...\n");
}
@ -793,7 +860,7 @@ void prepare_netlist_structs(int for_netlist)
/* delete instance pins spatial hash, wires spatial hash, node_hash, wires and inst nodes.*/
delete_netlist_structs();
free_simdata(); /* invalidate simulation cache */
dbg(1, "prepare_netlist_structs(): extraction\n");
dbg(1, "prepare_netlist_structs(): extraction: %s\n", xctx->sch[xctx->currsch]);
if(xctx->netlist_count == 0 ) startlevel = xctx->currsch;
/* print_erc is 1 the first time prepare_netlist_structs() is called on top level while
* doing the netlist, when netlist of sub blocks is completed and toplevel is reloaded
@ -947,7 +1014,6 @@ void prepare_netlist_structs(int for_netlist)
} /* if(type && ... */
} /* for(i=0;i<instances... */
name_pass_through_nets(); /* name nets that are attached to symbols with duplicated pins. */
/* name nets that do not touch ipin opin alias instances */
dbg(2, "prepare_netlist_structs(): naming nets that dont touch labels\n");
@ -971,6 +1037,7 @@ void prepare_netlist_structs(int for_netlist)
}
}
name_pass_through_nets(for_netlist); /* name nets that are attached to symbols with duplicated pins. */
/* NAME GENERICS */
@ -1186,7 +1253,7 @@ void prepare_netlist_structs(int for_netlist)
my_free(839, &value);
my_free(840, &class);
my_free(841, &global_node);
dbg(2, "prepare_netlist_structs(): returning\n");
dbg(1, "prepare_netlist_structs(): returning\n");
/* avoid below call: it in turn calls prepare_netlist_structs(), too many side effects */
/* propagate_hilights(1, 0, XINSERT_NOREPLACE);*/
}

5
src/spice_netlist.c
View File

@ -114,6 +114,7 @@ static void spice_netlist(FILE *fd, int spice_stop )
top_sub = tclgetboolvar("top_subckt");
if(!spice_stop) {
dbg(1, "spice_netlist(): invoke prepare_netlist_structs for %s\n", xctx->current_name);
xctx->prep_net_structs = 0;
prepare_netlist_structs(1);
traverse_node_hash(); /* print all warnings about unconnected floatings etc */
@ -199,6 +200,7 @@ void global_spice_netlist(int global) /* netlister driver */
split_f = tclgetboolvar("split_files");
top_sub = tclgetboolvar("top_subckt");
dbg(1, "global_spice_netlist(): invoking push_undo()\n");
xctx->push_undo();
xctx->netlist_unconn_cnt=0; /* unique count of unconnected pins while netlisting */
statusmsg("",2); /* clear infowindow */
@ -351,6 +353,7 @@ void global_spice_netlist(int global) /* netlister driver */
unselect_all(1);
remove_symbols(); /* 20161205 ensure all unused symbols purged before descending hierarchy */
/* reload data without popping undo stack, this populates embedded symbols if any */
dbg(1, "global_spice_netlist(): invoking pop_undo(2, 0)\n");
xctx->pop_undo(2, 0);
/* link_symbols_to_instances(-1); */ /* done in xctx->pop_undo() */
my_strdup(469, &xctx->sch_path[xctx->currsch+1], xctx->sch_path[xctx->currsch]);
@ -389,8 +392,10 @@ void global_spice_netlist(int global) /* netlister driver */
my_strncpy(xctx->sch[xctx->currsch] , "", S(xctx->sch[xctx->currsch]));
xctx->currsch--;
unselect_all(1);
dbg(1, "global_spice_netlist(): invoking pop_undo(0, 0)\n");
xctx->pop_undo(0, 0);
my_strncpy(xctx->current_name, rel_sym_path(xctx->sch[xctx->currsch]), S(xctx->current_name));
dbg(1, "spice_netlist(): invoke prepare_netlist_structs for %s\n", xctx->current_name);
prepare_netlist_structs(1); /* so 'lab=...' attributes for unnamed nets are set */
/* symbol vs schematic pin check, we do it here since now we have ALL symbols loaded */
sym_vs_sch_pins();

251
xschem_library/examples/test_doublepin.sch
View File

@ -24,110 +24,207 @@ vvss vss 0 dc 0
.tran 1n 200n}
E {}
T {OK!} 470 -750 0 0 1 1 {layer=4}
T {OK!} 470 -1010 0 0 1 1 {layer=4}
T {OK!} 470 -1260 0 0 1 1 {layer=4}
T {Spice netlist allows duplicated pins on symbols} 20 -1350 0 0 1 1 {}
T {OK!} 470 -490 0 0 1 1 {layer=4}
N 450 -660 600 -660 {
T {OK!} 500 -1020 0 0 1 1 {layer=4}
T {OK!} 500 -1250 0 0 1 1 {layer=4}
T {OK!} 500 -1480 0 0 1 1 {layer=4}
T {Spice netlist allows duplicated pins on symbols} 50 -1570 0 0 1 1 {}
T {OK!} 500 -790 0 0 1 1 {layer=4}
T {OK!} 500 -580 0 0 1 1 {layer=4}
T {OK!} 1320 -1160 0 0 1 1 {layer=4}
T {OK!} 1320 -1430 0 0 1 1 {layer=4}
T {OK!} 500 -350 0 0 1 1 {layer=4}
N 480 -930 630 -930 {
lab=RRSSTT}
N 450 -640 600 -640 {
N 480 -910 630 -910 {
lab=CCKK}
N 450 -620 600 -620 {
N 480 -890 630 -890 {
lab=AA}
N 450 -600 600 -600 {
N 480 -870 630 -870 {
lab=BB}
N 450 -560 480 -560 {
N 480 -830 510 -830 {
lab=ZZ5}
N 900 -560 930 -560 {
N 930 -830 960 -830 {
lab=ZZ6}
N 450 -820 480 -820 {
N 480 -1060 510 -1060 {
lab=ZZ3}
N 900 -820 930 -820 {
N 930 -1060 960 -1060 {
lab=ZZ4}
N 450 -1070 480 -1070 {
N 480 -1290 510 -1290 {
lab=ZZ1}
N 900 -1070 930 -1070 {
N 930 -1290 960 -1290 {
lab=ZZ2}
N 450 -1170 600 -1170 {
N 480 -1390 630 -1390 {
lab=RRSSTT}
N 450 -1150 600 -1150 {
N 480 -1370 630 -1370 {
lab=CCKK}
N 450 -1130 600 -1130 {
N 480 -1350 630 -1350 {
lab=AA}
N 450 -1110 600 -1110 {
N 480 -1330 630 -1330 {
lab=BB}
N 450 -410 630 -410 {
N 480 -720 660 -720 {
lab=RRSSTT}
N 450 -390 630 -390 {
N 480 -700 660 -700 {
lab=CCKK}
N 450 -370 630 -370 {
N 480 -680 660 -680 {
lab=AA}
N 450 -350 630 -350 {
N 480 -660 660 -660 {
lab=BB}
N 450 -310 480 -310 {
N 480 -620 510 -620 {
lab=ZZ7}
N 600 -310 630 -310 {
N 630 -620 660 -620 {
lab=ZZ8}
N 930 -410 1050 -410 {
N 960 -720 1080 -720 {
lab=RRSSTT}
N 930 -390 1050 -390 {
N 960 -700 1080 -700 {
lab=CCKK}
N 930 -370 1050 -370 {
N 960 -680 1080 -680 {
lab=AA}
N 930 -350 1050 -350 {
N 960 -660 1080 -660 {
lab=BB}
N 1350 -310 1380 -310 {
N 1380 -620 1410 -620 {
lab=ZZ9}
C {doublepin.sym} 1200 -360 0 0 {name=x9}
C {doublepin.sym} 780 -360 0 1 {name=x8}
C {doublepin.sym} 750 -610 0 0 {name=x2}
C {lab_wire.sym} 520 -620 0 0 {name=l2 sig_type=std_logic lab=AA}
C {lab_pin.sym} 480 -560 0 1 {name=p3 lab=ZZ5}
C {lab_pin.sym} 930 -560 0 1 {name=p5 lab=ZZ6}
C {lab_wire.sym} 520 -660 0 0 {name=l3 sig_type=std_logic lab=RRSSTT}
C {lab_wire.sym} 520 -640 0 0 {name=l4 sig_type=std_logic lab=CCKK}
C {lab_wire.sym} 520 -600 0 0 {name=l5 sig_type=std_logic lab=BB}
C {doublepin.sym} 300 -870 0 0 {name=x3}
C {doublepin.sym} 750 -870 0 0 {name=x4}
C {lab_pin.sym} 150 -880 0 0 {name=l6 sig_type=std_logic lab=AA}
C {lab_pin.sym} 480 -820 0 1 {name=p1 lab=ZZ3}
C {lab_pin.sym} 930 -820 0 1 {name=p2 lab=ZZ4}
C {lab_pin.sym} 150 -920 0 0 {name=l7 sig_type=std_logic lab=RRSSTT}
C {lab_pin.sym} 150 -900 0 0 {name=l8 sig_type=std_logic lab=CCKK}
C {lab_pin.sym} 150 -860 0 0 {name=l9 sig_type=std_logic lab=BB}
C {lab_pin.sym} 900 -880 0 1 {name=l10 sig_type=std_logic lab=AA}
C {lab_pin.sym} 900 -920 0 1 {name=l11 sig_type=std_logic lab=RRSSTT}
C {lab_pin.sym} 900 -900 0 1 {name=l12 sig_type=std_logic lab=CCKK}
C {lab_pin.sym} 900 -860 0 1 {name=l13 sig_type=std_logic lab=BB}
C {doublepin.sym} 300 -1120 0 0 {name=x5}
C {doublepin.sym} 750 -1120 0 0 {name=x6}
C {lab_pin.sym} 150 -1130 0 0 {name=l14 sig_type=std_logic lab=AA}
C {lab_pin.sym} 480 -1070 0 1 {name=p4 lab=ZZ1}
C {lab_pin.sym} 930 -1070 0 1 {name=p6 lab=ZZ2}
C {lab_pin.sym} 150 -1170 0 0 {name=l15 sig_type=std_logic lab=RRSSTT}
C {lab_pin.sym} 150 -1150 0 0 {name=l16 sig_type=std_logic lab=CCKK}
C {lab_pin.sym} 150 -1110 0 0 {name=l17 sig_type=std_logic lab=BB}
C {lab_pin.sym} 900 -1130 0 1 {name=l18 sig_type=std_logic lab=AA}
C {lab_pin.sym} 900 -1170 0 1 {name=l19 sig_type=std_logic lab=RRSSTT}
C {lab_pin.sym} 900 -1150 0 1 {name=l20 sig_type=std_logic lab=CCKK}
C {lab_pin.sym} 900 -1110 0 1 {name=l21 sig_type=std_logic lab=BB}
C {lab_wire.sym} 520 -1130 0 0 {name=l22 sig_type=std_logic lab=AA}
C {lab_wire.sym} 520 -1170 0 0 {name=l23 sig_type=std_logic lab=RRSSTT}
C {lab_wire.sym} 520 -1150 0 0 {name=l24 sig_type=std_logic lab=CCKK}
C {lab_wire.sym} 520 -1110 0 0 {name=l25 sig_type=std_logic lab=BB}
C {lab_pin.sym} 150 -350 0 0 {name=l33 sig_type=std_logic lab=BB}
C {doublepin.sym} 300 -610 0 0 {name=x1}
C {lab_pin.sym} 480 -310 0 1 {name=p7 lab=ZZ7}
C {lab_pin.sym} 600 -310 0 0 {name=p8 lab=ZZ8}
C {lab_pin.sym} 150 -370 0 0 {name=l30 sig_type=std_logic lab=AA}
C {lab_pin.sym} 150 -410 0 0 {name=l31 sig_type=std_logic lab=RRSSTT}
C {lab_pin.sym} 150 -390 0 0 {name=l32 sig_type=std_logic lab=CCKK}
C {doublepin.sym} 300 -360 0 0 {name=x7}
N 480 -510 660 -510 {
lab=#net9}
N 480 -490 660 -490 {
lab=#net10}
N 480 -470 660 -470 {
lab=#net11}
N 480 -450 660 -450 {
lab=#net12}
N 480 -410 510 -410 {
lab=ZZ12}
N 630 -410 660 -410 {
lab=ZZ11}
N 960 -510 1080 -510 {
lab=#net13}
N 960 -490 1080 -490 {
lab=#net14}
N 960 -470 1080 -470 {
lab=#net15}
N 960 -450 1080 -450 {
lab=#net16}
N 1380 -410 1410 -410 {
lab=ZZ10}
N 1520 -990 1550 -990 {
lab=ZZ13}
N 1170 -1090 1220 -1090 {
lab=RRSSTT}
N 1170 -1070 1220 -1070 {
lab=CCKK}
N 1170 -1050 1220 -1050 {
lab=AA}
N 1170 -1030 1220 -1030 {
lab=BB}
N 1190 -1250 1220 -1250 {
lab=ZZ14}
N 1170 -1350 1220 -1350 {
lab=RRSSTT}
N 1170 -1330 1220 -1330 {
lab=CCKK}
N 1170 -1310 1220 -1310 {
lab=AA}
N 1170 -1290 1220 -1290 {
lab=BB}
N 480 -280 660 -280 {
lab=#net25}
N 480 -260 660 -260 {
lab=#net26}
N 480 -240 660 -240 {
lab=#net27}
N 480 -220 660 -220 {
lab=#net28}
N 480 -180 510 -180 {
lab=ZZ17}
N 630 -180 660 -180 {
lab=ZZ16}
N 960 -280 1080 -280 {
lab=#net29}
N 960 -260 1080 -260 {
lab=#net30}
N 960 -240 1080 -240 {
lab=#net31}
N 960 -220 1080 -220 {
lab=#net32}
N 1380 -180 1410 -180 {
lab=ZZ15}
N 10 -260 40 -260 {
lab=#net33}
N 120 -260 180 -260 {
lab=#net34}
C {doublepin.sym} 1230 -670 0 0 {name=x9}
C {doublepin.sym} 810 -670 0 1 {name=x8}
C {doublepin.sym} 780 -880 0 0 {name=x2}
C {lab_wire.sym} 550 -890 0 0 {name=l2 sig_type=std_logic lab=AA}
C {lab_pin.sym} 510 -830 0 1 {name=p3 lab=ZZ5}
C {lab_pin.sym} 960 -830 0 1 {name=p5 lab=ZZ6}
C {lab_wire.sym} 550 -930 0 0 {name=l3 sig_type=std_logic lab=RRSSTT}
C {lab_wire.sym} 550 -910 0 0 {name=l4 sig_type=std_logic lab=CCKK}
C {lab_wire.sym} 550 -870 0 0 {name=l5 sig_type=std_logic lab=BB}
C {doublepin.sym} 330 -1110 0 0 {name=x3}
C {doublepin.sym} 780 -1110 0 0 {name=x4}
C {lab_pin.sym} 180 -1120 0 0 {name=l6 sig_type=std_logic lab=AA}
C {lab_pin.sym} 510 -1060 0 1 {name=p1 lab=ZZ3}
C {lab_pin.sym} 960 -1060 0 1 {name=p2 lab=ZZ4}
C {lab_pin.sym} 180 -1160 0 0 {name=l7 sig_type=std_logic lab=RRSSTT}
C {lab_pin.sym} 180 -1140 0 0 {name=l8 sig_type=std_logic lab=CCKK}
C {lab_pin.sym} 180 -1100 0 0 {name=l9 sig_type=std_logic lab=BB}
C {lab_pin.sym} 930 -1120 0 1 {name=l10 sig_type=std_logic lab=AA}
C {lab_pin.sym} 930 -1160 0 1 {name=l11 sig_type=std_logic lab=RRSSTT}
C {lab_pin.sym} 930 -1140 0 1 {name=l12 sig_type=std_logic lab=CCKK}
C {lab_pin.sym} 930 -1100 0 1 {name=l13 sig_type=std_logic lab=BB}
C {doublepin.sym} 330 -1340 0 0 {name=x5}
C {doublepin.sym} 780 -1340 0 0 {name=x6}
C {lab_pin.sym} 180 -1350 0 0 {name=l14 sig_type=std_logic lab=AA}
C {lab_pin.sym} 510 -1290 0 1 {name=p4 lab=ZZ1}
C {lab_pin.sym} 960 -1290 0 1 {name=p6 lab=ZZ2}
C {lab_pin.sym} 180 -1390 0 0 {name=l15 sig_type=std_logic lab=RRSSTT}
C {lab_pin.sym} 180 -1370 0 0 {name=l16 sig_type=std_logic lab=CCKK}
C {lab_pin.sym} 180 -1330 0 0 {name=l17 sig_type=std_logic lab=BB}
C {lab_pin.sym} 930 -1350 0 1 {name=l18 sig_type=std_logic lab=AA}
C {lab_pin.sym} 930 -1390 0 1 {name=l19 sig_type=std_logic lab=RRSSTT}
C {lab_pin.sym} 930 -1370 0 1 {name=l20 sig_type=std_logic lab=CCKK}
C {lab_pin.sym} 930 -1330 0 1 {name=l21 sig_type=std_logic lab=BB}
C {lab_wire.sym} 550 -1350 0 0 {name=l22 sig_type=std_logic lab=AA}
C {lab_wire.sym} 550 -1390 0 0 {name=l23 sig_type=std_logic lab=RRSSTT}
C {lab_wire.sym} 550 -1370 0 0 {name=l24 sig_type=std_logic lab=CCKK}
C {lab_wire.sym} 550 -1330 0 0 {name=l25 sig_type=std_logic lab=BB}
C {lab_pin.sym} 180 -660 0 0 {name=l33 sig_type=std_logic lab=BB}
C {doublepin.sym} 330 -880 0 0 {name=x1}
C {lab_pin.sym} 510 -620 0 1 {name=p7 lab=ZZ7}
C {lab_pin.sym} 630 -620 0 0 {name=p8 lab=ZZ8}
C {lab_pin.sym} 180 -680 0 0 {name=l30 sig_type=std_logic lab=AA}
C {lab_pin.sym} 180 -720 0 0 {name=l31 sig_type=std_logic lab=RRSSTT}
C {lab_pin.sym} 180 -700 0 0 {name=l32 sig_type=std_logic lab=CCKK}
C {doublepin.sym} 330 -670 0 0 {name=x7}
C {ipin.sym} 100 -80 0 0 { name=p9 lab=RRSSTT }
C {ipin.sym} 100 -100 0 0 { name=p10 lab=CCKK }
C {ipin.sym} 100 -120 0 0 { name=p11 lab=BB }
C {ipin.sym} 100 -140 0 0 { name=p12 lab=AA }
C {opin.sym} 270 -120 0 0 { name=p13 lab=ZZ[9..1]}
C {opin.sym} 270 -120 0 0 { name=p13 lab=ZZ[17..1]}
C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
C {lab_pin.sym} 1380 -310 0 1 {name=p8 lab=ZZ9}
C {lab_pin.sym} 1410 -620 0 1 {name=p8 lab=ZZ9}
C {doublepin.sym} 1230 -460 0 0 {name=x10}
C {doublepin.sym} 810 -460 0 1 {name=x11}
C {lab_pin.sym} 510 -410 0 1 {name=p7 lab=ZZ12}
C {lab_pin.sym} 630 -410 0 0 {name=p8 lab=ZZ11}
C {doublepin.sym} 330 -460 0 0 {name=x12}
C {lab_pin.sym} 1410 -410 0 1 {name=p1 lab=ZZ10}
C {doublepin.sym} 1370 -1040 0 0 {name=x13}
C {lab_pin.sym} 1550 -990 0 1 {name=p2 lab=ZZ13}
C {lab_pin.sym} 1520 -1050 0 1 {name=l10 sig_type=std_logic lab=AA}
C {lab_pin.sym} 1520 -1090 0 1 {name=l11 sig_type=std_logic lab=RRSSTT}
C {lab_pin.sym} 1520 -1070 0 1 {name=l12 sig_type=std_logic lab=CCKK}
C {lab_pin.sym} 1520 -1030 0 1 {name=l13 sig_type=std_logic lab=BB}
C {doublepin.sym} 1370 -1300 0 1 {name=x14}
C {lab_pin.sym} 1190 -1250 0 0 {name=p2 lab=ZZ14}
C {lab_pin.sym} 1520 -1310 0 1 {name=l10 sig_type=std_logic lab=AA}
C {lab_pin.sym} 1520 -1350 0 1 {name=l11 sig_type=std_logic lab=RRSSTT}
C {lab_pin.sym} 1520 -1330 0 1 {name=l12 sig_type=std_logic lab=CCKK}
C {lab_pin.sym} 1520 -1290 0 1 {name=l13 sig_type=std_logic lab=BB}
C {doublepin.sym} 330 -230 0 0 {name=x17}
C {doublepin.sym} 810 -230 0 1 {name=x16}
C {lab_pin.sym} 510 -180 0 1 {name=p7 lab=ZZ17}
C {lab_pin.sym} 630 -180 0 0 {name=p8 lab=ZZ16}
C {doublepin.sym} 1230 -230 0 0 {name=x15}
C {lab_pin.sym} 1410 -180 0 1 {name=p1 lab=ZZ15}
C {inv_ngspice.sym} 80 -260 0 0 {name=x18 ROUT=1000}