sort symbol pins if key pinnumber is present on all of them

src/save.c

@@ -2730,6 +2730,63 @@ static void calc_symbol_bbox(int pos)
   xctx->sym[pos].maxy = boundbox.y2;
 }
 
+static int order_changed;
+static int pin_compare(const void *a, const void *b)
+{
+  int pinnumber_a, pinnumber_b;
+  const char *tmp;
+  int result;
+  
+  tmp = get_tok_value(((xRect *)a)->prop_ptr, "pinnumber", 0);
+  pinnumber_a = tmp[0] ?  atoi(tmp) : -1;
+  tmp = get_tok_value(((xRect *)b)->prop_ptr, "pinnumber", 0);
+  pinnumber_b = tmp[0] ?atoi(tmp) : -1;
+  result =  pinnumber_a < pinnumber_b ? -1 : pinnumber_a == pinnumber_b ? 0 : 1;
+  if(result >= 0) order_changed = 1;
+  return result;
+}
+
+void sort_symbol_pins(int i)
+{
+  xSymbol *sym = xctx->sym;
+  xRect *pin_array = sym[i].rect[PINLAYER];
+  int j, do_sort = 0;
+  int npins = sym[i].rects[PINLAYER];
+  const char *pinnumber;
+  order_changed = 0;
+
+  if(npins > 0) do_sort = 1; /* no pins, no sort... */
+  /* do not sort if some pins don't have pinnumber attribute */
+  for(j = 0; j < npins; j++) {
+    pinnumber = get_tok_value(pin_array[j].prop_ptr, "pinnumber", 0);
+    if(!pinnumber[0]) do_sort = 0;
+  }
+  if(do_sort) {
+    const char *pinname;
+    
+    if(debug_var >= 1) for(j = 0; j < npins; j++) {
+      pinname = get_tok_value(pin_array[j].prop_ptr, "name", 0);
+      dbg(0, "pin name=%s\n", pinname);
+    }
+    qsort(pin_array, npins, sizeof(xRect), pin_compare);
+    if(order_changed) {
+      dbg(0, "Symbol %s has pinnumber attributes on pins. Pins will be sorted\n", sym[i].name);
+      /* 
+      tclvareval("alert_ {",
+                 "About to load symbol ", sym[i].name, ".\n",
+                 "It has pinnumber attributes on pins, so pins will be sorted\n",
+                 "To avoid this message descend into ", sym[i].name, "\n",
+                 "and save the symbol.",
+                 "}", NULL);
+      */
+    }
+    if(debug_var >= 1) for(j = 0; j < npins; j++) {
+      pinname = get_tok_value(pin_array[j].prop_ptr, "name", 0);
+      dbg(1, "pin name=%s\n", pinname);
+    }
+  }
+}
+
 /* Global (or static global) variables used:
  * cadlayers
  * errfp
@@ -3367,6 +3424,7 @@ int load_sym_def(const char *name, FILE *embed_fd)
   my_free(912, &symname);
   my_free(913, &symtype);
   recursion_counter--;
+  sort_symbol_pins(xctx->symbols - 1); /* sort on pinnumber if given in pins */
   return 1;
 }
 

src/xschem.h

@@ -1119,6 +1119,7 @@ extern const char *rel_sym_path(const char *s);
 extern const char *abs_sym_path(const char *s, const char *ext);
 extern const char *add_ext(const char *f, const char *ext);
 extern void make_symbol(void);
+extern void sort_symbol_pins(int i); /* sort based on pinnumber pin attribute if present */
 extern void make_schematic_symbol_from_sel(void);
 extern const char *get_sym_template(char *s, char *extra);
 /* bit0: invoke change_linewidth(), bit1: centered zoom */

xschem_library/logic/ram.sch

@@ -132,14 +132,22 @@ T {add0} 230 -425 0 0 0.3 0.3 {}
 T {data0} 310 -365 0 0 0.3 0.3 {}
 T {prech} 215 -550 0 0 0.18 0.3 {}
 T {sense} 260 -550 0 0 0.18 0.3 {}
-C {opin.sym} 340 -220 0 0 {name=p10 lab=DOUT[width-1:0] verilog_type=wire}
-C {ipin.sym} 200 -220 0 0 {name=p8 lab=DIN[width-1:0]}
-C {ipin.sym} 200 -110 0 0 {name=p12 lab=CK}
-C {ipin.sym} 200 -140 0 0 {name=p1 lab=OEN}
-C {ipin.sym} 200 -260 0 0 {name=p3 lab=ADD[dim-1:0]}
-C {ipin.sym} 200 -190 0 0 {name=p2 lab=WEN}
-C {ipin.sym} 200 -170 0 0 {name=p4 lab=CEN}
-C {ipin.sym} 200 -240 0 0 {name=p5 lab=M[width-1:0]}
+C {opin.sym} 340 -220 0 0 {name=p10 lab=DOUT[width-1:0] verilog_type=wire
+pinnumber=8}
+C {ipin.sym} 200 -220 0 0 {name=p8 lab=DIN[width-1:0]
+pinnumber=5}
+C {ipin.sym} 200 -110 0 0 {name=p12 lab=CK
+pinnumber=1}
+C {ipin.sym} 200 -140 0 0 {name=p1 lab=OEN
+pinnumber=2}
+C {ipin.sym} 200 -260 0 0 {name=p3 lab=ADD[dim-1:0]
+pinnumber=7}
+C {ipin.sym} 200 -190 0 0 {name=p2 lab=WEN
+pinnumber=4}
+C {ipin.sym} 200 -170 0 0 {name=p4 lab=CEN
+pinnumber=3}
+C {ipin.sym} 200 -240 0 0 {name=p5 lab=M[width-1:0]
+pinnumber=6}
 C {verilog_timescale.sym} 710 -197.5 0 0 {name=s1 timestep="1ps" precision="1ps" }
 C {title.sym} 160 -30 0 0 {name=l2}
 C {use.sym} 360 -130 0 0 {------------------------------------------------

xschem_library/logic/ram.sym

@@ -1,4 +1,5 @@
-v {xschem version=3.0.0 file_version=1.2 }
+v {xschem version=3.1.0 file_version=1.2
+}
 G {}
 K {type=subcircuit
 vhdl_stop=true
@@ -23,14 +24,15 @@ L 4 -150 0 -130 0 {}
 L 4 -150 20 -130 20 {}
 L 4 -150 40 -130 40 {}
 L 4 -150 60 -130 60 {}
-B 5 -152.5 -62.5 -147.5 -57.5 {name=ADD[dim-1:0] dir=in }
-B 5 -152.5 -42.5 -147.5 -37.5 {name=M[width-1:0] dir=in }
-B 5 147.5 -62.5 152.5 -57.5 {name=DOUT[width-1:0] verilog_type=wire dir=out }
-B 5 -152.5 -22.5 -147.5 -17.5 {name=DIN[width-1:0] dir=in }
-B 5 -152.5 -2.5 -147.5 2.5 {name=WEN dir=in }
-B 5 -152.5 17.5 -147.5 22.5 {name=CEN dir=in }
-B 5 -152.5 37.5 -147.5 42.5 {name=OEN dir=in }
-B 5 -152.5 57.5 -147.5 62.5 {name=CK dir=in }
+B 5 -152.5 -62.5 -147.5 -57.5 {name=ADD[dim-1:0] dir=in pinnumber=7}
+B 5 -152.5 -42.5 -147.5 -37.5 {name=M[width-1:0] dir=in pinnumber=6}
+B 5 147.5 -62.5 152.5 -57.5 {name=DOUT[width-1:0] verilog_type=wire dir=out
+pinnumber=8 }
+B 5 -152.5 -22.5 -147.5 -17.5 {name=DIN[width-1:0] dir=in pinnumber=5}
+B 5 -152.5 -2.5 -147.5 2.5 {name=WEN dir=in pinnumber=4}
+B 5 -152.5 17.5 -147.5 22.5 {name=CEN dir=in pinnumber=3}
+B 5 -152.5 37.5 -147.5 42.5 {name=OEN dir=in pinnumber=2}
+B 5 -152.5 57.5 -147.5 62.5 {name=CK dir=in pinnumber=1}
 T {@symname} -31.5 -6 0 0 0.3 0.3 {}
 T {@name} 135 -82 0 0 0.2 0.2 {}
 T {ADD[dim-1:0]} -125 -64 0 0 0.2 0.2 {}
@@ -41,6 +43,3 @@ T {WEN} -125 -4 0 0 0.2 0.2 {}
 T {CEN} -125 16 0 0 0.2 0.2 {}
 T {OEN} -125 36 0 0 0.2 0.2 {}
 T {CK} -125 56 0 0 0.2 0.2 {}
-T {2} -115 -84 0 0 0.2 0.2 {}
-T {@dim} -105 -94 0 0 0.2 0.2 {}
-T {x @width} -95 -84 0 0 0.2 0.2 {}