better parsing xxx='<expr>' or xxx={expr} patterns in flatten.awk. Doc upcates, test circuit updates.
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@ -23,7 +23,11 @@ p{padding: 15px 30px 10px;}
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</p>
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<ul>
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<li> Install Xschem. Follow the Manual <a href="install_xschem.html">Install instructions</a></li>
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<p class="important">
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If you install xschem from sources ensure no xschem package is already installed in your linux system. Packaged xschem versions
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are too old so you should remove the installed package. The command for ubuntu/Debian systems is
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<kbd>sudo apt-get remove --purge xschem </kbd><br>
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</p><br>
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<li> Install the Magic VLSI layout editor. Instructions <a href="http://opencircuitdesign.com/magic/index.html">here.</a></li>
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<li> Install <a href="https://sourceforge.net/projects/ngspice/">ngspice</a>, by cloning the git source repository
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@ -45,9 +45,12 @@ BEGIN{
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nodes["I"]=2; nodes["C"]=2; nodes["L"]=2; nodes["Q"]=3
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nodes["E"]=4; nodes["G"]=4; nodes["H"]=2; nodes["F"]=2
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nodes["B"]=2; nodes["S"]=4
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controlblock = 0
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}
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{
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if( toupper($0) !~/^(\.INCLUDE|\.LIB|\.WRITE| *WRITE)/) $0=toupper($0)
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if(toupper($0) ~ /^[ \t]*\.CONTROL/) controlblock = 1
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if(controlblock == 0 && toupper($0) !~/^(\.INCLUDE|\.LIB|\.WRITE| *WRITE)/) $0=toupper($0)
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if(toupper($0) ~ /^[ \t]*\.ENDC/) controlblock = 0
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# allow to specify *.nodes[W]=2 or *.nodes["W"] = 2 metadata in the netlist for additional
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# custom devices nodes specification.
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if($0 ~/^[ \t]*\*\.[ \t]*NODES\["?[^]["]"?\][ \t]*=[ \t]*.*/) {
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@ -76,6 +79,8 @@ BEGIN{
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}
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END{
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for(j=0;j<lines;j++) a[j] = trim_quoted_spaces(a[j])
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devpattern = "^["
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for(j in nodes) {
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devpattern = devpattern j
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@ -84,6 +89,7 @@ END{
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for(j=0;j<lines;j++)
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{
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$0=a[j]
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if($1 ~ /\.GLOBAL/) # get global nodes
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for(i=2;i<=NF;i++) global[$i]=i;
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if($1 ~ /^\.SUBCKT/) # parse subckts
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@ -138,10 +144,14 @@ function expand(name, path, param,ports, # func. params
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paramarray2[parameter[1]]=parameter[2]
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}
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split(ports,portarray)
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controlblock = 0
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for(j=subckt[name , "first"]+1;j<subckt[name , "last"];j++)
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{
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if(a[j] ~ /^[ \t]*\.control/) controlblock = 1
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num=split(a[j],line)
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if(line[1] ~ /^X/ )
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if(controlblock) {
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print a[j]
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} else if(line[1] ~ /^X/ )
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{
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paramlist = ""; portlist = ""; subname=""
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for(k=num;k>=2;k--)
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@ -217,6 +227,7 @@ function expand(name, path, param,ports, # func. params
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}
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printf "\n"
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}
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if(a[j] ~ /^[ \t]*\.endc/) controlblock = 0
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}
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}
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@ -284,4 +295,18 @@ function general_sub(string,name,pathnode,portarray, nod, sss, state, last
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}
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sss=sss string
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return sss
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}
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}
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function trim_quoted_spaces(s, p, m)
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{
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p = ""
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while(match(s, /['{][^}']*['}]/)) {
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m = substr(s, RSTART, RLENGTH)
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gsub(/ /, "", m)
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p = p substr(s, 1, RSTART -1) m
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s = substr(s, RSTART + RLENGTH)
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}
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p = p s
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return p
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}
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@ -16,8 +16,8 @@ y1=-47
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y2=50
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divy=4
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subdivy=4
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x1=0.00824068
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x2=0.00893539
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x1=0.00823137
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x2=0.00892608
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divx=8
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subdivx=1
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dataset=0
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@ -34,8 +34,8 @@ y1=0
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y2=160
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divy=4
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subdivy=9
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x1=0.00824068
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x2=0.00893539
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x1=0.00823137
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x2=0.00892608
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divx=8
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subdivx=9
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dataset=0
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@ -52,8 +52,8 @@ y1=-0.19
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y2=160
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divy=4
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subdivy=9
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x1=0.00824068
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x2=0.00893539
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x1=0.00823137
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x2=0.00892608
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divx=8
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subdivx=9
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dataset=0
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@ -322,7 +322,7 @@ C {ngspice_get_expr.sym} 800 -1090 0 1 {name=r8
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node="[format %.4g [expr [ngspice::get_voltage e4] - [ngspice::get_voltage c7]]]"
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descr = veb
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}
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C {ngspice_get_expr.sym} 860 -1070 0 0 {name=r16
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C {ngspice_get_expr.sym} 880 -1070 0 0 {name=r16
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node="[format %.4g [expr [ngspice::get_current \{q4[ic]\}] / [ngspice::get_current \{q4[ib]\}] ] ]"
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descr = beta
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}
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@ -1,4 +1,5 @@
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v {xschem version=3.0.0 file_version=1.2 }
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v {xschem version=3.1.0 file_version=1.2
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}
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G {process
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begin
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A<='0';
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@ -217,7 +218,8 @@ C {use.sym} 40 -670 0 0 {------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;}
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C {ram.sym} 840 -630 0 0 {name=xcoderam dim=5 width=8 hex=1 datafile=ram.list}
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C {ram.sym} 840 -630 0 0 {name=xcoderam dim=5 width=8 hex=1 datafile=ram.list
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spice_ignore=true}
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C {lab_pin.sym} 990 -690 0 1 {name=p25 lab=DOUT[7:0]}
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C {lab_pin.sym} 690 -690 0 0 {name=p26 lab=ADD[4:0]}
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C {lab_pin.sym} 690 -650 0 0 {name=p27 lab=DIN[7:0]}
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@ -233,7 +235,7 @@ C {lab_pin.sym} 220 -220 0 1 {name=p37 lab=OEN verilog_type=reg}
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C {lab_pin.sym} 220 -200 0 1 {name=p38 lab=CK verilog_type=reg}
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C {lab_pin.sym} 220 -260 0 1 {name=p39 lab=CEN verilog_type=reg}
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C {lab_pin.sym} 220 -300 0 1 {name=p40 lab=M[7:0] verilog_type=reg}
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C {sync_reg.sym} 840 -810 0 0 {name=x8 width=8}
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C {sync_reg.sym} 840 -810 0 0 {name=x8 width=8 spice_ignore=true}
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C {lab_pin.sym} 740 -840 0 0 {name=p33 lab=DIN[7:0]}
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C {lab_pin.sym} 740 -780 0 0 {name=p41 lab=CK}
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C {lab_pin.sym} 740 -800 0 0 {name=p42 lab=BN}
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