better parsing xxx='<expr>' or xxx={expr} patterns in flatten.awk. Doc upcates, test circuit updates.

This commit is contained in:
Stefan Frederik 2022-10-20 20:25:49 +02:00
parent 506cf627cd
commit bc33261f90
4 changed files with 45 additions and 14 deletions

View File

@ -23,7 +23,11 @@ p{padding: 15px 30px 10px;}
</p>
<ul>
<li> Install Xschem. Follow the Manual <a href="install_xschem.html">Install instructions</a></li>
<p class="important">
If you install xschem from sources ensure no xschem package is already installed in your linux system. Packaged xschem versions
are too old so you should remove the installed package. The command for ubuntu/Debian systems is
<kbd>sudo apt-get remove --purge xschem </kbd><br>
</p><br>
<li> Install the Magic VLSI layout editor. Instructions <a href="http://opencircuitdesign.com/magic/index.html">here.</a></li>
<li> Install <a href="https://sourceforge.net/projects/ngspice/">ngspice</a>, by cloning the git source repository

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@ -45,9 +45,12 @@ BEGIN{
nodes["I"]=2; nodes["C"]=2; nodes["L"]=2; nodes["Q"]=3
nodes["E"]=4; nodes["G"]=4; nodes["H"]=2; nodes["F"]=2
nodes["B"]=2; nodes["S"]=4
controlblock = 0
}
{
if( toupper($0) !~/^(\.INCLUDE|\.LIB|\.WRITE| *WRITE)/) $0=toupper($0)
if(toupper($0) ~ /^[ \t]*\.CONTROL/) controlblock = 1
if(controlblock == 0 && toupper($0) !~/^(\.INCLUDE|\.LIB|\.WRITE| *WRITE)/) $0=toupper($0)
if(toupper($0) ~ /^[ \t]*\.ENDC/) controlblock = 0
# allow to specify *.nodes[W]=2 or *.nodes["W"] = 2 metadata in the netlist for additional
# custom devices nodes specification.
if($0 ~/^[ \t]*\*\.[ \t]*NODES\["?[^]["]"?\][ \t]*=[ \t]*.*/) {
@ -76,6 +79,8 @@ BEGIN{
}
END{
for(j=0;j<lines;j++) a[j] = trim_quoted_spaces(a[j])
devpattern = "^["
for(j in nodes) {
devpattern = devpattern j
@ -84,6 +89,7 @@ END{
for(j=0;j<lines;j++)
{
$0=a[j]
if($1 ~ /\.GLOBAL/) # get global nodes
for(i=2;i<=NF;i++) global[$i]=i;
if($1 ~ /^\.SUBCKT/) # parse subckts
@ -138,10 +144,14 @@ function expand(name, path, param,ports, # func. params
paramarray2[parameter[1]]=parameter[2]
}
split(ports,portarray)
controlblock = 0
for(j=subckt[name , "first"]+1;j<subckt[name , "last"];j++)
{
if(a[j] ~ /^[ \t]*\.control/) controlblock = 1
num=split(a[j],line)
if(line[1] ~ /^X/ )
if(controlblock) {
print a[j]
} else if(line[1] ~ /^X/ )
{
paramlist = ""; portlist = ""; subname=""
for(k=num;k>=2;k--)
@ -217,6 +227,7 @@ function expand(name, path, param,ports, # func. params
}
printf "\n"
}
if(a[j] ~ /^[ \t]*\.endc/) controlblock = 0
}
}
@ -284,4 +295,18 @@ function general_sub(string,name,pathnode,portarray, nod, sss, state, last
}
sss=sss string
return sss
}
}
function trim_quoted_spaces(s, p, m)
{
p = ""
while(match(s, /['{][^}']*['}]/)) {
m = substr(s, RSTART, RLENGTH)
gsub(/ /, "", m)
p = p substr(s, 1, RSTART -1) m
s = substr(s, RSTART + RLENGTH)
}
p = p s
return p
}

View File

@ -16,8 +16,8 @@ y1=-47
y2=50
divy=4
subdivy=4
x1=0.00824068
x2=0.00893539
x1=0.00823137
x2=0.00892608
divx=8
subdivx=1
dataset=0
@ -34,8 +34,8 @@ y1=0
y2=160
divy=4
subdivy=9
x1=0.00824068
x2=0.00893539
x1=0.00823137
x2=0.00892608
divx=8
subdivx=9
dataset=0
@ -52,8 +52,8 @@ y1=-0.19
y2=160
divy=4
subdivy=9
x1=0.00824068
x2=0.00893539
x1=0.00823137
x2=0.00892608
divx=8
subdivx=9
dataset=0
@ -322,7 +322,7 @@ C {ngspice_get_expr.sym} 800 -1090 0 1 {name=r8
node="[format %.4g [expr [ngspice::get_voltage e4] - [ngspice::get_voltage c7]]]"
descr = veb
}
C {ngspice_get_expr.sym} 860 -1070 0 0 {name=r16
C {ngspice_get_expr.sym} 880 -1070 0 0 {name=r16
node="[format %.4g [expr [ngspice::get_current \{q4[ic]\}] / [ngspice::get_current \{q4[ib]\}] ] ]"
descr = beta
}

View File

@ -1,4 +1,5 @@
v {xschem version=3.0.0 file_version=1.2 }
v {xschem version=3.1.0 file_version=1.2
}
G {process
begin
A<='0';
@ -217,7 +218,8 @@ C {use.sym} 40 -670 0 0 {------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;}
C {ram.sym} 840 -630 0 0 {name=xcoderam dim=5 width=8 hex=1 datafile=ram.list}
C {ram.sym} 840 -630 0 0 {name=xcoderam dim=5 width=8 hex=1 datafile=ram.list
spice_ignore=true}
C {lab_pin.sym} 990 -690 0 1 {name=p25 lab=DOUT[7:0]}
C {lab_pin.sym} 690 -690 0 0 {name=p26 lab=ADD[4:0]}
C {lab_pin.sym} 690 -650 0 0 {name=p27 lab=DIN[7:0]}
@ -233,7 +235,7 @@ C {lab_pin.sym} 220 -220 0 1 {name=p37 lab=OEN verilog_type=reg}
C {lab_pin.sym} 220 -200 0 1 {name=p38 lab=CK verilog_type=reg}
C {lab_pin.sym} 220 -260 0 1 {name=p39 lab=CEN verilog_type=reg}
C {lab_pin.sym} 220 -300 0 1 {name=p40 lab=M[7:0] verilog_type=reg}
C {sync_reg.sym} 840 -810 0 0 {name=x8 width=8}
C {sync_reg.sym} 840 -810 0 0 {name=x8 width=8 spice_ignore=true}
C {lab_pin.sym} 740 -840 0 0 {name=p33 lab=DIN[7:0]}
C {lab_pin.sym} 740 -780 0 0 {name=p41 lab=CK}
C {lab_pin.sym} 740 -800 0 0 {name=p42 lab=BN}