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add @path attribute for spice/verilog/vhdl/tedax backends

This commit is contained in:
Stefan Frederik 2022-11-02 00:47:59 +01:00
parent 74dad2e034
commit 4bb321af68
2 changed files with 22 additions and 1 deletions
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2
doc/xschem_man/graphs.html
View File

@ -185,7 +185,7 @@ p{padding: 15px 30px 10px;}
<li><kbd>log10()</kbd> Base 10 logarithm</li>
<li><kbd>db20()</kbd> Value in deciBel (20 * log10(n))</li>
<li><kbd>avg()</kbd> Average</li>
<li><kbd>prev()</kbd> Delete waveform by one point (at any x-axis position take the previous value)</li>
<li><kbd>prev()</kbd> Delay waveform by one point (at any x-axis position take the previous value)</li>
<li><kbd>deriv()</kbd> Derivative w.r.t. graph sweep variable</li>
<li><kbd>deriv0()</kbd> Derivative w.r.t. simulation (index 0) sweep variable</li>
<li><kbd>integ()</kbd> Integration</li>

21
src/token.c
View File

@ -768,6 +768,10 @@ static void print_vhdl_primitive(FILE *fd, int inst) /* netlist primitives, 200
}
else fprintf(fd, "%s", value);
}
else if(strcmp(token,"@path")==0)
{
fprintf( fd, "%s",xctx->sch_path[xctx->currsch] + 1);
}
else if(strcmp(token,"@symname")==0) /* of course symname must not be present */
/* in hash table */
{
@ -1755,6 +1759,15 @@ int print_spice_element(FILE *fd, int inst)
/* fputs(value,fd); */
}
}
else if (strcmp(token,"@path")==0) /* of course symname must not be present in attributes */
{
const char *s = xctx->sch_path[xctx->currsch] + 1;
tmp = strlen(s) +100 ; /* always make room for some extra chars
* so 1-char writes to result do not need reallocs */
STR_ALLOC(&result, tmp + result_pos, &size);
result_pos += my_snprintf(result + result_pos, tmp, "%s", s);
/* fputs(s,fd); */
}
else if (strcmp(token,"@symname")==0) /* of course symname must not be present in attributes */
{
const char *s = skip_dir(xctx->inst[inst].name);
@ -2117,6 +2130,10 @@ void print_tedax_element(FILE *fd, int inst)
{
fputs(value,fd);
}
else if(strcmp(token,"@path")==0)
{
fputs(xctx->sch_path[xctx->currsch] + 1, fd);
}
else if(strcmp(token,"@symname")==0) /* of course symname must not be present */
/* in hash table */
{
@ -2345,6 +2362,10 @@ static void print_verilog_primitive(FILE *fd, int inst) /* netlist switch level
}
else fprintf(fd, "%s", value);
}
else if(strcmp(token,"@path")==0)
{
fputs(xctx->sch_path[xctx->currsch] + 1, fd);
}
else if(strcmp(token,"@symname")==0) /* of course symname must not be present */
/* in hash table */
{