stefan schippers
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a50bfb3622
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when doing spice netlisting if top level has a symbol (and the symbol has i/o ports) use the symbol for printing the top level subckt port list. This ensures same port ordering when netlisting a testbench containing a component and netlisting the component itself. Tab context menu: open Symbol / open Schematic will use the search_schematic setting and search counterpart accordingly.
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2023-11-16 01:26:55 +01:00 |
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stefan schippers
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be914f4ee4
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raw_read(): clear text floater caches if a rawfile is successfully read
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2023-11-15 21:04:10 +01:00 |
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stefan schippers
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0df3cfcc7b
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better recognize global nets in LCC schematics (translate(), @spice_get_voltage(..) )
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2023-11-12 13:43:31 +01:00 |
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stefan schippers
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6bace90b41
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revert test changes on cmos_example.sch
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2023-11-11 00:09:05 +01:00 |
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stefan schippers
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bdd641cad3
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allow tcleval(xxxx) in % dataset specification on graph nodes
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2023-11-11 00:03:22 +01:00 |
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stefan schippers
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769c7d4663
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Add incremental_select tcl variable. It is normally set. If set show selected objects while dragging a selection rectangle. If unset show selection at end of drag operation. Fix possible endless loop whiel zooming on X axis if raw file has only one point (OP). Also if graph specifies custom plot switch to that raw file to get correct x range.
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2023-11-09 16:41:53 +01:00 |
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stefan schippers
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1d59571e52
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revert poweramp.sch changes for testing
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2023-11-07 15:02:04 +01:00 |
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stefan schippers
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366fa86d57
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do not sel tctc::*_simulation_id var if no process was started due to errors /missing command
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2023-11-07 12:44:56 +01:00 |
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stefan schippers
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0b93634fee
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Better Simulation->Graphs-> Load raw file (ask filename)
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2023-11-03 23:37:09 +01:00 |
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stefan schippers
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391a744302
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xschem setprop command: redraw all viewport if show_pin_net_names is enabled
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2023-10-29 22:22:05 +01:00 |
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stefan schippers
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8c10ecb8b7
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schematic example updates
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2023-10-24 10:29:39 +02:00 |
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stefan schippers
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4beb2d08a6
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update example schematics
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2023-10-24 00:07:36 +02:00 |
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stefan schippers
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a65cd534b7
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update circuit examples
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2023-10-23 18:41:13 +02:00 |
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stefan schippers
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8f3fedab1f
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fix a bug when closing with ctrl-q (ie from callback(), calling proc quit_xschem) and there are multiple windows, some with changed data (switch_tab() was skipped due to xctx->semaphore). Process status dialog window will not be updated if vertical slider is not positioned to bottom
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2023-10-22 02:53:03 +02:00 |
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stefan schippers
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52572a6ca4
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update cmos_example.sch
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2023-10-17 18:16:48 +02:00 |
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stefan schippers
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306c5d0d15
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fix two small memory leaks, doc updates (xschem raw command) Raw.filename renamed to Raw.rawfile
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2023-10-17 16:08:27 +02:00 |
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stefan schippers
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b165720bc8
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allow loading more and different analyses from the same raw file. Implied tcleval() in rawfile given in graphdialog, transform multiple saved OP sims into a dc sweep.
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2023-10-17 14:00:43 +02:00 |
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stefan schippers
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745e3fc5f4
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update cmos_example.sch
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2023-10-17 00:56:49 +02:00 |
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stefan schippers
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8cfd51d8f9
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add the ability to load multiple raw files with different analyses in a single schematic ( extra_rawfile() )
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2023-10-17 00:42:31 +02:00 |
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stefan schippers
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63bc486391
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update test schematic with new dataset node plotting functions
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2023-10-14 00:19:38 +02:00 |
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stefan schippers
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617e6b3b8d
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update live backannotation if "a" and "b" cursors are swapped, syntax node%n is now allowed to plot only dataset "n" of the node. Update html docs and example autozero_comp circuit
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2023-10-13 15:51:51 +02:00 |
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stefan schippers
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94bccc08d9
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do not duplicate empty strings as NULLs in hash tables
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2023-10-09 12:49:11 +02:00 |
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stefan schippers
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9fee9610ab
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vsource.sym and ammeter.sym: add "savecurrent=1|0|true|false" attribute do decide if a .save I(...) is to be printed in netlist. default is 1 for ammeter.sym and 0 for vsource.sym. Add "deltax deltay rot flip" optional parameters for xschem "copy_objects" command to make copy operation scriptable (lot more efficient than using clipboard)
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2023-10-02 12:11:05 +02:00 |
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stefan schippers
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810b814211
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added some comments in code / schematics
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2023-06-18 23:44:52 +02:00 |
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stefan schippers
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d56e3939d5
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updated xschem_library/examples/test_backannotated_subckt.sch; fix a potential segfault in proc fix_symbol
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2023-06-08 01:08:05 +02:00 |
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stefan schippers
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4d98cc7b41
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moved test_generators under generators/
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2023-06-07 09:51:11 +02:00 |
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stefan schippers
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3a42cfa64c
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added test_generators.sch example
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2023-06-07 09:38:11 +02:00 |
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stefan schippers
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245993f034
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added attributes spice_ignore=short, verilog_ignore=short, .... that will transform the instance into a short in the current netlisting mode, shorting all pins to the same net. Works similarly as lvs_ignore=short, but does not need lvs_ignore global setting
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2023-06-07 03:41:49 +02:00 |
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stefan schippers
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394db224d1
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added global tcl variable `lvs_ignore` that can be used to enable instance or symbol attributes `lvs_ignore=open` or `lvs_ignore=short` while netlisting, added `test_lvs_ignore.sch` example
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2023-06-06 15:22:45 +02:00 |
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stefan schippers
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ff216e8187
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function reset_flags() set flags on symbols and instances; call reset_flags before rebuilding connectivity to update cached values; add short.sym component that can be used to short two nets together (and remove the short using *_ignore=true); instcheck(): do not proces instances that have *_ignore=true set.
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2023-06-06 08:42:43 +02:00 |
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Stefan Schippers
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f5c592c889
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xschem resolved_net command: add [net] parameter; instcheck(): use inst[].lab instead of get_tok_value(inst[].prop_ptr, "lab",0)
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2023-06-01 18:00:47 +02:00 |
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Stefan Schippers
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f3f12da486
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updated test_extracted_netlist.sch example
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2023-06-01 16:02:40 +02:00 |
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stefan schippers
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60a6a76ac2
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update test_extracted_netlist.sch
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2023-06-01 11:36:47 +02:00 |
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stefan schippers
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39f2747149
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fix some errors found by Joanne in test_bus_tap.sch
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2023-05-31 00:14:22 +02:00 |
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stefan schippers
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5085301cd7
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add net_name=true in bus_tap.sym (so avoid setting it on instancs), add documentation for bus taps
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2023-05-30 11:03:07 +02:00 |
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stefan schippers
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4a06176f0d
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comments, more test_bus_tap examples
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2023-05-29 16:48:13 +02:00 |
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stefan schippers
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487b1eb202
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more flexible bus_tap syntax
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2023-05-29 09:17:06 +02:00 |
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stefan schippers
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6bbc60f8fb
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add more ".." bus notations: XX[4,2,8..1..3,12,23] and others. bus_tap.sym: if no "[n]" pattern is given assume it is the complete name of the slice (does not need bus basename)
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2023-05-28 15:30:40 +02:00 |
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stefan schippers
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5043b14921
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fix uninitialized wave_color due to regression after rainbow wave color enablement in double dc sweeps; more bus_tap.sym usage in examples; make bus_tap.sym work correctly for all netlist formats
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2023-05-27 23:36:10 +02:00 |
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Stefan Schippers
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cff9f7d169
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some bug fixes in resolved_net hashing, use some @#n:resolved_net labels in examples
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2023-05-27 21:48:21 +02:00 |
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stefan schippers
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c3d7780150
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updated test_bus_tap.sch with more bus tapping cases
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2023-05-25 09:51:17 +02:00 |
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Stefan Schippers
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ba402e65c0
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remove unneeded variable in create_new_tab()
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2023-05-24 18:20:18 +02:00 |
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stefan schippers
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d3b99d3a76
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update n and p jfets, added pjfet simulation
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2023-05-24 10:02:26 +02:00 |
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stefan schippers
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608a144dd1
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fix tcl procedures using find_file to find a component: use find_file_first (return 1st match) , since find_file may return multiple matches; add njfet.sym, pjfet.sym and test_jfet.sch
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2023-05-24 08:43:05 +02:00 |
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Stefan Schippers
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1774ff4e3a
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allow @#n:pin_attr or @#pin_name:pin_attr in spice format string (print_spice_element), in addition to @#n (convergence to translate()
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2023-05-22 21:50:14 +02:00 |
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stefan schippers
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ade1aaf858
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(3) update examples/test_bus_tap.sch
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2023-05-22 08:51:23 +02:00 |
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stefan schippers
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6de12e5a0f
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(2) update examples/test_bus_tap.sch
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2023-05-22 08:09:42 +02:00 |
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stefan schippers
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8f63560737
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examples/test_bus_tap.sch: auto set show_pin_net_names=1
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2023-05-22 08:05:37 +02:00 |
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stefan schippers
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9715cf4a5c
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update examples/test_bus_tap.sch
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2023-05-22 07:45:23 +02:00 |
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stefan schippers
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b68dd8c099
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when a bus label is edited correctly propagate list of instances to be redrawn if show net names on components is enabled (ie: propagate thru bus taps)
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2023-05-22 07:28:12 +02:00 |