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update live backannotation if "a" and "b" cursors are swapped, syntax node%n is now allowed to plot only dataset "n" of the node. Update html docs and example autozero_comp circuit

This commit is contained in:
stefan schippers 2023-10-13 15:51:51 +02:00
parent 6ad282a3df
commit 617e6b3b8d
8 changed files with 391 additions and 314 deletions
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13
doc/xschem_man/graphs.html
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@ -196,7 +196,18 @@ p{padding: 15px 30px 10px;}
<li><kbd>integ()</kbd> Integration</li>
<li><kbd>dup()</kbd> Duplicate last element on stack</li>
</ul>
<h3>Display a specific dataset for a node</h3>
<p>
The following syntax:
<kbd>node%n</kbd> where <kbd>node</kbd> is a saved node or a bus or an expression
and <kbd>n</kbd> is an integer number will plot only the indicated dataset number.
Dataset numbers start from 0.
This syntax is accepted for single nodes, bus names and expressions:<br><br>
<kbd>"DATA_4; en cal saout % 4"</kbd><br>
<kbd>saout%3</kbd><br>
<kbd>"Power dataset 6; I(VVCC) VCC * %6"</kbd><br><br>
<img src="graphs17.png"><br>
</p>
<!-- end of slide -->
<div class="filler"></div>
</div>

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8
src/callback.c
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@ -379,7 +379,6 @@ static int waves_callback(int event, int mx, int my, KeySym key, int button, int
if(there_are_floaters()) set_modify(-2); /* update floater caches to reflect actual backannotation */
redraw_all_at_end = 1;
}
else need_redraw = 1;
}
gr->master_gx1 = gr->gx1;
gr->master_gx2 = gr->gx2;
@ -453,7 +452,12 @@ static int waves_callback(int event, int mx, int my, KeySym key, int button, int
tmp = xctx->graph_cursor2_x;
xctx->graph_cursor2_x = xctx->graph_cursor1_x;
xctx->graph_cursor1_x = tmp;
need_all_redraw = 1;
if(tclgetboolvar("live_cursor2_backannotate")) {
backannotate_at_cursor_b_pos(r, gr);
if(there_are_floaters()) set_modify(-2); /* update floater caches to reflect actual backannotation */
redraw_all_at_end = 1;
}
else need_all_redraw = 1;
}
/* measurement tooltip */
else if((key == 'm') ) {

44
src/draw.c
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@ -3131,6 +3131,8 @@ void draw_graph(int i, const int flags, Graph_ctx *gr, void *ct)
char *express = NULL;
xRect *r = &xctx->rect[GRIDLAYER][i];
Raw *raw = xctx->raw;
int node_dataset = -1; /* dataset specified as %<n> after node/bus/expression name */
char *ntok_copy = NULL; /* copy of ntok without %<n> */
if(xctx->only_probes) return;
if(RECT_OUTSIDE( gr->sx1, gr->sy1, gr->sx2, gr->sy2,
@ -3162,15 +3164,25 @@ void draw_graph(int i, const int flags, Graph_ctx *gr, void *ct)
n_nodes = count_items(node, " \t\n", "\"");
/* process each node given in "node" attribute, get also associated color/sweep var if any*/
while( (ntok = my_strtok_r(nptr, "\n\t ", "\"", 4, &saven)) ) {
if(strstr(ntok, ",")) {
/* also trim spaces */
my_strdup2(_ALLOC_ID_, &bus_msb, trim_chars(find_nth(ntok, ";,", "\"", 0, 2), " "));
/* if %<n> is specified after node name, <n> is the dataset number to plot in graph */
char *nd = find_nth(ntok, "%", "\"", 0, 2);
if(nd[0]) {
node_dataset = atoi(nd);
my_strdup(_ALLOC_ID_, &ntok_copy, find_nth(ntok, "%", "\"", 0, 1));
} else {
node_dataset = -1;
my_strdup(_ALLOC_ID_, &ntok_copy, ntok);
}
dbg(1, "ntok=|%s|, bus_msb=|%s|\n", ntok, bus_msb ? bus_msb : "NULL");
dbg(1, "ntok=|%s|\nntok_copy=|%s|\nnode_dataset=%d\n", ntok, ntok_copy, node_dataset);
if(strstr(ntok_copy, ",")) {
/* also trim spaces */
my_strdup2(_ALLOC_ID_, &bus_msb, trim_chars(find_nth(ntok_copy, ";,", "\"", 0, 2), " "));
}
dbg(1, "ntok_copy=|%s|, bus_msb=|%s|\n", ntok_copy, bus_msb ? bus_msb : "NULL");
ctok = my_strtok_r(cptr, " ", "", 0, &savec);
stok = my_strtok_r(sptr, "\t\n ", "\"", 0, &saves);
nptr = cptr = sptr = NULL;
dbg(1, "ntok=%s ctok=%s\n", ntok, ctok? ctok: "NULL");
dbg(1, "ntok_copy=%s ctok=%s\n", ntok_copy, ctok? ctok: "NULL");
if(ctok && ctok[0]) wc = atoi(ctok);
if(wc < 0) wc = 4;
if(wc >= cadlayers) wc = cadlayers - 1;
@ -3181,20 +3193,21 @@ void draw_graph(int i, const int flags, Graph_ctx *gr, void *ct)
}
}
draw_graph_variables(wcnt, wc, n_nodes, sweep_idx, flags, ntok, stok, bus_msb, gr);
/* if ntok following possible 'alias;' definition contains spaces --> custom data plot */
/* if ntok_copy following possible 'alias;' definition contains spaces --> custom data plot */
idx = -1;
expression = 0;
if(raw && raw->values && !bus_msb) {
if(strstr(ntok, ";")) {
my_strdup2(_ALLOC_ID_, &express, find_nth(ntok, ";", "\"", 0, 2));
if(strstr(ntok_copy, ";")) {
my_strdup2(_ALLOC_ID_, &express, find_nth(ntok_copy, ";", "\"", 0, 2));
} else {
my_strdup2(_ALLOC_ID_, &express, ntok);
my_strdup2(_ALLOC_ID_, &express, ntok_copy);
}
dbg(1, "express=|%s|\n", express);
if(strpbrk(express, " \n\t")) {
expression = 1;
}
}
/* quickly find index number of ntok variable to be plotted */
/* quickly find index number of ntok_copy variable to be plotted */
if( expression || (idx = get_raw_index(bus_msb ? bus_msb : express)) != -1 ) {
int p, dset, ofs;
int poly_npoints;
@ -3207,13 +3220,13 @@ void draw_graph(int i, const int flags, Graph_ctx *gr, void *ct)
SPICE_DATA **idx_arr = NULL;
int sweepvar_wrap = 0; /* incremented on new dataset or sweep variable wrap */
XPoint *point = NULL;
int dataset = gr->dataset;
int dataset = node_dataset >=0 ? node_dataset : gr->dataset;
int digital = gr->digital;
ofs = 0;
start = (gr->gx1 <= gr->gx2) ? gr->gx1 : gr->gx2;
end = (gr->gx1 <= gr->gx2) ? gr->gx2 : gr->gx1;
if(bus_msb) {
idx_arr = get_bus_idx_array(ntok, &n_bits); /* idx_arr allocated by function, must free! */
idx_arr = get_bus_idx_array(ntok_copy, &n_bits); /* idx_arr allocated by function, must free! */
}
bbox(START, 0.0, 0.0, 0.0, 0.0);
bbox(ADD,gr->x1, gr->y1, gr->x2, gr->y2);
@ -3245,7 +3258,7 @@ void draw_graph(int i, const int flags, Graph_ctx *gr, void *ct)
else wave_color = wc;
if(bus_msb) {
if(digital) {
draw_graph_bus_points(ntok, n_bits, idx_arr, first, last, wave_color,
draw_graph_bus_points(ntok_copy, n_bits, idx_arr, first, last, wave_color,
sweep_idx, wcnt, n_nodes, gr, ct);
}
} else {
@ -3287,7 +3300,7 @@ void draw_graph(int i, const int flags, Graph_ctx *gr, void *ct)
else wave_color = wc;
if(bus_msb) {
if(digital) {
draw_graph_bus_points(ntok, n_bits, idx_arr, first, last, wave_color,
draw_graph_bus_points(ntok_copy, n_bits, idx_arr, first, last, wave_color,
sweep_idx, wcnt, n_nodes, gr, ct);
}
} else {
@ -3302,7 +3315,7 @@ void draw_graph(int i, const int flags, Graph_ctx *gr, void *ct)
} /* for(dset...) */
bbox(END, 0.0, 0.0, 0.0, 0.0);
if(measure_p != -1) show_node_measures(measure_p, measure_x, measure_prev_x, bus_msb, wave_color,
idx, idx_arr, n_bits, n_nodes, ntok, wcnt, gr);
idx, idx_arr, n_bits, n_nodes, ntok_copy, wcnt, gr);
my_free(_ALLOC_ID_, &point);
if(idx_arr) my_free(_ALLOC_ID_, &idx_arr);
@ -3310,6 +3323,7 @@ void draw_graph(int i, const int flags, Graph_ctx *gr, void *ct)
++wcnt;
if(bus_msb) my_free(_ALLOC_ID_, &bus_msb);
} /* while( (ntok = my_strtok_r(nptr, "\n\t ", "", 0, &saven)) ) */
if(ntok_copy) my_free(_ALLOC_ID_, &ntok_copy);
if(express) my_free(_ALLOC_ID_, &express);
my_free(_ALLOC_ID_, &node);
my_free(_ALLOC_ID_, &color);

2
src/xschem.tcl
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@ -6841,7 +6841,7 @@ set_ne graph_selected {}
set_ne graph_schname {}
set_ne graph_change_done 0 ;# used to push undo only once when editing graphs
set_ne raw_level -1 ;# hierarchy level where raw file has been loaded
set_ne graph_linewidth_mult 2.0 ;# default multiplier (w.r.t. xschem lines) for line width in graphs
set_ne graph_linewidth_mult 1.4 ;# default multiplier (w.r.t. xschem lines) for line width in graphs
# user clicked this wave
set_ne graph_sel_wave {}
# flag to force simulation stop (Esc key pressed)

3
xschem_library/examples/0_examples_top.sch
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@ -1,4 +1,4 @@
v {xschem version=3.4.4 file_version=1.2
v {xschem version=3.4.5 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@ -1495,3 +1495,4 @@ C {test_jfet.sym} 480 -620 0 0 {name=x25}
C {test_short_option.sym} 480 -580 0 0 {name=x26}
C {test_lvs_ignore.sym} 480 -540 0 0 {name=x27}
C {test_generators.sym} 480 -500 0 0 {name=x28}
C {autozero_comp.sym} 480 -460 0 0 {name=x29}

624
xschem_library/ngspice/autozero_comp.sch
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@ -1,4 +1,4 @@
v {xschem version=3.4.4 file_version=1.2
v {xschem version=3.4.5 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@ -38,48 +38,79 @@ L 4 410 -150 570 -150 {}
L 4 570 -170 570 -150 {}
L 4 570 -170 690 -170 {}
L 7 1090 -260 2520 -260 {}
B 2 300 -1060 760 -900 {flags=graph
B 2 350 -1020 810 -860 {flags=graph
y1 = 0
y2 = 0.93
divy = 5
x1=6.17604e-08
x2=4.71882e-07
x1=9.31247e-08
x2=4.30871e-07
divx=5
subdivx=4
unitx=n
node="cal
saout"
color="4 5"
node="cal%0
saout
saout%70
saout%3"
color="8 14 7 12"
linewidth_mult=1.0
hilight_wave=-1
dataset=-1}
B 2 300 -1200 760 -1070 {flags=graph
B 2 350 -1160 810 -1030 {flags=graph
y1 = 0.647319
y2 = 0.652563
divy = 5
x1=6.17604e-08
x2=4.71882e-07
x1=9.31247e-08
x2=4.30871e-07
unitx=n
divx=5
subdivx=4
node="plus
minus"
node="plus%0
minus%0"
color="4 5"
dataset=-1}
B 2 300 -1300 760 -1200 {flags=graph
dataset=-1
linewidth_mult=1.0}
B 2 350 -1320 810 -1160 {flags=graph
y1 = 0
y2 = 1
y2 = 0.9
divy = 5
x1=6.17604e-08
x2=4.71882e-07
x1=9.31247e-08
x2=4.30871e-07
unitx=n
divx=5
subdivx=4
node="en
cal"
color="4 4"
cal
\\"SAOUT#3; vss,saout%3\\"
--slow--
\\"SAOUT#15; vss,saout%15\\"
--failure--
\\"SAOUT#70; vss,saout%70\\""
color="4 4 4 8 8 7 7"
dataset=-1
digital=1
ypos1=0.0602914
ypos2=0.292255}
ypos1=0.0825406
ypos2=0.767045
ylabmag=1.2
linewidth_mult=1.0
subdivy=0}
B 2 350 -1450 810 -1330 {flags=graph
y1 = -8.54414e-05
y2 = 2.7198e-05
divy = 5
x1=9.31247e-08
x2=4.30871e-07
divx=5
subdivx=4
unitx=n
dataset=-1
color="4 7"
node="\\"power dset 97 ; i(vvcc) vcc * % 23\\"
\\"power dset 70 ; i(vvcc) vcc * % 70\\""
subdivy=4
linewidth_mult=1.0}
T {CAL} 140 -180 0 1 0.4 0.4 {}
T {EN} 140 -130 0 1 0.4 0.4 {}
T {CALIBRATION
@ -94,147 +125,163 @@ Output on SAOUT
Gaussian Threshold variation (via delvto parameter) is added to all MOS transistors.} 1110 -240 0 0 0.6 0.6 {}
T {.param ABSVAR=0.05
delvto='agauss(0,ABSVAR,3)'} 1390 -120 0 0 0.6 0.6 {layer=8}
T {Select one or more graphs (and no other objects)
and use arrow keys to zoom / pan waveforms} 310 -1380 0 0 0.3 0.3 {}
N 120 -470 120 -450 {lab=TEMPERAT}
N 160 -1180 190 -1180 {lab=VSS}
N 160 -1150 160 -1130 {lab=VSS}
N 160 -1230 160 -1210 {lab=VSSI}
N 1120 -1100 1150 -1100 {lab=VSS}
N 1120 -1330 1150 -1330 {lab=VCC}
N 1090 -1400 1120 -1400 {lab=VCC}
N 1120 -1400 1120 -1360 {lab=VCC}
N 1090 -970 1120 -970 {lab=VSSI}
N 1120 -1010 1120 -970 {lab=VSSI}
N 980 -1100 1080 -1100 {lab=ZERO0}
N 980 -1260 980 -1100 {lab=ZERO0}
N 900 -1260 980 -1260 {lab=ZERO0}
N 790 -1260 820 -1260 {lab=OUTDIFF}
N 790 -1440 790 -1260 {lab=OUTDIFF}
N 790 -1440 1220 -1440 {lab=OUTDIFF}
N 1120 -1260 1220 -1260 {lab=OUTDIFF}
N 1610 -1100 1640 -1100 {lab=VSS}
N 1610 -1330 1640 -1330 {lab=VCC}
N 1580 -1400 1610 -1400 {lab=VCC}
N 1610 -1400 1610 -1360 {lab=VCC}
N 1580 -970 1610 -970 {lab=VSSI}
N 1610 -1010 1610 -970 {lab=VSSI}
N 1470 -1100 1570 -1100 {lab=ZERO1}
N 1470 -1260 1470 -1100 {lab=ZERO1}
N 1390 -1260 1470 -1260 {lab=ZERO1}
N 1280 -1260 1310 -1260 {lab=SAOUTF}
N 1280 -1440 1280 -1260 {lab=SAOUTF}
N 1280 -1440 1710 -1440 {lab=SAOUTF}
N 1610 -1260 1710 -1260 {lab=SAOUTF}
N 1220 -1440 1220 -1260 {lab=OUTDIFF}
N 1120 -1300 1120 -1260 {lab=OUTDIFF}
N 980 -1330 980 -1260 {lab=ZERO0}
N 1610 -1300 1610 -1260 {lab=SAOUTF}
N 1470 -1330 1470 -1260 {lab=ZERO1}
N 1710 -1440 1710 -1260 {lab=SAOUTF}
N 890 -640 920 -640 {lab=VSS}
N 1060 -640 1090 -640 {lab=VSS}
N 1090 -800 1120 -800 {lab=VCC}
N 860 -800 890 -800 {lab=VCC}
N 930 -800 1050 -800 {lab=GN}
N 930 -800 930 -770 {lab=GN}
N 890 -770 930 -770 {lab=GN}
N 890 -770 890 -670 {lab=GN}
N 1090 -710 1090 -670 {lab=OUTDIFF}
N 890 -860 890 -830 {lab=VCC}
N 990 -860 1090 -860 {lab=VCC}
N 1090 -860 1090 -830 {lab=VCC}
N 1090 -610 1090 -590 {lab=SN}
N 990 -590 1090 -590 {lab=SN}
N 890 -610 890 -590 {lab=SN}
N 990 -510 1020 -510 {lab=VSS}
N 990 -590 990 -540 {lab=SN}
N 990 -880 990 -860 {lab=VCC}
N 960 -380 990 -380 {lab=VSSI}
N 990 -420 990 -380 {lab=VSSI}
N 1470 -510 1500 -510 {lab=VSS}
N 1470 -800 1500 -800 {lab=VCC}
N 1440 -870 1470 -870 {lab=VCC}
N 1470 -870 1470 -830 {lab=VCC}
N 1440 -380 1470 -380 {lab=VSSI}
N 1470 -420 1470 -380 {lab=VSSI}
N 1470 -710 1470 -540 {lab=SAOUTF}
N 1220 -710 1360 -710 {lab=OUTDIFF}
N 890 -860 990 -860 {lab=VCC}
N 890 -590 990 -590 {lab=SN}
N 1120 -1260 1120 -1130 {lab=OUTDIFF}
N 1610 -1260 1610 -1130 {lab=SAOUTF}
N 1360 -710 1360 -510 {lab=OUTDIFF}
N 1220 -1260 1220 -710 {lab=OUTDIFF}
N 1710 -1260 1710 -710 {lab=SAOUTF}
N 1710 -710 1850 -710 {lab=SAOUTF}
N 1090 -710 1220 -710 {lab=OUTDIFF}
N 1090 -770 1090 -710 {lab=OUTDIFF}
N 1360 -800 1360 -710 {lab=OUTDIFF}
N 1470 -1330 1570 -1330 {lab=ZERO1}
N 980 -1330 1080 -1330 {lab=ZERO0}
N 1360 -800 1430 -800 {lab=OUTDIFF}
N 1360 -510 1430 -510 {lab=OUTDIFF}
N 1960 -510 1990 -510 {lab=VSS}
N 1960 -800 1990 -800 {lab=VCC}
N 1930 -870 1960 -870 {lab=VCC}
N 1960 -870 1960 -830 {lab=VCC}
N 1930 -380 1960 -380 {lab=VSSI}
N 1960 -420 1960 -380 {lab=VSSI}
N 1960 -710 1960 -540 {lab=SAOUT}
N 1850 -710 1850 -510 {lab=SAOUTF}
N 2100 -1100 2130 -1100 {lab=VSS}
N 2100 -1330 2130 -1330 {lab=VCC}
N 2070 -1400 2100 -1400 {lab=VCC}
N 2100 -1400 2100 -1360 {lab=VCC}
N 2070 -970 2100 -970 {lab=VSSI}
N 2100 -1010 2100 -970 {lab=VSSI}
N 1960 -1100 2060 -1100 {lab=ZERO2}
N 1960 -1260 1960 -1100 {lab=ZERO2}
N 1880 -1260 1960 -1260 {lab=ZERO2}
N 1770 -1260 1800 -1260 {lab=SAOUT}
N 1770 -1440 1770 -1260 {lab=SAOUT}
N 1770 -1440 2290 -1440 {lab=SAOUT}
N 2100 -1260 2290 -1260 {lab=SAOUT}
N 2100 -1300 2100 -1260 {lab=SAOUT}
N 1960 -1330 1960 -1260 {lab=ZERO2}
N 2290 -1440 2290 -1260 {lab=SAOUT}
N 2100 -1260 2100 -1130 {lab=SAOUT}
N 2290 -1260 2290 -710 {lab=SAOUT}
N 1960 -1330 2060 -1330 {lab=ZERO2}
N 1850 -800 1920 -800 {lab=SAOUTF}
N 1850 -510 1920 -510 {lab=SAOUTF}
N 1470 -710 1710 -710 {lab=SAOUTF}
N 1960 -710 2290 -710 {lab=SAOUT}
N 1850 -800 1850 -710 {lab=SAOUTF}
N 1960 -770 1960 -710 {lab=SAOUT}
N 1470 -770 1470 -710 {lab=SAOUTF}
N 2180 -810 2210 -810 {lab=VCC}
N 2150 -880 2180 -880 {lab=VCC}
N 2180 -880 2180 -840 {lab=VCC}
N 2180 -780 2180 -710 {lab=SAOUT}
N 590 -680 620 -680 {lab=VCC}
N 420 -740 420 -710 {lab=SP}
N 520 -740 620 -740 {lab=SP}
N 620 -740 620 -710 {lab=SP}
N 420 -740 520 -740 {lab=SP}
N 420 -680 450 -680 {lab=VCC}
N 390 -550 420 -550 {lab=VSS}
N 620 -550 650 -550 {lab=VSS}
N 460 -550 580 -550 {lab=GP}
N 460 -580 460 -550 {lab=GP}
N 420 -580 460 -580 {lab=GP}
N 420 -650 420 -580 {lab=GP}
N 620 -650 620 -580 {lab=OUTDIFF}
N 620 -520 620 -500 {lab=VSSI}
N 420 -500 620 -500 {lab=VSSI}
N 420 -520 420 -500 {lab=VSSI}
N 490 -460 520 -460 {lab=VSSI}
N 520 -500 520 -460 {lab=VSSI}
N 530 -810 560 -810 {lab=VCC}
N 530 -780 530 -740 {lab=SP}
N 530 -860 530 -840 {lab=VCC}
N 620 -610 680 -610 {lab=OUTDIFF}
N 360 -530 390 -530 {lab=VSS}
N 360 -500 360 -480 {lab=VSS}
N 360 -580 360 -560 {lab=VSSI}
N 1200 -1070 1230 -1070 {lab=VSS}
N 1200 -1230 1230 -1230 {lab=VCC}
N 1170 -1300 1200 -1300 {lab=VCC}
N 1200 -1300 1200 -1260 {lab=VCC}
N 1170 -940 1200 -940 {lab=VSSI}
N 1200 -980 1200 -940 {lab=VSSI}
N 1060 -1070 1160 -1070 {lab=ZERO0}
N 1060 -1160 1060 -1070 {lab=ZERO0}
N 980 -1160 1060 -1160 {lab=ZERO0}
N 870 -1160 900 -1160 {lab=#net1}
N 870 -1340 870 -1160 {lab=#net1}
N 870 -1340 1300 -1340 {lab=#net1}
N 1200 -1160 1300 -1160 {lab=#net1}
N 1690 -1070 1720 -1070 {lab=VSS}
N 1690 -1230 1720 -1230 {lab=VCC}
N 1660 -1300 1690 -1300 {lab=VCC}
N 1690 -1300 1690 -1260 {lab=VCC}
N 1660 -940 1690 -940 {lab=VSSI}
N 1690 -980 1690 -940 {lab=VSSI}
N 1550 -1070 1650 -1070 {lab=ZERO1}
N 1550 -1160 1550 -1070 {lab=ZERO1}
N 1470 -1160 1550 -1160 {lab=ZERO1}
N 1360 -1160 1390 -1160 {lab=#net2}
N 1360 -1340 1360 -1160 {lab=#net2}
N 1360 -1340 1790 -1340 {lab=#net2}
N 1690 -1160 1790 -1160 {lab=#net2}
N 1300 -1340 1300 -1160 {lab=#net1}
N 1200 -1200 1200 -1160 {lab=#net1}
N 1060 -1230 1060 -1160 {lab=ZERO0}
N 1690 -1200 1690 -1160 {lab=#net2}
N 1550 -1230 1550 -1160 {lab=ZERO1}
N 1790 -1340 1790 -1160 {lab=#net2}
N 970 -640 1000 -640 {lab=VSS}
N 1140 -640 1170 -640 {lab=VSS}
N 1170 -800 1200 -800 {lab=VCC}
N 940 -800 970 -800 {lab=VCC}
N 1010 -800 1130 -800 {lab=GN}
N 1010 -800 1010 -770 {lab=GN}
N 970 -770 1010 -770 {lab=GN}
N 970 -770 970 -670 {lab=GN}
N 1170 -710 1170 -670 {lab=OUTDIFF}
N 970 -860 970 -830 {lab=VCC}
N 1070 -860 1170 -860 {lab=VCC}
N 1170 -860 1170 -830 {lab=VCC}
N 1170 -610 1170 -590 {lab=SN}
N 1070 -590 1170 -590 {lab=SN}
N 970 -610 970 -590 {lab=SN}
N 1070 -510 1100 -510 {lab=VSS}
N 1070 -590 1070 -540 {lab=SN}
N 1070 -880 1070 -860 {lab=VCC}
N 1040 -380 1070 -380 {lab=VSSI}
N 1070 -420 1070 -380 {lab=VSSI}
N 1550 -510 1580 -510 {lab=VSS}
N 1550 -800 1580 -800 {lab=VCC}
N 1520 -870 1550 -870 {lab=VCC}
N 1550 -870 1550 -830 {lab=VCC}
N 1520 -380 1550 -380 {lab=VSSI}
N 1550 -420 1550 -380 {lab=VSSI}
N 1550 -710 1550 -540 {lab=SAOUTF}
N 1300 -710 1440 -710 {lab=OUTDIFF}
N 970 -860 1070 -860 {lab=VCC}
N 970 -590 1070 -590 {lab=SN}
N 1200 -1160 1200 -1100 {lab=#net1}
N 1690 -1160 1690 -1100 {lab=#net2}
N 1440 -710 1440 -510 {lab=OUTDIFF}
N 1300 -840 1300 -710 {lab=OUTDIFF}
N 1790 -840 1790 -710 {lab=SAOUTF}
N 1790 -710 1930 -710 {lab=SAOUTF}
N 1170 -710 1300 -710 {lab=OUTDIFF}
N 1170 -770 1170 -710 {lab=OUTDIFF}
N 1440 -800 1440 -710 {lab=OUTDIFF}
N 1550 -1230 1650 -1230 {lab=ZERO1}
N 1060 -1230 1160 -1230 {lab=ZERO0}
N 1440 -800 1510 -800 {lab=OUTDIFF}
N 1440 -510 1510 -510 {lab=OUTDIFF}
N 2040 -510 2070 -510 {lab=VSS}
N 2040 -800 2070 -800 {lab=VCC}
N 2010 -870 2040 -870 {lab=VCC}
N 2040 -870 2040 -830 {lab=VCC}
N 2010 -380 2040 -380 {lab=VSSI}
N 2040 -420 2040 -380 {lab=VSSI}
N 2040 -710 2040 -540 {lab=SAOUT}
N 1930 -710 1930 -510 {lab=SAOUTF}
N 2180 -1070 2210 -1070 {lab=VSS}
N 2180 -1230 2210 -1230 {lab=VCC}
N 2150 -1300 2180 -1300 {lab=VCC}
N 2180 -1300 2180 -1260 {lab=VCC}
N 2150 -940 2180 -940 {lab=VSSI}
N 2180 -980 2180 -940 {lab=VSSI}
N 2040 -1070 2140 -1070 {lab=ZERO2}
N 2040 -1160 2040 -1070 {lab=ZERO2}
N 1960 -1160 2040 -1160 {lab=ZERO2}
N 1850 -1160 1880 -1160 {lab=#net3}
N 1850 -1340 1850 -1160 {lab=#net3}
N 1850 -1340 2370 -1340 {lab=#net3}
N 2180 -1160 2370 -1160 {lab=#net3}
N 2180 -1200 2180 -1160 {lab=#net3}
N 2040 -1230 2040 -1160 {lab=ZERO2}
N 2370 -1340 2370 -1160 {lab=#net3}
N 2180 -1160 2180 -1100 {lab=#net3}
N 2370 -840 2370 -710 {lab=SAOUT}
N 2040 -1230 2140 -1230 {lab=ZERO2}
N 1930 -800 2000 -800 {lab=SAOUTF}
N 1930 -510 2000 -510 {lab=SAOUTF}
N 1550 -710 1790 -710 {lab=SAOUTF}
N 2040 -710 2370 -710 {lab=SAOUT}
N 1930 -800 1930 -710 {lab=SAOUTF}
N 2040 -770 2040 -710 {lab=SAOUT}
N 1550 -770 1550 -710 {lab=SAOUTF}
N 2260 -810 2290 -810 {lab=VCC}
N 2230 -880 2260 -880 {lab=VCC}
N 2260 -880 2260 -840 {lab=VCC}
N 2260 -780 2260 -710 {lab=SAOUT}
N 720 -590 750 -590 {lab=VCC}
N 550 -650 550 -620 {lab=SP}
N 650 -650 750 -650 {lab=SP}
N 750 -650 750 -620 {lab=SP}
N 550 -650 650 -650 {lab=SP}
N 550 -590 580 -590 {lab=VCC}
N 520 -460 550 -460 {lab=VSS}
N 750 -460 780 -460 {lab=VSS}
N 590 -460 710 -460 {lab=GP}
N 590 -510 590 -460 {lab=GP}
N 550 -510 590 -510 {lab=GP}
N 550 -560 550 -510 {lab=GP}
N 750 -560 750 -490 {lab=OUTDIFF}
N 750 -430 750 -410 {lab=VSSI}
N 550 -410 750 -410 {lab=VSSI}
N 550 -430 550 -410 {lab=VSSI}
N 620 -370 650 -370 {lab=VSSI}
N 650 -410 650 -370 {lab=VSSI}
N 660 -780 690 -780 {lab=VCC}
N 660 -680 660 -650 {lab=SP}
N 660 -830 660 -810 {lab=VCC}
N 750 -520 810 -520 {lab=OUTDIFF}
N 660 -750 660 -740 {lab=#net4}
N 550 -510 550 -490 {
lab=GP}
N 490 -590 510 -590 {
lab=MINUS}
N 790 -590 810 -590 {
lab=PLUS}
N 910 -640 930 -640 {
lab=MINUS}
N 1210 -640 1230 -640 {
lab=PLUS}
N 1300 -1160 1300 -900 {lab=#net1}
N 1790 -1160 1790 -900 {lab=#net2}
N 2370 -1160 2370 -900 {lab=#net3}
N 570 -780 620 -780 {
lab=GP}
N 990 -510 1030 -510 {
lab=GN}
C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
C {ipin.sym} 110 -850 0 0 { name=p92 lab=CAL }
C {ipin.sym} 110 -910 0 0 { name=p93 lab=PLUS }
@ -245,19 +292,19 @@ C {ipin.sym} 110 -810 0 0 { name=p97 lab=VCC }
C {vsource_arith.sym} 120 -420 0 0 {name=E5 VOL=temper MAX=200 MIN=-200}
C {lab_pin.sym} 120 -470 0 1 {name=p113 lab=TEMPERAT}
C {lab_pin.sym} 120 -390 0 0 {name=p114 lab=VSS}
C {opin.sym} 130 -900 0 0 { name=p116 lab=SAOUT }
C {opin.sym} 230 -900 0 0 { name=p116 lab=SAOUT }
C {lab_pin.sym} 200 -570 0 1 {name=p126 lab=CALB}
C {lab_pin.sym} 120 -570 0 0 {name=l50 lab=CAL}
C {code.sym} 840 -190 0 0 {name=STIMULI
only_toplevel=true
xxplace=end
value="* .option SCALE=1e-6
.option method=gear $$ seed=12
.option method=gear
.param VCC=0.9
.param VDL='VCC/2+0.2'
.param ABSVAR=0.05
.temp 25
.param RNDVAL = 'agauss(0, 10, 1)'
** to generate following file:
** copy .../share/doc/xschem/ngspice/stimuli.autozero_comp to simulation directory
** then do 'Simulation->Utile Stimuli Editor (GUI)' and press 'Translate'
@ -272,16 +319,18 @@ value="* .option SCALE=1e-6
* .tran 0.1n 900n uic
.control
setseed 17
reset
echo Seed=$rndseed
let run=1
dowhile run <= 10
dowhile run <= 100
if run > 1
reset
set appendwrite
reset
end
* save saout cal i(vvcc) en plus minus saoutf outdiff
save all
tran 0.1n 900n uic
tran 0.3n 900n uic
write autozero_comp.raw
let run = run + 1
end
@ -297,146 +346,133 @@ C {inv-2.sym} 160 -700 0 0 {name=x5 m=1
+ VCCPIN=VCC VCCBPIN=VCC VSSPIN=VSS VSSBPIN=VSS}
C {lab_pin.sym} 120 -700 0 0 {name=p15 lab=CALB}
C {lab_pin.sym} 200 -700 0 1 {name=l4 lab=CALBB}
C {lab_pin.sym} 190 -1180 0 1 {name=p283 lab=VSS}
C {lab_pin.sym} 120 -1180 0 0 {name=l56 lab=EN}
C {lab_pin.sym} 160 -1130 0 0 {name=p284 lab=VSS}
C {lab_pin.sym} 160 -1230 0 0 {name=p199 lab=VSSI}
C {nmos4-v.sym} 140 -1180 0 0 {name=M67 verilog_gate=nmos del=50,50,50 model=nmos w=5u l=0.13u extra="delvto='agauss(0,ABSVAR,3)'"}
C {parax_cap.sym} 160 -1120 0 0 {name=c38 value=2p}
C {passgate.sym} 860 -1260 0 1 {name=x1 m=1
C {lab_pin.sym} 390 -530 0 1 {name=p283 lab=VSS}
C {lab_pin.sym} 320 -530 0 0 {name=l56 lab=EN}
C {lab_pin.sym} 360 -480 0 0 {name=p284 lab=VSS}
C {lab_pin.sym} 360 -580 0 0 {name=p199 lab=VSSI}
C {nmos4-v.sym} 340 -530 0 0 {name=M67 verilog_gate=nmos del=50,50,50 model=nmos w=5u l=0.13u extra="delvto='agauss(0,ABSVAR,3)'"}
C {parax_cap.sym} 360 -470 0 0 {name=c38 value=2p}
C {passgate.sym} 940 -1160 0 1 {name=x1 m=1
+ wn=0.4u ln=0.13u
+ wp=0.4u lp=0.13u
+ VCCBPIN=VCC VSSBPIN=VSS extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 860 -1290 0 1 {name=l19 sig_type=std_logic lab=CALB}
C {lab_pin.sym} 860 -1230 0 1 {name=l44 sig_type=std_logic lab=CALBB}
C {nmos4-v.sym} 1100 -1100 0 0 {name=M3 verilog_gate=nmos del=50,50,50 model=nmos w=1.0u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1150 -1100 0 1 {name=p179 lab=VSS}
C {pmos4-v.sym} 1100 -1330 0 0 {name=M4 verilog_gate=pmos del=50,50,50 model=pmos w=2.0u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1150 -1330 0 1 {name=p180 lab=VCC}
C {lab_pin.sym} 1090 -1400 0 0 {name=p181 lab=VCC}
C {lab_pin.sym} 1090 -970 0 0 {name=p182 lab=VSSI}
C {passgate.sym} 1350 -1260 0 1 {name=x2 m=1
C {lab_pin.sym} 940 -1190 0 1 {name=l19 sig_type=std_logic lab=CALB}
C {lab_pin.sym} 940 -1130 0 1 {name=l44 sig_type=std_logic lab=CALBB}
C {nmos4-v.sym} 1180 -1070 0 0 {name=M3 verilog_gate=nmos del=50,50,50 model=nmos w=1.0u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1230 -1070 0 1 {name=p179 lab=VSS}
C {pmos4-v.sym} 1180 -1230 0 0 {name=M4 verilog_gate=pmos del=50,50,50 model=pmos w=2.0u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1230 -1230 0 1 {name=p180 lab=VCC}
C {lab_pin.sym} 1170 -1300 0 0 {name=p181 lab=VCC}
C {lab_pin.sym} 1170 -940 0 0 {name=p182 lab=VSSI}
C {passgate.sym} 1430 -1160 0 1 {name=x2 m=1
+ wn=0.4u ln=0.13u
+ wp=0.4u lp=0.13u
+ VCCBPIN=VCC VSSBPIN=VSS extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1350 -1290 0 1 {name=l45 sig_type=std_logic lab=CALB}
C {lab_pin.sym} 1350 -1230 0 1 {name=l46 sig_type=std_logic lab=CALBB}
C {nmos4-v.sym} 1590 -1100 0 0 {name=M7 verilog_gate=nmos del=50,50,50 model=nmos w=1.3u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1640 -1100 0 1 {name=p183 lab=VSS}
C {pmos4-v.sym} 1590 -1330 0 0 {name=M9 verilog_gate=pmos del=50,50,50 model=pmos w=2.6u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1640 -1330 0 1 {name=p184 lab=VCC}
C {lab_pin.sym} 1580 -1400 0 0 {name=p185 lab=VCC}
C {lab_pin.sym} 1580 -970 0 0 {name=p186 lab=VSSI}
C {lab_pin.sym} 1470 -1320 0 0 {name=l47 lab=ZERO1}
C {lab_pin.sym} 980 -1320 0 0 {name=l48 lab=ZERO0}
C {nmos4-v.sym} 870 -640 0 0 {name=M20 verilog_gate=nmos del=50,50,50 model=nmos w=2u l=0.4u extra="delvto='agauss(0,ABSVAR,3)'"}
C {nmos4-v.sym} 1110 -640 0 1 {name=M8 verilog_gate=nmos del=50,50,50 model=nmos w=2u l=0.4u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 920 -640 0 1 {name=p187 lab=VSS}
C {lab_pin.sym} 1060 -640 0 0 {name=p188 lab=VSS}
C {pmos4-v.sym} 1070 -800 0 0 {name=M30 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1120 -800 0 1 {name=p189 lab=VCC}
C {pmos4-v.sym} 910 -800 0 1 {name=M12 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 860 -800 0 0 {name=p190 lab=VCC}
C {nmos4-v.sym} 970 -510 0 0 {name=M32 verilog_gate=nmos del=50,50,50 model=nmos w=1u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1020 -510 0 1 {name=p191 lab=VSS}
C {lab_pin.sym} 990 -880 0 0 {name=p192 lab=VCC}
C {lab_pin.sym} 960 -380 0 0 {name=p193 lab=VSSI}
C {nmos4-v.sym} 1450 -510 0 0 {name=M17 verilog_gate=nmos del=50,50,50 model=nmos w=1u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1500 -510 0 1 {name=p194 lab=VSS}
C {pmos4-v.sym} 1450 -800 0 0 {name=M13 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1500 -800 0 1 {name=p195 lab=VCC}
C {lab_pin.sym} 1440 -870 0 0 {name=p196 lab=VCC}
C {lab_pin.sym} 1440 -380 0 0 {name=p197 lab=VSSI}
C {lab_pin.sym} 1710 -750 0 0 {name=l49 lab=SAOUTF}
C {parax_cap.sym} 1540 -700 0 0 {name=c3 value=4f}
C {lab_pin.sym} 1220 -750 0 0 {name=l51 lab=OUTDIFF}
C {lab_pin.sym} 990 -570 0 0 {name=l52 lab=SN}
C {lab_pin.sym} 930 -770 0 1 {name=l53 lab=GN}
C {parax_cap.sym} 980 -790 0 0 {name=c5 value=4f}
C {parax_cap.sym} 910 -580 0 0 {name=c30 value=2f}
C {parax_cap.sym} 1180 -700 0 0 {name=c31 value=4f}
C {lab_pin.sym} 950 -510 0 0 {name=p198 lab=GN}
C {lab_pin.sym} 1130 -640 0 1 {name=l54 lab=PLUS}
C {lab_pin.sym} 850 -640 0 0 {name=l55 lab=MINUS}
C {ammeter.sym} 990 -450 0 0 {name=v2}
C {ammeter.sym} 1470 -450 0 0 {name=v3}
C {ammeter.sym} 1610 -1040 0 0 {name=v4}
C {ammeter.sym} 1120 -1040 0 0 {name=v6}
C {nmos4-v.sym} 1940 -510 0 0 {name=M19 verilog_gate=nmos del=50,50,50 model=nmos w=1u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1990 -510 0 1 {name=p9 lab=VSS}
C {pmos4-v.sym} 1940 -800 0 0 {name=M21 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1990 -800 0 1 {name=p10 lab=VCC}
C {lab_pin.sym} 1930 -870 0 0 {name=p11 lab=VCC}
C {lab_pin.sym} 1930 -380 0 0 {name=p12 lab=VSSI}
C {parax_cap.sym} 2030 -700 0 0 {name=c1 value=4f}
C {ammeter.sym} 1960 -450 0 0 {name=v1}
C {lab_pin.sym} 2290 -710 0 1 {name=l3 lab=SAOUT}
C {passgate.sym} 1840 -1260 0 1 {name=x3 m=1
C {lab_pin.sym} 1430 -1190 0 1 {name=l45 sig_type=std_logic lab=CALB}
C {lab_pin.sym} 1430 -1130 0 1 {name=l46 sig_type=std_logic lab=CALBB}
C {nmos4-v.sym} 1670 -1070 0 0 {name=M7 verilog_gate=nmos del=50,50,50 model=nmos w=1.3u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1720 -1070 0 1 {name=p183 lab=VSS}
C {pmos4-v.sym} 1670 -1230 0 0 {name=M9 verilog_gate=pmos del=50,50,50 model=pmos w=2.6u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1720 -1230 0 1 {name=p184 lab=VCC}
C {lab_pin.sym} 1660 -1300 0 0 {name=p185 lab=VCC}
C {lab_pin.sym} 1660 -940 0 0 {name=p186 lab=VSSI}
C {lab_pin.sym} 1550 -1220 0 0 {name=l47 lab=ZERO1}
C {lab_pin.sym} 1060 -1220 0 0 {name=l48 lab=ZERO0}
C {nmos4-v.sym} 950 -640 0 0 {name=M20 verilog_gate=nmos del=50,50,50 model=nmos w=2u l=0.4u extra="delvto='agauss(0,ABSVAR,3)'"}
C {nmos4-v.sym} 1190 -640 0 1 {name=M8 verilog_gate=nmos del=50,50,50 model=nmos w=2u l=0.4u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1000 -640 0 1 {name=p187 lab=VSS}
C {lab_pin.sym} 1140 -640 0 0 {name=p188 lab=VSS}
C {pmos4-v.sym} 1150 -800 0 0 {name=M30 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1200 -800 0 1 {name=p189 lab=VCC}
C {pmos4-v.sym} 990 -800 0 1 {name=M12 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 940 -800 0 0 {name=p190 lab=VCC}
C {nmos4-v.sym} 1050 -510 0 0 {name=M32 verilog_gate=nmos del=50,50,50 model=nmos w=1u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1100 -510 0 1 {name=p191 lab=VSS}
C {lab_pin.sym} 1070 -880 0 0 {name=p192 lab=VCC}
C {lab_pin.sym} 1040 -380 0 0 {name=p193 lab=VSSI}
C {nmos4-v.sym} 1530 -510 0 0 {name=M17 verilog_gate=nmos del=50,50,50 model=nmos w=1u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1580 -510 0 1 {name=p194 lab=VSS}
C {pmos4-v.sym} 1530 -800 0 0 {name=M13 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1580 -800 0 1 {name=p195 lab=VCC}
C {lab_pin.sym} 1520 -870 0 0 {name=p196 lab=VCC}
C {lab_pin.sym} 1520 -380 0 0 {name=p197 lab=VSSI}
C {lab_pin.sym} 1790 -750 0 0 {name=l49 lab=SAOUTF}
C {parax_cap.sym} 1620 -700 0 0 {name=c3 value=4f}
C {lab_pin.sym} 1300 -750 0 0 {name=l51 lab=OUTDIFF}
C {lab_pin.sym} 1070 -570 0 0 {name=l52 lab=SN}
C {lab_pin.sym} 1010 -770 0 1 {name=l53 lab=GN}
C {parax_cap.sym} 1060 -790 0 0 {name=c5 value=4f}
C {parax_cap.sym} 990 -580 0 0 {name=c30 value=2f}
C {parax_cap.sym} 1260 -700 0 0 {name=c31 value=4f}
C {lab_pin.sym} 990 -510 0 0 {name=p198 lab=GN}
C {lab_pin.sym} 1230 -640 0 1 {name=l54 lab=PLUS}
C {lab_pin.sym} 910 -640 0 0 {name=l55 lab=MINUS}
C {ammeter.sym} 1070 -450 0 0 {name=vdiffn}
C {ammeter.sym} 1550 -450 0 0 {name=v3}
C {ammeter.sym} 1690 -1010 0 0 {name=v4}
C {ammeter.sym} 1200 -1010 0 0 {name=v6}
C {nmos4-v.sym} 2020 -510 0 0 {name=M19 verilog_gate=nmos del=50,50,50 model=nmos w=1u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 2070 -510 0 1 {name=p9 lab=VSS}
C {pmos4-v.sym} 2020 -800 0 0 {name=M21 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 2070 -800 0 1 {name=p10 lab=VCC}
C {lab_pin.sym} 2010 -870 0 0 {name=p11 lab=VCC}
C {lab_pin.sym} 2010 -380 0 0 {name=p12 lab=VSSI}
C {parax_cap.sym} 2110 -700 0 0 {name=c1 value=4f}
C {ammeter.sym} 2040 -450 0 0 {name=v1}
C {lab_pin.sym} 2370 -710 0 1 {name=l3 lab=SAOUT}
C {passgate.sym} 1920 -1160 0 1 {name=x3 m=1
+ wn=0.4u ln=0.13u
+ wp=0.4u lp=0.13u
+ VCCBPIN=VCC VSSBPIN=VSS extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1840 -1290 0 1 {name=l5 sig_type=std_logic lab=CALB}
C {lab_pin.sym} 1840 -1230 0 1 {name=l6 sig_type=std_logic lab=CALBB}
C {nmos4-v.sym} 2080 -1100 0 0 {name=M23 verilog_gate=nmos del=50,50,50 model=nmos w=1.5u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 2130 -1100 0 1 {name=p13 lab=VSS}
C {pmos4-v.sym} 2080 -1330 0 0 {name=M24 verilog_gate=pmos del=50,50,50 model=pmos w=3u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 2130 -1330 0 1 {name=p14 lab=VCC}
C {lab_pin.sym} 2070 -1400 0 0 {name=p16 lab=VCC}
C {lab_pin.sym} 2070 -970 0 0 {name=p17 lab=VSSI}
C {lab_pin.sym} 1960 -1320 0 0 {name=l8 lab=ZERO2}
C {ammeter.sym} 2100 -1040 0 0 {name=v5}
C {pmos4-v.sym} 2160 -810 0 0 {name=M6 verilog_gate=pmos del=50,50,50 model=pmos w=0.6u l=0.2u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 2210 -810 0 1 {name=p18 lab=VCC}
C {lab_pin.sym} 2150 -880 0 0 {name=p19 lab=VCC}
C {lab_pin.sym} 2140 -810 0 0 {name=l2 lab=EN}
C {pmos4-v.sym} 640 -680 0 1 {name=M18 verilog_gate=pmos del=50,50,50 model=pmos w=4u l=0.4u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 590 -680 0 0 {name=p20 lab=VCC}
C {pmos4-v.sym} 400 -680 0 0 {name=M25 verilog_gate=pmos del=50,50,50 model=pmos w=4u l=0.4u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 450 -680 0 1 {name=p21 lab=VCC}
C {lab_pin.sym} 390 -550 0 0 {name=p22 lab=VSS}
C {lab_pin.sym} 650 -550 0 1 {name=p23 lab=VSS}
C {lab_pin.sym} 490 -460 0 0 {name=p24 lab=VSSI}
C {pmos4-v.sym} 510 -810 0 0 {name=M28 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 560 -810 0 1 {name=p25 lab=VCC}
C {lab_pin.sym} 530 -860 0 0 {name=p26 lab=VCC}
C {lab_pin.sym} 490 -810 0 0 {name=l7 lab=GP}
C {lab_pin.sym} 460 -580 0 1 {name=l9 lab=GP}
C {lab_pin.sym} 380 -680 0 0 {name=l10 lab=MINUS}
C {lab_pin.sym} 660 -680 0 1 {name=l11 lab=PLUS}
C {lab_pin.sym} 680 -610 0 1 {name=l12 lab=OUTDIFF}
C {nmos4-v.sym} 600 -550 0 0 {name=M26 verilog_gate=nmos del=50,50,50 model=nmos w=1u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {nmos4-v.sym} 440 -550 0 1 {name=M1 verilog_gate=nmos del=50,50,50 model=nmos w=1u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {parax_cap.sym} 500 -540 0 0 {name=c2 value=4f}
C {lab_pin.sym} 530 -760 0 0 {name=l13 lab=SP}
C {lab_pin.sym} 1920 -1190 0 1 {name=l5 sig_type=std_logic lab=CALB}
C {lab_pin.sym} 1920 -1130 0 1 {name=l6 sig_type=std_logic lab=CALBB}
C {nmos4-v.sym} 2160 -1070 0 0 {name=M23 verilog_gate=nmos del=50,50,50 model=nmos w=1.5u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 2210 -1070 0 1 {name=p13 lab=VSS}
C {pmos4-v.sym} 2160 -1230 0 0 {name=M24 verilog_gate=pmos del=50,50,50 model=pmos w=3u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 2210 -1230 0 1 {name=p14 lab=VCC}
C {lab_pin.sym} 2150 -1300 0 0 {name=p16 lab=VCC}
C {lab_pin.sym} 2150 -940 0 0 {name=p17 lab=VSSI}
C {lab_pin.sym} 2040 -1220 0 0 {name=l8 lab=ZERO2}
C {ammeter.sym} 2180 -1010 0 0 {name=v5}
C {pmos4-v.sym} 2240 -810 0 0 {name=M6 verilog_gate=pmos del=50,50,50 model=pmos w=0.6u l=0.2u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 2290 -810 0 1 {name=p18 lab=VCC}
C {lab_pin.sym} 2230 -880 0 0 {name=p19 lab=VCC}
C {lab_pin.sym} 2220 -810 0 0 {name=l2 lab=EN}
C {pmos4-v.sym} 770 -590 0 1 {name=M18 verilog_gate=pmos del=50,50,50 model=pmos w=4u l=0.4u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 720 -590 0 0 {name=p20 lab=VCC}
C {pmos4-v.sym} 530 -590 0 0 {name=M25 verilog_gate=pmos del=50,50,50 model=pmos w=4u l=0.4u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 580 -590 0 1 {name=p21 lab=VCC}
C {lab_pin.sym} 520 -460 0 0 {name=p22 lab=VSS}
C {lab_pin.sym} 780 -460 0 1 {name=p23 lab=VSS}
C {lab_pin.sym} 620 -370 0 0 {name=p24 lab=VSSI}
C {pmos4-v.sym} 640 -780 0 0 {name=M28 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 690 -780 0 1 {name=p25 lab=VCC}
C {lab_pin.sym} 660 -830 0 0 {name=p26 lab=VCC}
C {lab_pin.sym} 570 -780 0 0 {name=l7 lab=GP}
C {lab_pin.sym} 550 -530 0 1 {name=l9 lab=GP}
C {lab_pin.sym} 490 -590 0 0 {name=l10 lab=MINUS}
C {lab_pin.sym} 810 -590 0 1 {name=l11 lab=PLUS}
C {lab_pin.sym} 810 -520 0 1 {name=l12 lab=OUTDIFF}
C {nmos4-v.sym} 730 -460 0 0 {name=M26 verilog_gate=nmos del=50,50,50 model=nmos w=1u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {nmos4-v.sym} 570 -460 0 1 {name=M1 verilog_gate=nmos del=50,50,50 model=nmos w=1u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {parax_cap.sym} 630 -450 0 0 {name=c2 value=4f}
C {lab_pin.sym} 660 -670 0 0 {name=l13 lab=SP}
C {launcher.sym} 930 -260 0 0 {name=h2
descr="Simulate"
tclcommand="xschem netlist; xschem simulate"}
C {parax_cap.sym} 980 -1090 0 0 {name=c4 value=5f}
C {parax_cap.sym} 1470 -1090 0 0 {name=c6 value=5f}
C {parax_cap.sym} 1960 -1090 0 0 {name=c7 value=5f}
C {launcher.sym} 315 -1415 0 0 {name=h1
C {parax_cap.sym} 1060 -1060 0 0 {name=c4 value=5f}
C {parax_cap.sym} 1550 -1060 0 0 {name=c6 value=5f}
C {parax_cap.sym} 2040 -1060 0 0 {name=c7 value=5f}
C {launcher.sym} 65 -1075 0 0 {name=h1
descr="Select arrow and
Ctrl-Left-Click to load/unload waveforms"
Ctrl-Left-Click to
load/unload waveforms"
tclcommand="
xschem raw_read $netlist_dir/[file tail [file rootname [xschem get current_name]]].raw
"
}
C {ngspice_probe.sym} 890 -700 0 0 {name=r1}
C {ngspice_probe.sym} 660 -680 0 0 {name=r1}
C {ngspice_probe.sym} 380 -680 0 1 {name=r1}
C {ngspice_probe.sym} 1130 -640 0 0 {name=r1}
C {ngspice_probe.sym} 850 -640 0 1 {name=r2}
C {ngspice_probe.sym} 1000 -590 0 0 {name=r1}
C {ngspice_probe.sym} 1260 -710 0 0 {name=r1}
C {ngspice_probe.sym} 1600 -710 0 0 {name=r1}
C {ngspice_probe.sym} 2100 -710 0 0 {name=r1}
C {ngspice_probe.sym} 1610 -1390 0 0 {name=r1}
C {ngspice_probe.sym} 1470 -1200 0 0 {name=r1}
C {ngspice_probe.sym} 980 -1200 0 0 {name=r1}
C {ngspice_probe.sym} 1040 -860 0 0 {name=r1}
C {ngspice_probe.sym} 530 -860 0 0 {name=r1}
C {ngspice_probe.sym} 200 -570 0 0 {name=r1}
C {ngspice_probe.sym} 120 -570 0 1 {name=r1}
C {ngspice_probe.sym} 200 -700 0 0 {name=r1}
C {ngspice_probe.sym} 120 -470 0 0 {name=r1}
C {ngspice_probe.sym} 1960 -1200 0 0 {name=r1}
C {ammeter.sym} 660 -710 0 0 {name=vdiffp}
C {ammeter.sym} 1300 -870 0 0 {name=vcalib0}
C {ammeter.sym} 1790 -870 0 0 {name=vcalib1}
C {ammeter.sym} 2370 -870 0 0 {name=vcalib2}
C {test_generators.sym} 480 -500 0 0 {name=x28}

11
xschem_library/ngspice/autozero_comp.sym Normal file
View File

@ -0,0 +1,11 @@
v {xschem version=3.4.5 file_version=1.2}
K {type=subcircuit
format="@name @pinlist @symname"
template="name=x1"
}
T {@symname} -76.5 -6 0 0 0.3 0.3 {}
T {@name} 135 -22 0 0 0.2 0.2 {}
L 4 -130 -10 130 -10 {}
L 4 -130 10 130 10 {}
L 4 -130 -10 -130 10 {}
L 4 130 -10 130 10 {}