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xschem
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added attributes spice_ignore=short, verilog_ignore=short, .... that will transform the instance into a short in the current netlisting mode, shorting all pins to the same net. Works similarly as lvs_ignore=short, but does not need lvs_ignore global setting

This commit is contained in:
stefan schippers 2023-06-07 03:41:49 +02:00
parent 38a28a3acb
commit 245993f034
17 changed files with 284 additions and 206 deletions
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75
src/actions.c
View File

@ -679,6 +679,7 @@ int set_rect_flags(xRect *r)
int set_sym_flags(xSymbol *sym)
{
const char *ptr;
sym->flags = 0;
my_strdup2(_ALLOC_ID_, &sym->templ,
get_tok_value(sym->prop_ptr, "template", 0));
@ -692,22 +693,34 @@ int set_sym_flags(xSymbol *sym)
if(!strcmp(get_tok_value(sym->prop_ptr,"hide",0), "true"))
sym->flags |= HIDE_INST;
if(!strcmp(get_tok_value(sym->prop_ptr,"spice_ignore",0), "true"))
ptr = get_tok_value(sym->prop_ptr,"spice_ignore",0);
if(!strcmp(ptr, "short"))
sym->flags |= SPICE_SHORT;
else if(!strcmp(ptr, "true") || !strcmp(ptr, "open"))
sym->flags |= SPICE_IGNORE;
if(!strcmp(get_tok_value(sym->prop_ptr,"verilog_ignore",0), "true"))
ptr = get_tok_value(sym->prop_ptr,"verilog_ignore",0);
if(!strcmp(ptr, "short"))
sym->flags |= VERILOG_SHORT;
else if(!strcmp(ptr, "true") || !strcmp(ptr, "open"))
sym->flags |= VERILOG_IGNORE;
if(!strcmp(get_tok_value(sym->prop_ptr,"vhdl_ignore",0), "true"))
ptr = get_tok_value(sym->prop_ptr,"vhdl_ignore",0);
if(!strcmp(ptr, "short"))
sym->flags |= VHDL_SHORT;
else if(!strcmp(ptr, "true") || !strcmp(ptr, "open"))
sym->flags |= VHDL_IGNORE;
if(!strcmp(get_tok_value(sym->prop_ptr,"tedax_ignore",0), "true"))
ptr = get_tok_value(sym->prop_ptr,"tedax_ignore",0);
if(!strcmp(ptr, "short"))
sym->flags |= TEDAX_SHORT;
else if(!strcmp(ptr, "true") || !strcmp(ptr, "open"))
sym->flags |= TEDAX_IGNORE;
if(!strcmp(get_tok_value(sym->prop_ptr,"lvs_ignore",0), "short"))
ptr = get_tok_value(sym->prop_ptr,"lvs_ignore",0);
if(!strcmp(ptr, "short"))
sym->flags |= LVS_IGNORE_SHORT;
if(!strcmp(get_tok_value(sym->prop_ptr,"lvs_ignore",0), "open"))
else if(!strcmp(ptr, "true") || !strcmp(ptr, "open"))
sym->flags |= LVS_IGNORE_OPEN;
dbg(1, "set_sym_flags: inst %s flags=%d\n", sym->name, sym->flags);
return 0;
@ -715,6 +728,7 @@ int set_sym_flags(xSymbol *sym)
int set_inst_flags(xInstance *inst)
{
const char *ptr;
inst->flags &= IGNORE_INST; /* do not clear IGNORE_INST bit, used in draw_symbol() */
my_strdup2(_ALLOC_ID_, &inst->instname, get_tok_value(inst->prop_ptr, "name", 0));
if(inst->ptr >=0) {
@ -728,26 +742,41 @@ int set_inst_flags(xInstance *inst)
if(!strcmp(get_tok_value(inst->prop_ptr,"hide",0), "true"))
inst->flags |= HIDE_INST;
if(!strcmp(get_tok_value(inst->prop_ptr,"spice_ignore",0), "true"))
ptr = get_tok_value(inst->prop_ptr,"spice_ignore",0);
if(!strcmp(ptr, "short"))
inst->flags |= SPICE_SHORT;
else if(!strcmp(ptr, "true") || !strcmp(ptr, "open"))
inst->flags |= SPICE_IGNORE;
if(!strcmp(get_tok_value(inst->prop_ptr,"verilog_ignore",0), "true"))
inst->flags |= VERILOG_IGNORE;
if(!strcmp(get_tok_value(inst->prop_ptr,"vhdl_ignore",0), "true"))
inst->flags |= VHDL_IGNORE;
if(!strcmp(get_tok_value(inst->prop_ptr,"tedax_ignore",0), "true"))
inst->flags |= TEDAX_IGNORE;
if(!strcmp(get_tok_value(inst->prop_ptr,"hide_texts",0), "true"))
inst->flags |= HIDE_SYMBOL_TEXTS;
if(!strcmp(get_tok_value(inst->prop_ptr,"highlight",0), "true"))
inst->flags |= HILIGHT_CONN;
if(!strcmp(get_tok_value(inst->prop_ptr,"lvs_ignore",0), "open"))
ptr = get_tok_value(inst->prop_ptr,"verilog_ignore",0);
if(!strcmp(ptr, "short"))
inst->flags |= VERILOG_SHORT;
else if(!strcmp(ptr, "true") || !strcmp(ptr, "open"))
inst->flags |= VERILOG_IGNORE;
ptr = get_tok_value(inst->prop_ptr,"vhdl_ignore",0);
if(!strcmp(ptr, "short"))
inst->flags |= VHDL_SHORT;
else if(!strcmp(ptr, "true") || !strcmp(ptr, "open"))
inst->flags |= VHDL_IGNORE;
ptr = get_tok_value(inst->prop_ptr,"tedax_ignore",0);
if(!strcmp(ptr, "short"))
inst->flags |= TEDAX_SHORT;
else if(!strcmp(ptr, "true") || !strcmp(ptr, "open"))
inst->flags |= TEDAX_IGNORE;
ptr = get_tok_value(inst->prop_ptr,"lvs_ignore",0);
if(!strcmp(ptr, "short"))
inst->flags |= LVS_IGNORE_SHORT;
else if(!strcmp(ptr, "true") || !strcmp(ptr, "open"))
inst->flags |= LVS_IGNORE_OPEN;
if(!strcmp(get_tok_value(inst->prop_ptr,"lvs_ignore",0), "short"))
inst->flags |= LVS_IGNORE_SHORT;
if(!strcmp(get_tok_value(inst->prop_ptr,"hide_texts",0), "true"))
inst->flags |= HIDE_SYMBOL_TEXTS;
if(!strcmp(get_tok_value(inst->prop_ptr,"highlight",0), "true"))
inst->flags |= HILIGHT_CONN;
inst->embed = !strcmp(get_tok_value(inst->prop_ptr, "embed", 2), "true");

4
src/draw.c
View File

@ -489,9 +489,7 @@ void draw_symbol(int what,int c, int n,int layer,short tmp_flip, short rot,
}
}
}
if(lvs_ignore &&
( (xctx->inst[n].flags & LVS_IGNORE_SHORT) ||
(xctx->sym[xctx->inst[n].ptr].flags & LVS_IGNORE_SHORT)) ) {
if(shorted_instance(n, lvs_ignore)) {
c = PINLAYER;
what = NOW;
disabled = 2;

16
src/move.c
View File

@ -516,20 +516,8 @@ void find_inst_to_be_redrawn(int what)
int shorted_inst;
if(xctx->inst[n].ptr < 0 ) continue;
type=xctx->sym[xctx->inst[n].ptr].type;
shorted_inst =
lvs_ignore &&
/*
* (
* (inst[n].flags & LVS_IGNORE_SHORT) ||
* (xctx->sym[xctx->inst[n].ptr].flags & LVS_IGNORE_SHORT)
* ) &&
* can not use LVS_IGNORE_SHORT .flag since i want to re-display also when
* attribute is changed from short to anything else */
(
get_tok_value(inst[n].prop_ptr, "lvs_ignore", 0)[0] ||
get_tok_value(xctx->sym[xctx->inst[n].ptr].prop_ptr, "lvs_ignore", 0)[0]
);
set_inst_flags(&xctx->inst[n]);
shorted_inst = shorted_instance(n, lvs_ignore);
/* collect all nodes connected to instances that set node names */
if(type &&
(

54
src/netlist.c
View File

@ -670,12 +670,14 @@ static void set_inst_node(int i, int j, const char *node)
xInstance * const inst = xctx->inst;
int inst_mult;
xRect *rect = (inst[i].ptr + xctx->sym)->rect[PINLAYER];
int skip;
if(!inst[i].node) return;
dbg(1, "set_inst_node(): inst %s pin %d <-- %s\n", inst[i].instname, j, node);
expandlabel(inst[i].instname, &inst_mult);
my_strdup(_ALLOC_ID_, &inst[i].node[j], node);
if(!for_netlist) {
skip = skip_instance(i, netlist_lvs_ignore);
if(!for_netlist || skip) {
bus_node_hash_lookup(inst[i].node[j],"", XINSERT, 0,"","","","");
} else {
const char *dir = get_tok_value(rect[j].prop_ptr, "dir",0);
@ -817,7 +819,28 @@ static int name_attached_inst(int i, double x0, double y0, int sqx, int sqy, con
return err;
}
int skip_instance(int i, int lvs_ignore, int mask)
int shorted_instance(int i, int lvs_ignore)
{
xInstance * const inst = xctx->inst;
xSymbol * const sym = xctx->sym;
int shorted = 0;
if(inst[i].ptr < 0) shorted = 0;
else if(lvs_ignore) {
if((inst[i].flags & LVS_IGNORE_SHORT) || (sym[inst[i].ptr].flags & LVS_IGNORE_SHORT) ) shorted = 1;
} else if(xctx->netlist_type == CAD_SPICE_NETLIST) {
if((inst[i].flags & SPICE_SHORT) || (sym[inst[i].ptr].flags & SPICE_SHORT) ) shorted = 1;
} else if(xctx->netlist_type == CAD_VERILOG_NETLIST) {
if((inst[i].flags & VERILOG_SHORT) || (sym[inst[i].ptr].flags & VERILOG_SHORT) ) shorted = 1;
} else if(xctx->netlist_type == CAD_VHDL_NETLIST) {
if((inst[i].flags & VHDL_SHORT) || (sym[inst[i].ptr].flags & VHDL_SHORT) ) shorted = 1;
} else if(xctx->netlist_type == CAD_TEDAX_NETLIST)
if((inst[i].flags & TEDAX_SHORT) || (sym[inst[i].ptr].flags & TEDAX_SHORT) ) shorted = 1;
return shorted;
}
static int skip_instance2(int i, int lvs_ignore, int mask)
{
int skip = 0;
if(xctx->inst[i].ptr < 0) skip = 1;
@ -828,6 +851,23 @@ int skip_instance(int i, int lvs_ignore, int mask)
return skip;
}
int skip_instance(int i, int lvs_ignore)
{
int skip = 0;
if(xctx->netlist_type == CAD_SPICE_NETLIST)
skip = skip_instance2(i, lvs_ignore, SPICE_SHORT | SPICE_IGNORE);
else if(xctx->netlist_type == CAD_VERILOG_NETLIST)
skip = skip_instance2(i, lvs_ignore, VERILOG_SHORT | VERILOG_IGNORE);
else if(xctx->netlist_type == CAD_VHDL_NETLIST)
skip = skip_instance2(i, lvs_ignore, VHDL_SHORT | VHDL_IGNORE);
else if(xctx->netlist_type == CAD_TEDAX_NETLIST)
skip = skip_instance2(i, lvs_ignore, TEDAX_SHORT | TEDAX_IGNORE);
else skip = 0;
dbg(1, "skip_instance(): instance %d skip=%d\n", i, skip);
return skip;
}
/* what:
* Determine if given "ninst" instance has pass-through pins
@ -887,10 +927,7 @@ static int instcheck(int n, int p)
int rects = xctx->sym[inst[n].ptr].rects[PINLAYER];
int bus_tap = !strcmp(xctx->sym[inst[n].ptr].type, "bus_tap");
int k = inst[n].ptr;
int shorted_inst =
(k >=0) &&
((inst[n].flags & LVS_IGNORE_SHORT) || (sym[k].flags & LVS_IGNORE_SHORT)) &&
netlist_lvs_ignore;
int shorted_inst = shorted_instance(n, netlist_lvs_ignore);
if(!inst[n].node) return 0;
@ -1022,7 +1059,6 @@ static int name_nodes_of_pins_labels_and_propagate()
for (i=0;i<instances; ++i) {
/* name ipin opin label node fields from prop_ptr attributes */
if(inst[i].ptr<0) continue;
my_strdup(_ALLOC_ID_, &type,(inst[i].ptr+ xctx->sym)->type);
if(print_erc && (!inst[i].instname || !inst[i].instname[0]) &&
!get_tok_value((inst[i].ptr+ xctx->sym)->templ, "name", 0)[0]
@ -1050,7 +1086,7 @@ static int name_nodes_of_pins_labels_and_propagate()
xctx->hilight_nets=1;
}
if(type && inst[i].node && IS_LABEL_OR_PIN(type) ) { /* instance must have a pin! */
if(for_netlist>0) {
if(for_netlist) {
/* 20150918 skip labels / pins if ignore property specified on instance */
if( xctx->netlist_type == CAD_VERILOG_NETLIST && (inst[i].flags & VERILOG_IGNORE)) continue;
if( xctx->netlist_type == CAD_SPICE_NETLIST && (inst[i].flags & SPICE_IGNORE)) continue;
@ -1093,7 +1129,7 @@ static int name_nodes_of_pins_labels_and_propagate()
/* do not count multiple labels/pins with same name */
bus_node_hash_lookup(inst[i].node[0], /* insert node in hash table */
dir, XINSERT, port, sig_type, verilog_type, value, class);
dir, XINSERT, port, sig_type, verilog_type, value, class);
get_inst_pin_coord(i, 0, &x0, &y0);
get_square(x0, y0, &sqx, &sqy);

14
src/spice_netlist.c
View File

@ -166,7 +166,7 @@ static int spice_netlist(FILE *fd, int spice_stop )
err |= traverse_node_hash(); /* print all warnings about unconnected floatings etc */
for(i=0;i<xctx->instances; ++i) /* print first ipin/opin defs ... */
{
if(skip_instance(i, lvs_ignore, SPICE_IGNORE)) continue;
if(skip_instance(i, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && IS_PIN(type) ) {
if(top_sub && !flag) {
@ -187,7 +187,7 @@ static int spice_netlist(FILE *fd, int spice_stop )
if(top_sub) fprintf(fd, "\n");
for(i=0;i<xctx->instances; ++i) /* ... then print other lines */
{
if(skip_instance(i, lvs_ignore, SPICE_IGNORE)) continue;
if(skip_instance(i, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && !IS_LABEL_OR_PIN(type) ) {
@ -278,7 +278,7 @@ int global_spice_netlist(int global) /* netlister driver */
first = 0;
for(i=0;i<xctx->instances; ++i) /* print netlist_commands of top level cell with 'place=header' property */
{
if(skip_instance(i, lvs_ignore, SPICE_IGNORE)) continue;
if(skip_instance(i, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
my_strdup(_ALLOC_ID_, &place,get_tok_value((xctx->inst[i].ptr+ xctx->sym)->prop_ptr,"place",0));
if( type && !strcmp(type,"netlist_commands") ) {
@ -307,7 +307,7 @@ int global_spice_netlist(int global) /* netlister driver */
/* print top subckt ipin/opins */
for(i=0;i<xctx->instances; ++i) {
if(skip_instance(i, lvs_ignore, SPICE_IGNORE)) continue;
if(skip_instance(i, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
dbg(1, "global_spice_netlist(): |%s|\n", type);
/*
@ -329,7 +329,7 @@ int global_spice_netlist(int global) /* netlister driver */
for(i=0;i<xctx->instances; ++i) /* print netlist_commands of top level cell with no 'place=end' property
and no place=header */
{
if(skip_instance(i, lvs_ignore, SPICE_IGNORE)) continue;
if(skip_instance(i, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
my_strdup(_ALLOC_ID_, &place,get_tok_value((xctx->inst[i].ptr+ xctx->sym)->prop_ptr,"place",0));
if( type && !strcmp(type,"netlist_commands") ) {
@ -400,7 +400,7 @@ int global_spice_netlist(int global) /* netlister driver */
get_additional_symbols(1);
for(i=0;i<xctx->symbols; ++i)
{
if(xctx->sym[i].flags & SPICE_IGNORE) continue;
if(xctx->sym[i].flags & (SPICE_IGNORE | SPICE_SHORT)) continue;
if(lvs_ignore && (xctx->sym[i].flags & LVS_IGNORE)) continue;
if(!xctx->sym[i].type) continue;
my_strdup(_ALLOC_ID_, &abs_path, abs_sym_path(xctx->sym[i].name, ""));
@ -463,7 +463,7 @@ int global_spice_netlist(int global) /* netlister driver */
if(!split_f) {
for(i=0;i<xctx->instances; ++i) /* print netlist_commands of top level cell with 'place=end' property */
{
if(skip_instance(i, lvs_ignore, SPICE_IGNORE)) continue;
if(skip_instance(i, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
my_strdup(_ALLOC_ID_, &place,get_tok_value((xctx->inst[i].ptr+ xctx->sym)->prop_ptr,"place",0));
if( type && !strcmp(type,"netlist_commands") ) {

6
src/tedax_netlist.c
View File

@ -36,7 +36,7 @@ static int tedax_netlist(FILE *fd, int tedax_stop )
if(!tedax_stop) {
for(i=0;i<xctx->instances; ++i) /* print first ipin/opin defs ... */
{
if(skip_instance(i, lvs_ignore, TEDAX_IGNORE)) continue;
if(skip_instance(i, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && IS_PIN(type) ) {
print_tedax_element(fd, i) ; /* this is the element line */
@ -44,7 +44,7 @@ static int tedax_netlist(FILE *fd, int tedax_stop )
}
for(i=0;i<xctx->instances; ++i) /* ... then print other lines */
{
if(skip_instance(i, lvs_ignore, TEDAX_IGNORE)) continue;
if(skip_instance(i, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && !IS_LABEL_OR_PIN(type) ) {
@ -204,7 +204,7 @@ int global_tedax_netlist(int global) /* netlister driver */
get_additional_symbols(1);
for(i=0;i<xctx->symbols; ++i)
{
if(xctx->sym[i].flags & TEDAX_IGNORE) continue;
if(xctx->sym[i].flags & (TEDAX_IGNORE | TEDAX_SHORT)) continue;
if(lvs_ignore && (xctx->sym[i].flags & LVS_IGNORE)) continue;
if(!xctx->sym[i].type) continue;
my_strdup2(_ALLOC_ID_, &abs_path, abs_sym_path(tcl_hook2(xctx->sym[i].name), ""));

26
src/verilog_netlist.c
View File

@ -45,11 +45,11 @@ static int verilog_netlist(FILE *fd , int verilog_stop)
{
for(i=0;i<xctx->instances; ++i) /* ... print all element except ipin opin labels use package */
{
if(skip_instance(i, lvs_ignore, VERILOG_IGNORE)) continue;
if(skip_instance(i, lvs_ignore)) continue;
dbg(2, "verilog_netlist(): into the netlisting loop\n");
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type &&
( !IS_LABEL_OR_PIN(type) &&
( !IS_LABEL_SH_OR_PIN(type) &&
strcmp(type,"netlist_commands")&&
strcmp(type,"timescale")&&
strcmp(type,"verilog_preprocessor")
@ -129,7 +129,7 @@ int global_verilog_netlist(int global) /* netlister driver */
fmt_attr = xctx->format ? xctx->format : "verilog_format";
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore, VERILOG_IGNORE)) continue;
if(skip_instance(i, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"timescale")==0 || strcmp(type,"verilog_preprocessor")==0) )
{
@ -159,7 +159,7 @@ int global_verilog_netlist(int global) /* netlister driver */
tmp=0;
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore, VERILOG_IGNORE)) continue;
if(skip_instance(i, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"opin"))==0)
{
@ -173,7 +173,7 @@ int global_verilog_netlist(int global) /* netlister driver */
dbg(1, "global_verilog_netlist(): printing top level inout pins\n");
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore, VERILOG_IGNORE)) continue;
if(skip_instance(i, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"iopin"))==0)
{
@ -187,7 +187,7 @@ int global_verilog_netlist(int global) /* netlister driver */
dbg(1, "global_verilog_netlist(): printing top level input pins\n");
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore, VERILOG_IGNORE)) continue;
if(skip_instance(i, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"ipin"))==0)
{
@ -215,7 +215,7 @@ int global_verilog_netlist(int global) /* netlister driver */
dbg(1, "global_verilog_netlist(): printing top level out pins\n");
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore, VERILOG_IGNORE)) continue;
if(skip_instance(i, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"opin"))==0)
{
@ -234,7 +234,7 @@ int global_verilog_netlist(int global) /* netlister driver */
dbg(1, "global_verilog_netlist(): printing top level inout pins\n");
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore, VERILOG_IGNORE)) continue;
if(skip_instance(i, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"iopin"))==0)
{
@ -253,7 +253,7 @@ int global_verilog_netlist(int global) /* netlister driver */
dbg(1, "global_verilog_netlist(): printing top level input pins\n");
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore, VERILOG_IGNORE)) continue;
if(skip_instance(i, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"ipin"))==0)
{
@ -275,7 +275,7 @@ int global_verilog_netlist(int global) /* netlister driver */
fprintf(fd,"---- begin user architecture code\n");
for(i=0;i<xctx->instances; ++i) {
if(skip_instance(i, lvs_ignore, VERILOG_IGNORE)) continue;
if(skip_instance(i, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if(type && !strcmp(type,"netlist_commands")) {
fprintf(fd, "%s\n", get_tok_value(xctx->inst[i].prop_ptr,"value", 0));
@ -329,7 +329,7 @@ int global_verilog_netlist(int global) /* netlister driver */
get_additional_symbols(1);
for(i=0;i<xctx->symbols; ++i)
{
if(xctx->sym[i].flags & VERILOG_IGNORE) continue;
if(xctx->sym[i].flags & (VERILOG_IGNORE | VERILOG_SHORT)) continue;
if(lvs_ignore && (xctx->sym[i].flags & LVS_IGNORE)) continue;
if(!xctx->sym[i].type) continue;
my_strdup2(_ALLOC_ID_, &abs_path, abs_sym_path(tcl_hook2(xctx->sym[i].name), ""));
@ -459,7 +459,7 @@ int verilog_block_netlist(FILE *fd, int i)
fmt_attr = xctx->format ? xctx->format : "verilog_format";
for(j=0;j<xctx->instances; ++j)
{
if(skip_instance(j, lvs_ignore, VERILOG_IGNORE)) continue;
if(skip_instance(j, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[j].ptr+ xctx->sym)->type);
if( type && ( strcmp(type,"timescale")==0 || strcmp(type,"verilog_preprocessor")==0) )
{
@ -559,7 +559,7 @@ int verilog_block_netlist(FILE *fd, int i)
err |= verilog_netlist(fd, verilog_stop);
fprintf(fd,"---- begin user architecture code\n");
for(l=0;l<xctx->instances; ++l) {
if(skip_instance(l, lvs_ignore, VERILOG_IGNORE)) continue;
if(skip_instance(l, lvs_ignore)) continue;
if(xctx->netlist_count &&
!strcmp(get_tok_value(xctx->inst[l].prop_ptr, "only_toplevel", 0), "true")) continue;

36
src/vhdl_netlist.c
View File

@ -39,7 +39,7 @@ static int vhdl_netlist(FILE *fd , int vhdl_stop)
fprintf(fd, "//// begin user declarations\n");
for(l=0;l<xctx->instances; ++l)
{
if(skip_instance(l, lvs_ignore, VHDL_IGNORE)) continue;
if(skip_instance(l, lvs_ignore)) continue;
if(!(xctx->inst[l].ptr+ xctx->sym)->type) continue;
if(!strcmp((xctx->inst[l].ptr+ xctx->sym)->type, "arch_declarations") )
@ -55,7 +55,7 @@ static int vhdl_netlist(FILE *fd , int vhdl_stop)
fprintf(fd, "//// begin user attributes\n");
for(l=0;l<xctx->instances; ++l)
{
if(skip_instance(l, lvs_ignore, VHDL_IGNORE)) continue;
if(skip_instance(l, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[l].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"attributes"))==0)
{
@ -70,11 +70,11 @@ static int vhdl_netlist(FILE *fd , int vhdl_stop)
{
for(i=0;i<xctx->instances; ++i) /* ... print all element except ipin opin labels use package */
{ /* dont print elements with vhdl_ignore=true set in symbol */
if(skip_instance(i, lvs_ignore, VHDL_IGNORE)) continue;
if(skip_instance(i, lvs_ignore)) continue;
dbg(2, "vhdl_netlist(): into the netlisting loop\n");
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type &&
( !IS_LABEL_OR_PIN(type) &&
( !IS_LABEL_SH_OR_PIN(type) &&
strcmp(type,"generic")&&
strcmp(type,"use")&&
strcmp(type,"netlist_commands")&&
@ -152,7 +152,7 @@ int global_vhdl_netlist(int global) /* netlister driver */
dbg(1, "global_vhdl_netlist(): printing top level packages\n");
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore, VHDL_IGNORE)) continue;
if(skip_instance(i, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"package"))==0)
{
@ -167,7 +167,7 @@ int global_vhdl_netlist(int global) /* netlister driver */
dbg(1, "global_vhdl_netlist(): printing top level use statements\n");
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore, VHDL_IGNORE)) continue;
if(skip_instance(i, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"use"))==0)
{
@ -232,7 +232,7 @@ int global_vhdl_netlist(int global) /* netlister driver */
tmp=0;
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore, VHDL_IGNORE)) continue;
if(skip_instance(i, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &sig_type,get_tok_value(xctx->inst[i].prop_ptr,"sig_type",0));
if(!sig_type || sig_type[0]=='\0') my_strdup(_ALLOC_ID_, &sig_type,"std_logic");
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
@ -249,7 +249,7 @@ int global_vhdl_netlist(int global) /* netlister driver */
dbg(1, "global_vhdl_netlist(): printing top level inout pins\n");
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore, VHDL_IGNORE)) continue;
if(skip_instance(i, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &sig_type,get_tok_value(xctx->inst[i].prop_ptr,"sig_type",0));
if(!sig_type || sig_type[0]=='\0') my_strdup(_ALLOC_ID_, &sig_type,"std_logic");
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
@ -266,7 +266,7 @@ int global_vhdl_netlist(int global) /* netlister driver */
dbg(1, "global_vhdl_netlist(): printing top level input pins\n");
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore, VHDL_IGNORE)) continue;
if(skip_instance(i, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &sig_type,get_tok_value(xctx->inst[i].prop_ptr,"sig_type",0));
if(!sig_type || sig_type[0]=='\0') my_strdup(_ALLOC_ID_, &sig_type,"std_logic");
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
@ -284,7 +284,7 @@ int global_vhdl_netlist(int global) /* netlister driver */
dbg(1, "global_vhdl_netlist(): printing top level port attributes\n");
for(i=0;i<xctx->instances; ++i)
{
if(skip_instance(i, lvs_ignore, VHDL_IGNORE)) continue;
if(skip_instance(i, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"port_attributes"))==0)
{
@ -304,7 +304,7 @@ int global_vhdl_netlist(int global) /* netlister driver */
for(j=0;j<xctx->symbols; ++j)
{
if( strcmp(get_tok_value(xctx->sym[j].prop_ptr,"vhdl_primitive",0),"true")==0 ) continue;
if(xctx->sym[j].flags & VHDL_IGNORE) continue;
if(xctx->sym[j].flags & (VHDL_IGNORE | VHDL_SHORT)) continue;
if(lvs_ignore && (xctx->sym[j].flags & LVS_IGNORE)) continue;
if(!xctx->sym[j].type || (strcmp(xctx->sym[j].type,"primitive")!=0 &&
strcmp(xctx->sym[j].type,"subcircuit")!=0)) continue;
@ -363,7 +363,7 @@ int global_vhdl_netlist(int global) /* netlister driver */
fprintf(fd,"//// begin user architecture code\n");
for(i=0;i<xctx->instances; ++i) {
if(skip_instance(i, lvs_ignore, VHDL_IGNORE)) continue;
if(skip_instance(i, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
if(type && !strcmp(type,"netlist_commands")) {
fprintf(fd, "%s\n", get_tok_value(xctx->inst[i].prop_ptr,"value", 0));
@ -417,7 +417,7 @@ int global_vhdl_netlist(int global) /* netlister driver */
get_additional_symbols(1);
for(i=0;i<xctx->symbols; ++i)
{
if(xctx->sym[i].flags & VHDL_IGNORE) continue;
if(xctx->sym[i].flags & (VHDL_IGNORE | VHDL_SHORT)) continue;
if(lvs_ignore && (xctx->sym[i].flags & LVS_IGNORE)) continue;
if(!xctx->sym[i].type) continue;
my_strdup(_ALLOC_ID_, &abs_path, abs_sym_path(xctx->sym[i].name, ""));
@ -539,7 +539,7 @@ int vhdl_block_netlist(FILE *fd, int i)
dbg(1, "vhdl_block_netlist(): packages\n");
for(l=0;l<xctx->instances; ++l)
{
if(skip_instance(l, lvs_ignore, VHDL_IGNORE)) continue;
if(skip_instance(l, lvs_ignore)) continue;
if(!(xctx->inst[l].ptr+ xctx->sym)->type) continue;
if( !strcmp((xctx->inst[l].ptr+ xctx->sym)->type, "package") )
fprintf(fd, "%s\n", xctx->inst[l].prop_ptr);
@ -548,7 +548,7 @@ int vhdl_block_netlist(FILE *fd, int i)
dbg(1, "vhdl_block_netlist(): use statements\n");
for(l=0;l<xctx->instances; ++l)
{
if(skip_instance(l, lvs_ignore, VHDL_IGNORE)) continue;
if(skip_instance(l, lvs_ignore)) continue;
if(!(xctx->inst[l].ptr+ xctx->sym)->type) continue;
if( !strcmp((xctx->inst[l].ptr+ xctx->sym)->type, "use") )
fprintf(fd, "%s\n", xctx->inst[l].prop_ptr);
@ -590,7 +590,7 @@ int vhdl_block_netlist(FILE *fd, int i)
dbg(1, "vhdl_block_netlist(): port attributes\n");
for(l=0;l<xctx->instances; ++l)
{
if(skip_instance(l, lvs_ignore, VHDL_IGNORE)) continue;
if(skip_instance(l, lvs_ignore)) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[l].ptr+ xctx->sym)->type);
if( type && (strcmp(type,"port_attributes"))==0)
{
@ -625,7 +625,7 @@ int vhdl_block_netlist(FILE *fd, int i)
found=0;
for(l=0;l<xctx->instances; ++l)
{
if(skip_instance(l, lvs_ignore, VHDL_IGNORE)) continue;
if(skip_instance(l, lvs_ignore)) continue;
if(!xctx->x_strcmp(xctx->sym[j].name, tcl_hook2(xctx->inst[l].name)))
{
found=1; break;
@ -671,7 +671,7 @@ int vhdl_block_netlist(FILE *fd, int i)
fprintf(fd,"//// begin user architecture code\n");
for(l=0;l<xctx->instances; ++l) {
if(skip_instance(l, lvs_ignore, VHDL_IGNORE)) continue;
if(skip_instance(l, lvs_ignore)) continue;
if(xctx->netlist_count &&
!strcmp(get_tok_value(xctx->inst[l].prop_ptr, "only_toplevel", 0), "true")) continue;

3
src/xschem.h
View File

@ -1533,7 +1533,8 @@ extern void display_hilights(int what, char **str);
extern void redraw_hilights(int clear);
extern void set_tcl_netlist_type(void);
extern int prepare_netlist_structs(int for_netlist);
extern int skip_instance(int i, int lvs_ignore, int mask);
extern int skip_instance(int i, int lvs_ignore);
extern int shorted_instance(int i, int lvs_ignore);
extern int compare_schematics(const char *filename);
extern int warning_overlapped_symbols(int sel);
extern void free_simdata(void);

4
xschem_library/devices/capa.sym
View File

@ -1,4 +1,5 @@
v {xschem version=2.9.8 file_version=1.2}
v {xschem version=3.4.0 file_version=1.2
}
G {}
K {type=capacitor
format="@name @pinlist @value m=@m"
@ -7,6 +8,7 @@ value @name @value
device @name @device
@comptag"
verilog_ignore=true
vhdl_ignore=true
template="name=C1
m=1
value=1p

6
xschem_library/examples/0_examples_top.sch
View File

@ -79,14 +79,16 @@ T {Simulation
Graphs
} 1530 -550 0 0 0.6 0.6 {layer=4}
T {Bus rippers} 580 -380 0 0 0.6 0.6 {layer=4}
N 820 -420 940 -420 {lab=#net1}
N 860 -460 860 -370 {lab=#net2}
N 910 -420 940 -420 {lab=#net1}
N 860 -390 860 -370 {lab=#net2}
N 860 -390 920 -390 {lab=#net2}
N 880 -430 910 -420 {lab=#net1}
N 380 -310 640 -310 {lab=BUS[4:0]}
N 510 -400 510 -320 {lab=BUS[1]}
N 410 -350 410 -320 {lab=BUS[2]}
N 460 -400 460 -320 {lab=BUS[2:1]}
N 860 -460 860 -390 {lab=#net2}
N 820 -420 910 -420 {lab=#net1}
C {poweramp.sym} 480 -820 0 0 {name=x1
tclcommand="xschem descend"}
C {tesla.sym} 160 -700 0 0 {name=x2}

6
xschem_library/examples/classD_amp.sch
View File

@ -1,4 +1,4 @@
v {xschem version=3.1.0 file_version=1.2
v {xschem version=3.4.0 file_version=1.2
}
G {}
K {}
@ -205,8 +205,6 @@ N 460 -1060 460 -1020 {lab=#net1}
N 460 -700 460 -640 {lab=VNN}
N 460 -940 460 -920 {lab=OUT}
N 460 -1160 460 -1120 { lab=VPP}
N 570 -920 680 -920 {
lab=OUT}
N 220 -1020 460 -1020 {
lab=#net1}
N 340 -1090 420 -1090 {
@ -242,7 +240,7 @@ lab=OUT_LPF}
N 740 -920 780 -920 {
lab=OUT_LPF}
N 460 -740 460 -700 {lab=VNN}
N 460 -920 570 -920 {
N 460 -920 680 -920 {
lab=OUT}
N 780 -830 780 -810 {
lab=VSS}

25
xschem_library/examples/poweramp.sch
View File

@ -1,4 +1,4 @@
v {xschem version=3.1.0 file_version=1.2
v {xschem version=3.4.0 file_version=1.2
}
G {}
K {}
@ -102,7 +102,6 @@ T {@spice_get_voltage} 761.875 -206.09375 0 0 0.8 0.8 {layer=15
name=p14}
N 70 -1220 70 -1200 {lab=#net1}
N 70 -1080 70 -1060 {lab=#net2}
N 300 -1140 310 -1140 {lab=VSS}
N 710 -700 860 -700 {lab=OUTM}
N 500 -1150 570 -1150 {lab=VSS}
N 570 -1150 570 -1140 {lab=VSS}
@ -112,9 +111,7 @@ N 610 -1200 700 -1200 {lab=REFP}
N 260 -1070 260 -1060 {lab=VNN}
N 260 -1140 260 -1130 {lab=VSS}
N 70 -1060 100 -1060 {lab=#net2}
N 300 -1060 310 -1060 {lab=VNN}
N 70 -1220 100 -1220 {lab=#net1}
N 300 -1220 310 -1220 {lab=VPP}
N 260 -1140 270 -1140 {lab=VSS}
N 240 -1220 270 -1220 {lab=VPP}
N 240 -1060 260 -1060 {lab=VNN}
@ -157,21 +154,15 @@ N 350 -890 400 -890 {lab=FBN}
N 350 -430 400 -430 {lab=FB}
N 570 -1060 610 -1060 {lab=VSS}
N 570 -1070 570 -1060 {lab=VSS}
N 270 -1220 300 -1220 {lab=VPP}
N 260 -1060 300 -1060 {lab=VNN}
N 270 -1140 300 -1140 {lab=VSS}
N 270 -1220 310 -1220 {lab=VPP}
N 260 -1060 310 -1060 {lab=VNN}
N 270 -1140 310 -1140 {lab=VSS}
N 270 -1150 270 -1140 { lab=VSS}
N 270 -1220 270 -1210 { lab=VPP}
N 240 -730 240 -680 { lab=VSSX}
N 240 -270 240 -220 { lab=INX}
N 400 -920 400 -910 { lab=FBN}
N 400 -910 400 -890 { lab=FBN}
N 400 -460 400 -450 { lab=FB}
N 400 -450 400 -430 { lab=FB}
N 240 -780 240 -760 { lab=VSSX}
N 240 -760 240 -730 { lab=VSSX}
N 240 -320 240 -300 { lab=INX}
N 240 -300 240 -270 { lab=INX}
N 400 -920 400 -890 { lab=FBN}
N 400 -460 400 -430 { lab=FB}
N 240 -780 240 -680 { lab=VSSX}
N 240 -320 240 -220 { lab=INX}
N 160 -1220 180 -1220 {lab=#net3}
N 160 -1060 180 -1060 {lab=#net4}
N 70 -1140 180 -1140 {lab=#net5}

5
xschem_library/examples/poweramp_lcc.sch
View File

@ -1,4 +1,4 @@
v {xschem version=3.1.0 file_version=1.2
v {xschem version=3.4.0 file_version=1.2
}
G {}
K {}
@ -140,7 +140,7 @@ N 2080 -1410 2080 -1400 { lab=VPP}
N 210 -570 210 -540 { lab=FBN}
N 210 1020 210 1050 { lab=FB}
N 190 -960 190 -860 { lab=VSSX}
N 190 570 190 670 { lab=INX}
N 190 640 190 670 { lab=INX}
N 1970 -1410 1990 -1410 {lab=#net3}
N 1970 -1250 1990 -1250 {lab=#net4}
N 1880 -1330 1990 -1330 {lab=#net5}
@ -174,6 +174,7 @@ N 270 640 270 820 {
lab=INX}
N 190 640 270 640 {
lab=INX}
N 190 570 190 640 { lab=INX}
C {vsource.sym} 1880 -1360 0 0 {name=V1 value="dc 50 pwl 0 0 1m 50"}
C {vsource.sym} 1880 -1300 0 0 {name=V0 value="dc 50 pwl 0 0 1m 50"}
C {lab_pin.sym} 2120 -1410 0 1 {name=p5 lab=VPP}

4
xschem_library/examples/test_lvs_ignore.sch
View File

@ -23,7 +23,7 @@ it is used only to display the net
name it is attached to. This works if
Options->Show net names on symbol pins
is enabled.} 220 -350 0 0 0.4 0.4 {}
N 850 -430 920 -430 {
N 850 -430 1010 -430 {
lab=#net1}
N 850 -430 850 -380 {
lab=#net1}
@ -43,8 +43,6 @@ N 850 -580 850 -570 {
lab=VDD}
N 850 -510 850 -430 {
lab=#net1}
N 920 -430 1010 -430 {
lab=#net1}
N 1090 -430 1110 -430 {
lab=#net3}
N 850 -320 850 -290 {

198
xschem_library/examples/test_short_option.sch
View File

@ -5,80 +5,96 @@ K {}
V {}
S {}
E {}
L 7 920 -190 1100 -190 {}
P 4 7 320 -630 320 -550 310 -550 320 -530 330 -550 320 -550 320 -630 {}
P 4 7 640 -540 590 -540 590 -550 570 -540 590 -530 590 -540 640 -540 {}
P 4 7 950 -470 950 -380 940 -380 950 -360 960 -380 950 -380 950 -470 {}
L 7 930 -250 1110 -250 {}
P 4 7 330 -690 330 -610 320 -610 330 -590 340 -610 330 -610 330 -690 {}
P 4 7 650 -600 600 -600 600 -610 580 -600 600 -590 600 -600 650 -600 {}
T {Title symbol has embedded TCL command
to enable show_pin_net_names.} 130 -130 0 0 0.4 0.4 { layer=7}
to enable show_pin_net_names.} 160 -120 0 0 0.4 0.4 { layer=6}
T {Set tcl variable IGNORE to 1 or 0 to
enable / disable some components} 50 -940 0 0 1 1 {}
T {tcleval(IGNORE=$IGNORE)} 920 -230 0 0 0.6 0.6 {name=l1}
enable / disable / short some components} 50 -940 0 0 1 1 {}
T {tcleval(IGNORE=$IGNORE)} 930 -290 0 0 0.6 0.6 {name=l1}
T {The short component is a pass-through symbol. It can be used to short two nets.
Setting spice_ignore=true will disable the component and remove the short.} 80 -690 0 0 0.4 0.4 {}
Setting spice_ignore=true will disable the component and remove the short.} 90 -750 0 0 0.4 0.4 {}
T {This is the lab_show component
it is used only to display the net
name it is attached to. This works if
Options->Show net names on symbol pins
is enabled.} 650 -600 0 0 0.4 0.4 {}
N 120 -230 170 -230 {
is enabled.} 660 -660 0 0 0.4 0.4 {}
T {This instance has a 'spice_ignore=short'
attribute when IGNORE=0} 440 -240 0 0 0.4 0.4 { layer=6}
T {This component behaves either as
an inverter or as a short
depending on IGNORE} 1310 -540 0 0 0.4 0.4 { layer=1}
N 130 -290 180 -290 {
lab=NET_A}
N 470 -230 520 -230 {
lab=#net1}
N 170 -330 170 -230 {
lab=NET_A}
N 470 -330 470 -230 {
lab=#net1}
N 170 -330 290 -330 {
lab=NET_A}
N 350 -330 470 -330 {
lab=#net1}
N 120 -420 170 -420 {
lab=NET_C}
N 470 -420 520 -420 {
lab=NET_C}
N 170 -520 170 -420 {
lab=NET_C}
N 470 -520 470 -420 {
lab=NET_C}
N 170 -520 290 -520 {
lab=NET_C}
N 350 -520 470 -520 {
lab=NET_C}
N 370 -420 470 -420 {
lab=NET_C}
N 170 -420 290 -420 {
lab=NET_C}
N 370 -230 470 -230 {
lab=#net1}
N 170 -230 290 -230 {
lab=NET_A}
N 600 -420 650 -420 {
lab=#net2}
N 650 -400 650 -340 {
lab=#net2}
N 650 -340 740 -340 {
lab=#net2}
N 650 -300 740 -300 {
N 480 -290 530 -290 {
lab=NET_B}
N 650 -300 650 -230 {
N 180 -390 180 -290 {
lab=NET_A}
N 480 -390 480 -290 {
lab=NET_B}
N 600 -230 650 -230 {
N 180 -390 300 -390 {
lab=NET_A}
N 360 -390 480 -390 {
lab=NET_B}
N 860 -320 900 -320 {
N 160 -480 180 -480 {
lab=NET_C}
N 480 -480 530 -480 {
lab=NET_C}
N 180 -580 180 -480 {
lab=NET_C}
N 480 -580 480 -480 {
lab=NET_C}
N 180 -580 300 -580 {
lab=NET_C}
N 360 -580 480 -580 {
lab=NET_C}
N 380 -480 480 -480 {
lab=NET_C}
N 180 -480 300 -480 {
lab=NET_C}
N 380 -290 480 -290 {
lab=NET_B}
N 180 -290 300 -290 {
lab=NET_A}
N 610 -480 660 -480 {
lab=#net1}
N 660 -460 660 -400 {
lab=#net1}
N 660 -400 750 -400 {
lab=#net1}
N 660 -360 750 -360 {
lab=NET_B}
N 660 -360 660 -290 {
lab=NET_B}
N 610 -290 660 -290 {
lab=NET_B}
N 980 -380 1020 -380 {
lab=NET_E}
N 660 -460 760 -460 {
lab=#net1}
N 820 -460 980 -460 {
lab=NET_E}
N 980 -460 980 -380 {
lab=NET_E}
N 660 -480 660 -460 {
lab=#net1}
N 120 -420 160 -420 {
lab=NET_C}
N 160 -480 160 -420 {
lab=NET_C}
N 1560 -590 1680 -590 {
lab=#net2}
N 650 -400 750 -400 {
lab=#net2}
N 810 -400 860 -400 {
lab=#net2}
N 860 -400 860 -320 {
lab=#net2}
N 650 -420 650 -400 {
lab=#net2}
N 840 -320 860 -320 {
lab=#net2}
C {lab_pin.sym} 120 -230 0 0 {name=p3 sig_type=std_logic lab=NET_A}
C {iopin.sym} 80 -140 0 1 { name=p4 lab=NET_A }
N 120 -480 160 -480 {
lab=NET_C}
N 1760 -590 1820 -590 {
lab=NET_F}
N 1210 -590 1480 -590 {
lab=NET_B}
N 850 -380 980 -380 {
lab=NET_E}
C {lab_pin.sym} 130 -290 0 0 {name=p3 sig_type=std_logic lab=NET_A}
C {ipin.sym} 100 -190 0 0 { name=p4 lab=NET_D }
C {title.sym} 160 -30 0 0 {name=l1
author="tcleval([
if \{$show_pin_net_names == 0\} \{
@ -89,36 +105,37 @@ author="tcleval([
return \{Stefan Schippers\}
])"
}
C {short.sym} 320 -330 0 0 {name=x2
C {short.sym} 330 -390 0 0 {name=x2
spice_ignore="tcleval([if \{$IGNORE == 1\} \{return \{false\}\} else \{return \{true\}\}])"
}
C {lab_pin.sym} 650 -230 0 1 {name=p5 sig_type=std_logic lab=NET_B}
C {lab_show.sym} 470 -330 0 1 {name=l2 }
C {lab_pin.sym} 120 -420 0 0 {name=p1 sig_type=std_logic lab=NET_C}
C {short.sym} 320 -520 0 0 {name=x5
C {lab_pin.sym} 660 -290 0 1 {name=p5 sig_type=std_logic lab=NET_B}
C {lab_show.sym} 480 -390 0 1 {name=l2 }
C {lab_pin.sym} 60 -480 0 0 {name=p1 sig_type=std_logic lab=NET_C}
C {short.sym} 330 -580 0 0 {name=x5
spice_ignore="tcleval([if \{$IGNORE == 1\} \{return \{true\}\} else \{return \{false\}\}])"
}
C {lab_show.sym} 470 -520 0 1 {name=l3 }
C {iopin.sym} 80 -110 0 1 { name=p7 lab=NET_C }
C {lab_show.sym} 650 -420 0 1 {name=l5 }
C {inv_ngspice.sym} 560 -420 0 0 {name=x3
C {lab_show.sym} 480 -580 0 1 {name=l3 }
C {ipin.sym} 100 -170 0 0 { name=p7 lab=NET_C }
C {lab_show.sym} 660 -480 0 1 {name=l5 }
C {inv_ngspice.sym} 570 -480 0 0 {name=x3
ROUT=1000}
C {inv_ngspice.sym} 560 -230 0 0 {name=x6
ROUT=1000}
C {inv_ngspice.sym} 330 -420 0 0 {name=x7
C {inv_ngspice.sym} 570 -290 0 0 {name=x6
ROUT=1000
spice_ignore="tcleval([if \{$IGNORE == 1\} \{return \{false\}\} else \{return \{short\}\}])"}
C {inv_ngspice.sym} 340 -480 0 0 {name=x7
spice_ignore="tcleval([if \{$IGNORE == 1\} \{return \{false\}\} else \{return \{true\}\}])"
ROUT=1000}
C {inv_ngspice.sym} 330 -230 0 0 {name=x8
C {inv_ngspice.sym} 340 -290 0 0 {name=x8
spice_ignore="tcleval([if \{$IGNORE == 1\} \{return \{true\}\} else \{return \{false\}\}])"
ROUT=1000}
C {and_ngspice.sym} 780 -320 0 0 {name=x4 ROUT=1000
spice_ignore="tcleval([if \{$IGNORE == 1\} \{return \{false\}\} else \{return \{true\}\}])"
C {and_ngspice.sym} 790 -380 0 0 {name=x4 ROUT=1000
spice_ignore="tcleval([if \{$IGNORE == 0\} \{return \{false\}\} else \{return \{true\}\}])"
}
C {short.sym} 780 -400 0 0 {name=x1
spice_ignore="tcleval([if \{$IGNORE == 1\} \{return \{true\}\} else \{return \{false\}\}])"
C {short.sym} 790 -460 0 0 {name=x1
spice_ignore="tcleval([if \{$IGNORE == 0\} \{return \{true\}\} else \{return \{false\}\}])"
}
C {lab_show.sym} 900 -320 0 1 {name=l4 }
C {launcher.sym} 750 -90 0 0 {name=h1
C {lab_show.sym} 1020 -380 0 1 {name=l4 }
C {launcher.sym} 830 -100 0 0 {name=h1
descr="Toggle IGNORE variable and
rebuild connectivity"
tclcommand="
@ -130,3 +147,22 @@ if \{![info exists IGNORE]\} \{
xschem rebuild_connectivity
xschem unhilight_all
"}
C {ammeter.sym} 90 -480 3 0 {name=Vopt2
spice_ignore="tcleval([if \{$IGNORE == 1\} \{return \{true\}\} else \{return \{short\}\}])"
}
C {lab_pin.sym} 60 -420 0 0 {name=p2 sig_type=std_logic lab=NET_D}
C {ammeter.sym} 90 -420 3 0 {name=Vopt1
spice_ignore="tcleval([if \{$IGNORE == 0\} \{return \{true\}\} else \{return \{short\}\}])"
}
C {lab_show.sym} 180 -580 0 0 {name=l6 }
C {lab_wire.sym} 920 -380 0 0 {name=p6 sig_type=std_logic lab=NET_E}
C {lab_pin.sym} 1820 -590 0 1 {name=p8 sig_type=std_logic lab=NET_F}
C {inv_ngspice.sym} 1520 -590 0 0 {name=x10
ROUT=1000
spice_ignore="tcleval([if \{$IGNORE == 0\} \{return \{false\}\} else \{return \{short\}\}])"}
C {inv_ngspice.sym} 1720 -590 0 0 {name=x11
ROUT=1000}
C {lab_pin.sym} 1210 -590 0 0 {name=p9 sig_type=std_logic lab=NET_B}
C {lab_show.sym} 1590 -590 0 1 {name=l7 }
C {lab_show.sym} 1380 -590 0 1 {name=l8 }
C {ipin.sym} 100 -210 0 0 { name=p10 lab=NET_A }

8
xschem_library/ngspice/solar_panel.sch
View File

@ -254,14 +254,12 @@ N 820 -330 820 -210 {
lab=0}
N 1760 -710 1810 -710 {
lab=#net7}
N 1780 -650 1810 -650 {
lab=#net8}
N 1930 -680 2040 -680 {
lab=#net8}
N 1770 -650 1810 -650 {
lab=#net9}
N 1770 -650 1780 -650 {
lab=#net8}
N 1770 -650 1770 -520 {
lab=#net8}
lab=#net9}
C {title.sym} 160 -40 0 0 {name=l1 author="Stefan Schippers" net_name=true}
C {code_shown.sym} 170 -310 0 0 {name=CONTROL
value="tcleval(