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update example schematics

This commit is contained in:
stefan schippers 2023-10-24 00:07:36 +02:00
parent 0819211bb0
commit 4beb2d08a6
7 changed files with 17 additions and 12 deletions
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4
tests/xschemtest.tcl
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@ -190,13 +190,13 @@ proc test_xschem_simulation {{f simulate_ff.sch}} {
proc netlist_test {} {
global netlist_dir
foreach {f t h} {
rom8k.sch spice 1998661799
rom8k.sch spice 1947979332
greycnt.sch verilog 2899796185
autozero_comp.sch spice 751826850
loading.sch vhdl 2975204502
mos_power_ampli.sch spice 1986885043
hierarchical_tedax.sch tedax 998070173
LCC_instances.sch spice 268038818
LCC_instances.sch spice 1619668159
pcb_test1.sch tedax 1925087189
test_doublepin.sch spice 894741562
simulate_ff.sch spice 574849766

1
xschem_library/examples/LCC_instances.sch
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@ -118,6 +118,7 @@ write LCC_instances.raw
set appendwrite
dc v1 3 0 -0.001
write LCC_instances.raw
quit 0
.endc
"}
C {code.sym} 840 -190 0 0 {name=MODEL

7
xschem_library/examples/plot_manipulation.sch
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@ -1,4 +1,4 @@
v {xschem version=3.4.4 file_version=1.2
v {xschem version=3.4.5 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@ -108,7 +108,8 @@ C {lab_pin.sym} 630 -280 0 1 {name=p10 lab=MINUS net_name=true}
C {lab_pin.sym} 830 -360 0 1 {name=p11 lab=DIFFOUT net_name=true}
C {lab_pin.sym} 240 -230 0 0 {name=p13 lab=GN net_name=true}
C {lab_pin.sym} 30 -280 0 0 {name=p14 lab=0 net_name=true}
C {vsource.sym} 30 -310 0 0 {name=VPLUS value="2.5 pwl 0 2.4 10n 2.4 10.1n 2.6" net_name=true}
C {vsource.sym} 30 -310 0 0 {name=VPLUS value=2.5 net_name=true
}
C {lab_pin.sym} 60 -370 0 1 {name=p15 lab=PLUS net_name=true}
C {lab_pin.sym} 30 -430 0 0 {name=p16 lab=0 net_name=true}
C {vsource.sym} 30 -460 0 0 {name=V1 value=2.5 net_name=true}
@ -159,7 +160,7 @@ setscale vcc $ set as xaxis for myplot
settype voltage vcc
write plot_manipulation.raw
plot s_vec
quit 0
.endc
** ngspice

11
xschem_library/examples/tesla.sch
View File

@ -1,4 +1,4 @@
v {xschem version=3.4.4 file_version=1.2
v {xschem version=3.4.5 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@ -32,8 +32,8 @@ ypos2=2
divy=5
subdivy=1
unity=k
x1=4e-10
x2=0.001
x1=0.000952652
x2=0.000957538
divx=5
subdivx=1
node=hv
@ -49,8 +49,8 @@ ypos2=2
divy=5
subdivy=1
unity=1
x1=4e-10
x2=0.001
x1=0.000952652
x2=0.000957538
divx=5
subdivx=1
@ -174,6 +174,7 @@ tran 40n 1m uic
meas tran iavg AVG i(vvcc) from=950u to=990u
save tran p(q5) i(l1) i(l2)
write tesla.raw
quit 0
.endc
"}
C {lab_pin.sym} 140 -680 0 0 {name=p1 lab=VCC}

4
xschem_library/examples/test_bus_tap.sch
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@ -1,4 +1,4 @@
v {xschem version=3.4.4 file_version=1.2
v {xschem version=3.4.5 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@ -27,7 +27,7 @@ E {}
P 4 7 630 -290 630 -320 620 -320 630 -347.5 640 -320 630 -320 630 -290 {fill=true}
T {Specifying @lab
will result in net
@#1:net_name} 640 -310 0 0 0.4 0.4 {name=l6 layer=4}
@#0:net_name} 640 -310 0 0 0.4 0.4 {name=l6 layer=4}
T {Title symbol has embedded TCL command
to enable show_pin_net_names } 180 -110 0 0 0.4 0.4 { layer=7}
T {@#1:net_name} 1120 -1030 0 0 0.4 0.4 {name=l19 layer=4}

1
xschem_library/ngspice/delta_sigma.sch
View File

@ -114,6 +114,7 @@ value="
* save all
tran 0.2n 9u uic
write delta_sigma.raw
quit 0
.endc
"}
C {vsource.sym} 270 -540 0 1 {name=v3

1
xschem_library/rom8k/rom8k.sch
View File

@ -388,6 +388,7 @@ vvss vss 0 0
tran 0.2n 480n uic
write rom8k_ngspice.raw
acct
quit 0
.endc
** download models from here: