comments, more test_bus_tap examples
This commit is contained in:
stefan schippers
parent
487b1eb202
commit
4a06176f0d
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@ -873,9 +873,11 @@ static int instcheck(int n, int p)
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char *node_base_name = NULL;
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const char *tap;
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dbg(1, "instcheck: bus tap node: %s\n", inst[n].node[0]);
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if(!inst[n].node[1]) {
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if(!inst[n].node[1]) { /* still unnamed */
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tap = get_tok_value(inst[n].prop_ptr, "lab", 0);
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/* Check if this is a bus slice and must be appended to bus base name */
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if(tap[0] == '[' || isonlydigit(tap)) {
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/* find bus basename, from beginning or first character after ',' and ' ' */
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char *nptr = strchr(inst[n].node[0], '[');
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if(nptr) {
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while(nptr > inst[n].node[0]) {
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@ -5,171 +5,196 @@ K {}
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V {}
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S {}
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E {}
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P 4 7 740 -280 740 -310 730 -310 740 -337.5 750 -310 740 -310 740 -280 {fill=true}
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P 4 7 630 -290 630 -320 620 -320 630 -347.5 640 -320 630 -320 630 -290 {fill=true}
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T {Specifying @lab
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will result in net
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@#1:net_name} 750 -300 0 0 0.4 0.4 {name=l6 layer=4}
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@#1:net_name} 640 -310 0 0 0.4 0.4 {name=l6 layer=4}
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T {Title symbol has embedded TCL command
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to enable show_pin_net_names } 180 -110 0 0 0.4 0.4 { layer=7}
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N 280 -380 1020 -380 {bus=true
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T {@#1:net_name} 1120 -1030 0 0 0.4 0.4 {name=l19 layer=4}
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T {This label only names the
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bus radix. Do NOT attach
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components to it.
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Use a bus tap symbol.} 870 -770 0 0 0.3 0.3 {}
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N 170 -390 910 -390 {bus=true
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lab=DATA[15:0]}
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N 500 -520 500 -390 {
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N 390 -530 390 -400 {
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lab=DATA[3]}
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N 390 -520 390 -390 {
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N 280 -530 280 -400 {
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lab=DATA[13]}
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N 560 -370 560 -220 {
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N 450 -380 450 -230 {
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lab=DATA[7:4]}
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N 440 -370 440 -220 {
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N 330 -380 330 -230 {
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lab=DATA[11:8]}
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N 330 -370 330 -220 {
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N 220 -380 220 -230 {
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lab=DATA[3:0]}
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N 710 -370 710 -220 {
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N 600 -380 600 -230 {
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lab=DATA[15:12]}
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N 610 -520 610 -390 {
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N 500 -530 500 -400 {
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lab=DATA[10]}
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N 730 -520 730 -390 {
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N 620 -530 620 -400 {
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lab=DATA[0]}
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N 950 -490 950 -480 {
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N 840 -500 840 -490 {
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lab=VCC}
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N 610 -590 610 -580 {
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N 500 -600 500 -590 {
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lab=VCC}
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N 500 -590 500 -580 {
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N 390 -600 390 -590 {
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lab=VCC}
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N 390 -590 390 -580 {
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N 280 -600 280 -590 {
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lab=VCC}
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N 330 -160 330 -150 {
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N 220 -170 220 -160 {
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lab=VSS}
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N 440 -160 440 -150 {
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N 330 -170 330 -160 {
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lab=VSS}
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N 560 -160 560 -150 {
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N 450 -170 450 -160 {
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lab=VSS}
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N 710 -160 710 -150 {
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N 600 -170 600 -160 {
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lab=VSS}
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N 300 -440 300 -380 {
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N 190 -450 190 -390 {
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lab=DATA[15:0]}
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N 300 -510 300 -500 {
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N 190 -520 190 -510 {
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lab=VCC}
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N 950 -420 950 -380 {
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N 840 -430 840 -390 {
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lab=DATA[15:0]}
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N 280 -780 940 -780 {bus=true
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N 170 -790 720 -790 {bus=true
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lab=DIN[15..0]}
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N 390 -770 390 -710 {
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lab=0}
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N 610 -770 610 -710 {
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N 280 -780 280 -720 {
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lab=DIN0}
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N 500 -780 500 -720 {
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lab=DIN[4..1]}
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N 390 -650 390 -630 {
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N 280 -660 280 -640 {
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lab=VSS}
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N 610 -650 610 -630 {
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N 500 -660 500 -640 {
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lab=VSS}
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N 810 -770 810 -710 {
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lab=5}
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N 810 -650 810 -630 {
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N 700 -780 700 -720 {
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lab=DIN5}
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N 700 -660 700 -640 {
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lab=VSS}
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N 280 -970 940 -970 {bus=true
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N 230 -980 720 -980 {bus=true
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lab="CK , S1, ADD[3:0],ENAB"}
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N 390 -960 390 -900 {
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N 280 -970 280 -910 {
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lab=ADD[3:0]}
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N 610 -960 610 -900 {
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N 500 -970 500 -910 {
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lab=ENAB}
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N 390 -840 390 -820 {
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N 280 -850 280 -830 {
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lab=VSS}
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N 610 -840 610 -820 {
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N 500 -850 500 -830 {
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lab=VSS}
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N 810 -960 810 -900 {
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N 700 -970 700 -910 {
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lab=CK}
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N 810 -840 810 -820 {
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N 700 -850 700 -830 {
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lab=VSS}
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C {bus_tap.sym} 510 -380 3 0 {name=l1 lab=[3]
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N 980 -790 1640 -790 {bus=true
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lab=DOUT}
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N 1140 -780 1140 -720 {
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lab=DOUT[0]}
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N 1310 -780 1310 -720 {
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lab=DOUT[7:1]}
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N 1140 -660 1140 -640 {
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lab=VSS}
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N 1310 -660 1310 -640 {
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lab=VSS}
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N 1510 -780 1510 -720 {
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lab=DOUT[15:8]}
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N 1510 -660 1510 -640 {
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lab=VSS}
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N 980 -1170 1090 -1170 {
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lab=DOUT[15:0]}
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N 1090 -1170 1110 -1170 {
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lab=DOUT[15:0]}
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N 1110 -1170 1110 -800 {
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lab=DOUT[15:0]}
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C {bus_tap.sym} 400 -390 3 0 {name=l1 lab=[3]
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net_name=true}
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C {bus_tap.sym} 400 -380 3 0 {name=l2 lab=[13]
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C {bus_tap.sym} 290 -390 3 0 {name=l2 lab=[13]
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net_name=true}
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C {bus_tap.sym} 550 -380 1 0 {name=l3 lab=[7:4]
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C {bus_tap.sym} 440 -390 1 0 {name=l3 lab=[7:4]
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net_name=true}
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C {bus_tap.sym} 430 -380 1 0 {name=l4 lab=[11:8]
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C {bus_tap.sym} 320 -390 1 0 {name=l4 lab=[11:8]
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net_name=true}
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C {bus_tap.sym} 320 -380 1 0 {name=l5 lab=[3:0]
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C {bus_tap.sym} 210 -390 1 0 {name=l5 lab=[3:0]
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net_name=true}
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C {bus_tap.sym} 620 -380 3 0 {name=l7 lab=[10]
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C {bus_tap.sym} 510 -390 3 0 {name=l7 lab=[10]
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net_name=true}
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C {bus_tap.sym} 740 -380 3 0 {name=l8 lab=[0]
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C {bus_tap.sym} 630 -390 3 0 {name=l8 lab=[0]
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net_name=true}
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C {res.sym} 730 -550 0 0 {name=R1
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C {res.sym} 620 -560 0 0 {name=R1
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value=1k
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footprint=1206
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device=resistor
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m=1
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net_name=true}
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C {res.sym} 610 -550 0 0 {name=R2
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C {res.sym} 500 -560 0 0 {name=R2
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value=1k
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footprint=1206
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device=resistor
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m=1
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net_name=true}
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C {res.sym} 500 -550 0 0 {name=R3
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C {res.sym} 390 -560 0 0 {name=R3
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value=1k
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footprint=1206
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device=resistor
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m=1
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net_name=true}
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C {res.sym} 390 -550 0 0 {name=R4
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C {res.sym} 280 -560 0 0 {name=R4
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value=1k
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footprint=1206
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device=resistor
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m=1
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net_name=true}
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C {res.sym} 330 -190 0 0 {name=R5[3:0]
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C {res.sym} 220 -200 0 0 {name=R5[3:0]
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value=1k
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footprint=1206
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device=resistor
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m=1
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net_name=true}
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C {res.sym} 440 -190 0 0 {name=R6[3:0]
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C {res.sym} 330 -200 0 0 {name=R6[3:0]
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value=1k
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footprint=1206
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device=resistor
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m=1
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net_name=true}
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C {res.sym} 560 -190 0 0 {name=R7[3:0]
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C {res.sym} 450 -200 0 0 {name=R7[3:0]
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value=1k
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footprint=1206
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device=resistor
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m=1
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net_name=true}
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C {res.sym} 710 -190 0 0 {name=R8[3:0]
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C {res.sym} 600 -200 0 0 {name=R8[3:0]
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value=1k
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footprint=1206
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device=resistor
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m=1
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net_name=true}
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C {lab_pin.sym} 300 -510 0 0 {name=p10 sig_type=std_logic lab=VCC
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C {lab_pin.sym} 190 -520 0 0 {name=p10 sig_type=std_logic lab=VCC
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}
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C {bus_tap.sym} 700 -380 1 0 {name=l6 lab=[15:12]
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C {bus_tap.sym} 590 -390 1 0 {name=l6 lab=[15:12]
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net_name=true}
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C {lab_pin.sym} 390 -590 0 0 {name=p2 sig_type=std_logic lab=VCC
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C {lab_pin.sym} 280 -600 0 0 {name=p2 sig_type=std_logic lab=VCC
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}
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C {lab_pin.sym} 500 -590 0 0 {name=p3 sig_type=std_logic lab=VCC
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C {lab_pin.sym} 390 -600 0 0 {name=p3 sig_type=std_logic lab=VCC
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}
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C {lab_pin.sym} 610 -590 0 0 {name=p4 sig_type=std_logic lab=VCC
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C {lab_pin.sym} 500 -600 0 0 {name=p4 sig_type=std_logic lab=VCC
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}
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C {lab_pin.sym} 950 -490 0 0 {name=p5 sig_type=std_logic lab=VCC
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C {lab_pin.sym} 840 -500 0 0 {name=p5 sig_type=std_logic lab=VCC
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}
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C {lab_pin.sym} 330 -150 0 0 {name=p6 sig_type=std_logic lab=VSS
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C {lab_pin.sym} 220 -160 0 0 {name=p6 sig_type=std_logic lab=VSS
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}
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C {lab_pin.sym} 440 -150 0 0 {name=p7 sig_type=std_logic lab=VSS
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C {lab_pin.sym} 330 -160 0 0 {name=p7 sig_type=std_logic lab=VSS
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}
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C {lab_pin.sym} 560 -150 0 0 {name=p8 sig_type=std_logic lab=VSS
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C {lab_pin.sym} 450 -160 0 0 {name=p8 sig_type=std_logic lab=VSS
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}
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C {lab_pin.sym} 710 -150 0 0 {name=p9 sig_type=std_logic lab=VSS
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C {lab_pin.sym} 600 -160 0 0 {name=p9 sig_type=std_logic lab=VSS
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}
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C {res.sym} 300 -470 0 0 {name=R9[15:0]
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C {res.sym} 190 -480 0 0 {name=R9[15:0]
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value=1k
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footprint=1206
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device=resistor
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m=1
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net_name=true}
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C {lab_pin.sym} 280 -380 0 0 {name=p1 sig_type=std_logic lab=DATA[15:0]
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C {lab_pin.sym} 170 -390 0 0 {name=p1 sig_type=std_logic lab=DATA[15:0]
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}
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C {res.sym} 950 -450 0 0 {name=R10[15:0]
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C {res.sym} 840 -460 0 0 {name=R10[15:0]
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value=1k
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footprint=1206
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device=resistor
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@ -183,67 +208,109 @@ author="tcleval(Stefan Schippers[
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xschem update_all_sym_bboxes
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\}]
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)"}
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C {lab_pin.sym} 280 -780 0 0 {name=p11 sig_type=std_logic lab=DIN[15..0]
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C {lab_pin.sym} 170 -790 0 0 {name=p11 sig_type=std_logic lab=DIN[15..0]
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}
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C {bus_tap.sym} 380 -780 1 0 {name=l10 lab=0
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C {bus_tap.sym} 270 -790 1 0 {name=l10 lab=0
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net_name=true}
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C {bus_tap.sym} 600 -780 1 0 {name=l11 lab=[4..1]
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C {bus_tap.sym} 490 -790 1 0 {name=l11 lab=[4..1]
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net_name=true}
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C {res.sym} 610 -680 0 0 {name=R11[3:0]
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C {res.sym} 500 -690 0 0 {name=R11[3:0]
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value=1k
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footprint=1206
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device=resistor
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m=1
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net_name=true}
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C {res.sym} 390 -680 0 0 {name=R12
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C {res.sym} 280 -690 0 0 {name=R12
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value=1k
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footprint=1206
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device=resistor
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m=1
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net_name=true}
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C {lab_pin.sym} 390 -630 0 0 {name=p12 sig_type=std_logic lab=VSS
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C {lab_pin.sym} 280 -640 0 0 {name=p12 sig_type=std_logic lab=VSS
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}
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C {lab_pin.sym} 610 -630 0 0 {name=p13 sig_type=std_logic lab=VSS
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C {lab_pin.sym} 500 -640 0 0 {name=p13 sig_type=std_logic lab=VSS
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}
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C {bus_tap.sym} 800 -780 1 0 {name=l12 lab=5
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C {bus_tap.sym} 690 -790 1 0 {name=l12 lab=5
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net_name=true}
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C {res.sym} 810 -680 0 0 {name=R13
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C {res.sym} 700 -690 0 0 {name=R13
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value=1k
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footprint=1206
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device=resistor
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m=1
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net_name=true}
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C {lab_pin.sym} 810 -630 0 0 {name=p14 sig_type=std_logic lab=VSS
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C {lab_pin.sym} 700 -640 0 0 {name=p14 sig_type=std_logic lab=VSS
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}
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C {lab_pin.sym} 280 -970 0 0 {name=p15 sig_type=std_logic lab="CK , S1, ADD[3:0],ENAB"
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C {lab_pin.sym} 230 -980 0 0 {name=p15 sig_type=std_logic lab="CK , S1, ADD[3:0],ENAB"
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}
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C {bus_tap.sym} 380 -970 1 0 {name=l13 lab=[3:0]
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C {bus_tap.sym} 270 -980 1 0 {name=l13 lab=[3:0]
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net_name=true}
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C {bus_tap.sym} 600 -970 1 0 {name=l14 lab=ENAB
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C {bus_tap.sym} 490 -980 1 0 {name=l14 lab=ENAB
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net_name=true}
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C {res.sym} 610 -870 0 0 {name=R1[3:0]
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C {res.sym} 500 -880 0 0 {name=R15[3:0]
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value=1k
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footprint=1206
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device=resistor
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m=1
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net_name=true}
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C {res.sym} 390 -870 0 0 {name=R5
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C {res.sym} 280 -880 0 0 {name=R14
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value=1k
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footprint=1206
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device=resistor
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m=1
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net_name=true}
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C {lab_pin.sym} 390 -820 0 0 {name=p16 sig_type=std_logic lab=VSS
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C {lab_pin.sym} 280 -830 0 0 {name=p16 sig_type=std_logic lab=VSS
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}
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C {lab_pin.sym} 610 -820 0 0 {name=p17 sig_type=std_logic lab=VSS
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C {lab_pin.sym} 500 -830 0 0 {name=p17 sig_type=std_logic lab=VSS
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}
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C {bus_tap.sym} 800 -970 1 0 {name=l15 lab=CK
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C {bus_tap.sym} 690 -980 1 0 {name=l15 lab=CK
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net_name=true}
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C {res.sym} 810 -870 0 0 {name=R6
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C {res.sym} 700 -880 0 0 {name=R16
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value=1k
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footprint=1206
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device=resistor
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m=1
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net_name=true}
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C {lab_pin.sym} 810 -820 0 0 {name=p18 sig_type=std_logic lab=VSS
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C {lab_pin.sym} 700 -830 0 0 {name=p18 sig_type=std_logic lab=VSS
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}
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C {lab_pin.sym} 980 -790 0 0 {name=p19 sig_type=std_logic lab=DOUT
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}
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C {bus_tap.sym} 1130 -790 1 0 {name=l16 lab=[0]
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net_name=true}
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C {bus_tap.sym} 1300 -790 1 0 {name=l17 lab=[7:1]
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net_name=true}
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C {res.sym} 1310 -690 0 0 {name=R18[6:0]
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value=1k
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footprint=1206
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device=resistor
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m=1
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net_name=true}
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C {res.sym} 1140 -690 0 0 {name=R17
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value=1k
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footprint=1206
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device=resistor
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m=1
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net_name=true}
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C {lab_pin.sym} 1140 -640 0 0 {name=p20 sig_type=std_logic lab=VSS
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}
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C {lab_pin.sym} 1310 -640 0 0 {name=p21 sig_type=std_logic lab=VSS
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}
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C {bus_tap.sym} 1500 -790 1 0 {name=l18 lab=[15:8]
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net_name=true}
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C {res.sym} 1510 -690 0 0 {name=R19[7:0]
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value=1k
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footprint=1206
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device=resistor
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m=1
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net_name=true}
|
||||
C {lab_pin.sym} 1510 -640 0 0 {name=p22 sig_type=std_logic lab=VSS
|
||||
}
|
||||
C {rom2_sa.sym} 830 -1110 0 0 {name=xsa[15:0]}
|
||||
C {lab_pin.sym} 680 -1170 0 0 {name=p24 lab=LDCP}
|
||||
C {lab_pin.sym} 680 -1150 0 0 {name=p25 lab=LDYMS}
|
||||
C {lab_pin.sym} 680 -1130 0 0 {name=p26 lab=LDOE}
|
||||
C {lab_pin.sym} 680 -1110 0 0 {name=p27 lab=LDPRECH}
|
||||
C {lab_pin.sym} 680 -1090 0 0 {name=p28 lab=LDSAL}
|
||||
C {lab_pin.sym} 680 -1070 0 0 {name=p29 lab=vcc}
|
||||
C {lab_pin.sym} 680 -1050 0 0 {name=p30 lab=vss}
|
||||
C {bus_tap.sym} 1120 -790 3 0 {name=l19 lab=[15:0]
|
||||
net_name=true}
|
||||
|
|
|
|||
Loading…
Reference in New Issue