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when a bus label is edited correctly propagate list of instances to be redrawn if show net names on components is enabled (ie: propagate thru bus taps)

This commit is contained in:
stefan schippers 2023-05-22 07:28:12 +02:00
parent a4d5ddb63f
commit b68dd8c099
2 changed files with 84 additions and 43 deletions
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19
src/move.c
View File

@ -513,7 +513,13 @@ void find_inst_to_be_redrawn(int what)
int p;
char *type=xctx->sym[xctx->inst[n].ptr].type;
/* collect all nodes connected to instances that set node names */
if(type && IS_LABEL_OR_PIN(type)) {
if(type &&
(
IS_LABEL_OR_PIN(type) ||
/* bus taps */
(!strcmp(type, "show_label") && (inst[n].ptr + xctx->sym)->rects[PINLAYER] == 2)
)
) {
for(p = 0; p < (inst[n].ptr + xctx->sym)->rects[PINLAYER]; p++) {
if( inst[n].node && inst[n].node[p]) {
dbg(1,"find_inst_to_be_redrawn(): hashing inst %s, node %s\n", inst[n].instname, inst[n].node[p]);
@ -527,6 +533,17 @@ void find_inst_to_be_redrawn(int what)
int_hash_lookup(&xctx->node_redraw_table, xctx->wire[n].node, 0, XINSERT_NOREPLACE);
}
}
/* propagate all node[1] of bus taps that have node[0] hashed above */
for(i=0; i < xctx->instances; ++i) {
char *type=xctx->sym[xctx->inst[i].ptr].type;
/* bus taps */
if(type && !strcmp(type, "show_label") && (inst[i].ptr + xctx->sym)->rects[PINLAYER] == 2 ) {
if(int_hash_lookup(&xctx->node_redraw_table, xctx->inst[i].node[0], 0, XLOOKUP)) {
int_hash_lookup(&xctx->node_redraw_table, xctx->inst[i].node[1], 0, XINSERT_NOREPLACE);
dbg(0, "bus_tap: propagate %s\n", xctx->inst[i].node[1]);
}
}
}
} /* if(!(what & 8)) */
if(!xctx->inst_redraw_table || xctx->instances > xctx->inst_redraw_table_size) {

108
xschem_library/examples/test_bus_tap.sch
View File

@ -7,88 +7,121 @@ S {}
E {}
N 140 -300 880 -300 {bus=true
lab=DATA[15:0]}
N 360 -410 360 -310 {
N 360 -490 360 -310 {
lab=DATA[3]}
N 250 -410 250 -310 {
lab=DATA[4]}
N 420 -290 420 -210 {
N 250 -490 250 -310 {
lab=DATA[13]}
N 420 -290 420 -100 {
lab=DATA[7:4]}
N 300 -290 300 -210 {
N 300 -290 300 -100 {
lab=DATA[11:8]}
N 190 -290 190 -210 {
N 190 -290 190 -100 {
lab=DATA[3:0]}
N 570 -290 570 -210 {
N 570 -290 570 -100 {
lab=DATA[15:12]}
N 470 -410 470 -310 {
N 470 -490 470 -310 {
lab=DATA[10]}
N 590 -410 590 -310 {
N 590 -490 590 -310 {
lab=DATA[0]}
N 590 -480 590 -470 {
N 590 -560 590 -550 {
lab=VCC}
N 470 -480 470 -470 {
N 470 -560 470 -550 {
lab=VCC}
N 360 -480 360 -470 {
N 360 -560 360 -550 {
lab=VCC}
N 250 -480 250 -470 {
N 250 -560 250 -550 {
lab=VCC}
N 190 -150 190 -140 {
N 190 -40 190 -30 {
lab=VSS}
N 300 -150 300 -140 {
N 300 -40 300 -30 {
lab=VSS}
N 420 -150 420 -140 {
N 420 -40 420 -30 {
lab=VSS}
N 570 -150 570 -140 {
N 570 -40 570 -30 {
lab=VSS}
N 160 -410 160 -300 {
lab=DATA[15:0]}
N 160 -480 160 -470 {
lab=VCC}
N 810 -150 810 -140 {
lab=VSS}
N 810 -300 810 -210 {
lab=DATA[15:0]}
C {bus_tap.sym} 370 -300 3 0 {name=l1 lab=[3]}
C {bus_tap.sym} 260 -300 3 0 {name=l2 lab=[4]}
C {bus_tap.sym} 260 -300 3 0 {name=l2 lab=[13]}
C {bus_tap.sym} 410 -300 1 0 {name=l3 lab=[7:4]}
C {bus_tap.sym} 290 -300 1 0 {name=l4 lab=[11:8]}
C {bus_tap.sym} 180 -300 1 0 {name=l5 lab=[3:0]}
C {bus_tap.sym} 480 -300 3 0 {name=l7 lab=[10]}
C {bus_tap.sym} 600 -300 3 0 {name=l8 lab=[0]}
C {res.sym} 590 -440 0 0 {name=R1
C {res.sym} 590 -520 0 0 {name=R1
value=1k
footprint=1206
device=resistor
m=1
net_name=true}
C {res.sym} 470 -440 0 0 {name=R2
C {res.sym} 470 -520 0 0 {name=R2
value=1k
footprint=1206
device=resistor
m=1
net_name=true}
C {res.sym} 360 -440 0 0 {name=R3
C {res.sym} 360 -520 0 0 {name=R3
value=1k
footprint=1206
device=resistor
m=1
net_name=true}
C {res.sym} 250 -440 0 0 {name=R4
C {res.sym} 250 -520 0 0 {name=R4
value=1k
footprint=1206
device=resistor
m=1
net_name=true}
C {res.sym} 190 -180 0 0 {name=R5[3:0]
C {res.sym} 190 -70 0 0 {name=R5[3:0]
value=1k
footprint=1206
device=resistor
m=1
net_name=true}
C {res.sym} 300 -180 0 0 {name=R6[3:0]
C {res.sym} 300 -70 0 0 {name=R6[3:0]
value=1k
footprint=1206
device=resistor
m=1
net_name=true}
C {res.sym} 420 -180 0 0 {name=R7[3:0]
C {res.sym} 420 -70 0 0 {name=R7[3:0]
value=1k
footprint=1206
device=resistor
m=1
net_name=true}
C {res.sym} 570 -180 0 0 {name=R8[3:0]
C {res.sym} 570 -70 0 0 {name=R8[3:0]
value=1k
footprint=1206
device=resistor
m=1
net_name=true}
C {lab_pin.sym} 160 -480 0 0 {name=p10 sig_type=std_logic lab=VCC
}
C {bus_tap.sym} 560 -300 1 0 {name=l6 lab=[15:12]}
C {lab_pin.sym} 250 -560 0 0 {name=p2 sig_type=std_logic lab=VCC
}
C {lab_pin.sym} 360 -560 0 0 {name=p3 sig_type=std_logic lab=VCC
}
C {lab_pin.sym} 470 -560 0 0 {name=p4 sig_type=std_logic lab=VCC
}
C {lab_pin.sym} 590 -560 0 0 {name=p5 sig_type=std_logic lab=VCC
}
C {lab_pin.sym} 190 -30 0 0 {name=p6 sig_type=std_logic lab=VSS
}
C {lab_pin.sym} 300 -30 0 0 {name=p7 sig_type=std_logic lab=VSS
}
C {lab_pin.sym} 420 -30 0 0 {name=p8 sig_type=std_logic lab=VSS
}
C {lab_pin.sym} 570 -30 0 0 {name=p9 sig_type=std_logic lab=VSS
}
C {res.sym} 160 -440 0 0 {name=R9[15:0]
value=1k
footprint=1206
device=resistor
@ -96,20 +129,11 @@ m=1
net_name=true}
C {lab_pin.sym} 140 -300 0 0 {name=p1 sig_type=std_logic lab=DATA[15:0]
}
C {bus_tap.sym} 560 -300 1 0 {name=l6 lab=[15:12]}
C {lab_pin.sym} 250 -480 0 0 {name=p2 sig_type=std_logic lab=VCC
}
C {lab_pin.sym} 360 -480 0 0 {name=p3 sig_type=std_logic lab=VCC
}
C {lab_pin.sym} 470 -480 0 0 {name=p4 sig_type=std_logic lab=VCC
}
C {lab_pin.sym} 590 -480 0 0 {name=p5 sig_type=std_logic lab=VCC
}
C {lab_pin.sym} 190 -140 0 0 {name=p6 sig_type=std_logic lab=VSS
}
C {lab_pin.sym} 300 -140 0 0 {name=p7 sig_type=std_logic lab=VSS
}
C {lab_pin.sym} 420 -140 0 0 {name=p8 sig_type=std_logic lab=VSS
}
C {lab_pin.sym} 570 -140 0 0 {name=p9 sig_type=std_logic lab=VSS
C {lab_pin.sym} 810 -140 0 0 {name=p11 sig_type=std_logic lab=VSS
}
C {res.sym} 810 -180 0 0 {name=R10[15:0]
value=1k
footprint=1206
device=resistor
m=1
net_name=true}