schematic example updates

This commit is contained in:
stefan schippers 2023-10-24 10:29:39 +02:00
parent 4beb2d08a6
commit 8c10ecb8b7
3 changed files with 10 additions and 4 deletions

View File

@ -1,4 +1,4 @@
v {xschem version=3.4.4 file_version=1.2
v {xschem version=3.4.5 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@ -42,7 +42,6 @@ C {ipin.sym} 210 -190 0 0 {name=p3 lab=B}
C {opin.sym} 810 -250 0 0 {name=p4 lab=Z}
C {ipin.sym} 330 -150 0 0 {name=p5 lab=RST}
C {ipin.sym} 360 -240 0 0 {name=p7 lab=CK}
C {noconn.sym} 810 -250 2 1 {name=l6}
C {use.sym} 380 -480 0 0 {------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

View File

@ -1,4 +1,4 @@
v {xschem version=3.4.4 file_version=1.2
v {xschem version=3.4.5 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@ -33,6 +33,7 @@ end if ;
end process ;
}
K {}
V {reg iQ;
always @( D or G or RST) begin
@ -61,3 +62,8 @@ C {ipin.sym} 120 -440 0 0 {name=p14 lab=RST}
C {opin.sym} 280 -440 0 0 {name=p1 lab=QN}
C {title.sym} 160 -30 0 0 {name=l17}
C {ipin.sym} 120 -380 0 0 {name=p3 lab=D}
C {noconn.sym} 280 -320 2 1 {name=l4}
C {noconn.sym} 280 -440 2 1 {name=l1}
C {noconn.sym} 120 -440 2 0 {name=l2}
C {noconn.sym} 120 -380 2 0 {name=l3}
C {noconn.sym} 120 -320 2 0 {name=l5}

View File

@ -1,4 +1,4 @@
v {xschem version=3.4.4 file_version=1.2
v {xschem version=3.4.5 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@ -55,6 +55,7 @@ T {position the mouse close to one of the curves
and press 't' to display only that curve.
This allows you to annotate the active
waveform in the schematic.} 480 -370 0 0 0.3 0.3 {}
T {tcleval(SUN=[expr \{[xschem getprop rect 2 0 dataset] == -1 ? \{N/A\} : ([xschem getprop rect 2 0 dataset] + 1)*20\}]%)} 710 -460 0 0 0.4 0.4 {name=xxxx}
N 430 -480 430 -420 {
lab=minus}
N 430 -570 430 -540 {