schematic example updates
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@ -1,4 +1,4 @@
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v {xschem version=3.4.4 file_version=1.2
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v {xschem version=3.4.5 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -42,7 +42,6 @@ C {ipin.sym} 210 -190 0 0 {name=p3 lab=B}
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C {opin.sym} 810 -250 0 0 {name=p4 lab=Z}
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C {ipin.sym} 330 -150 0 0 {name=p5 lab=RST}
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C {ipin.sym} 360 -240 0 0 {name=p7 lab=CK}
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C {noconn.sym} 810 -250 2 1 {name=l6}
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C {use.sym} 380 -480 0 0 {------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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@ -1,4 +1,4 @@
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v {xschem version=3.4.4 file_version=1.2
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v {xschem version=3.4.5 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -33,6 +33,7 @@ end if ;
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end process ;
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}
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K {}
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V {reg iQ;
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always @( D or G or RST) begin
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@ -61,3 +62,8 @@ C {ipin.sym} 120 -440 0 0 {name=p14 lab=RST}
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C {opin.sym} 280 -440 0 0 {name=p1 lab=QN}
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C {title.sym} 160 -30 0 0 {name=l17}
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C {ipin.sym} 120 -380 0 0 {name=p3 lab=D}
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C {noconn.sym} 280 -320 2 1 {name=l4}
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C {noconn.sym} 280 -440 2 1 {name=l1}
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C {noconn.sym} 120 -440 2 0 {name=l2}
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C {noconn.sym} 120 -380 2 0 {name=l3}
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C {noconn.sym} 120 -320 2 0 {name=l5}
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@ -1,4 +1,4 @@
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v {xschem version=3.4.4 file_version=1.2
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v {xschem version=3.4.5 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -55,6 +55,7 @@ T {position the mouse close to one of the curves
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and press 't' to display only that curve.
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This allows you to annotate the active
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waveform in the schematic.} 480 -370 0 0 0.3 0.3 {}
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T {tcleval(SUN=[expr \{[xschem getprop rect 2 0 dataset] == -1 ? \{N/A\} : ([xschem getprop rect 2 0 dataset] + 1)*20\}]%)} 710 -460 0 0 0.4 0.4 {name=xxxx}
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N 430 -480 430 -420 {
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lab=minus}
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N 430 -570 430 -540 {
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