when doing spice netlisting if top level has a symbol (and the symbol has i/o ports) use the symbol for printing the top level subckt port list. This ensures same port ordering when netlisting a testbench containing a component and netlisting the component itself. Tab context menu: open Symbol / open Schematic will use the search_schematic setting and search counterpart accordingly.
This commit is contained in:
stefan schippers
parent
5117001a9c
commit
a50bfb3622
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@ -245,6 +245,9 @@ int global_spice_netlist(int global) /* netlister driver */
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Str_hashentry *model_entry;
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int lvs_ignore = tclgetboolvar("lvs_ignore");
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int save_prev_mod = xctx->prev_set_modify;
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struct stat buf;
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char *top_symbol_name = NULL;
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int found_top_symbol = 0; /* if top level has a symbol use it for pin ordering */
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split_f = tclgetboolvar("split_files");
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dbg(1, "global_spice_netlist(): invoking push_undo()\n");
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@ -310,20 +313,29 @@ int global_spice_netlist(int global) /* netlister driver */
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fprintf(fd,".subckt %s", get_cell(xctx->sch[xctx->currsch], 0));
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/* print top subckt ipin/opins */
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for(i=0;i<xctx->instances; ++i) {
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if(skip_instance(i, 1, lvs_ignore)) continue;
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my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
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dbg(1, "global_spice_netlist(): |%s|\n", type);
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/*
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if( type && !strcmp(type,"netlist_options") ) {
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continue;
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}
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*/
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if( type && IS_PIN(type)) {
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str_tmp = expandlabel ( (xctx->inst[i].lab ? xctx->inst[i].lab : ""), &multip);
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/*must handle invalid node names */
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fprintf(fd, " %s", str_tmp ? str_tmp : "(NULL)" );
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}
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my_strdup2(_ALLOC_ID_, &top_symbol_name, abs_sym_path(add_ext(xctx->current_name, ".sym"), ""));
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if(!stat(top_symbol_name, &buf)) { /* if top level has a symbol use the symbol for pin ordering */
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dbg(1, "found top level symbol %s\n", top_symbol_name);
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load_sym_def(top_symbol_name, NULL);
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/* only use the symbol if it has pins */
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if(xctx->sym[xctx->symbols - 1].rects[PINLAYER] > 0) {
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fprintf(fd," ");
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print_spice_subckt_nodes(fd, xctx->symbols - 1);
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found_top_symbol = 1;
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}
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remove_symbol(xctx->symbols - 1);
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my_free(_ALLOC_ID_, &top_symbol_name);
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}
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if(!found_top_symbol) {
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for(i=0;i<xctx->instances; ++i) {
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if(skip_instance(i, 1, lvs_ignore)) continue;
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my_strdup(_ALLOC_ID_, &type,(xctx->inst[i].ptr+ xctx->sym)->type);
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if( type && IS_PIN(type)) {
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str_tmp = expandlabel ( (xctx->inst[i].lab ? xctx->inst[i].lab : ""), &multip);
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/*must handle invalid node names */
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fprintf(fd, " %s", str_tmp ? str_tmp : "(NULL)" );
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}
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}
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}
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fprintf(fd,"\n");
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@ -5897,7 +5897,7 @@ proc tab_ctx_cmd {tab_but what} {
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# puts $filename
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}
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proc tab_context_menu {tab_but} {
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global retval
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global retval search_schematic
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# find filename associated with tab button
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@ -5917,11 +5917,19 @@ proc tab_context_menu {tab_but} {
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xschem new_schematic switch $old {} 0 ;# no draw
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if {$filetype ne {symbol}} {
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set counterpart [abs_sym_path $filename .sym]
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if {$search_schematic == 1} {
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set counterpart [abs_sym_path [xschem get current_name] {.sym}]
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} else {
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set counterpart [abs_sym_path $filename .sym]
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}
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set msg {Open symbol}
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set img CtxmenuSymbol
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} else {
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set counterpart [abs_sym_path $filename .sch]
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if {$search_schematic == 1} {
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set counterpart [abs_sym_path [xschem get current_name] {.sch}]
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} else {
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set counterpart [abs_sym_path $filename .sch]
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}
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set msg {Open schematic}
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set img CtxmenuSchematic
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}
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@ -197,7 +197,7 @@ proc netlist_test {} {
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inst_sch_select.sch spice 801962545
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test_bus_tap.sch spice 181420586
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loading.sch vhdl 2975204502
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mos_power_ampli.sch spice 2027301758
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mos_power_ampli.sch spice 4084823731
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hierarchical_tedax.sch tedax 998070173
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LCC_instances.sch spice 696885230
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pcb_test1.sch tedax 1925087189
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@ -137,11 +137,11 @@ N 690 -1210 690 -970 {lab=VBOOST}
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N 690 -910 690 -900 {lab=B1}
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N 260 -550 260 -540 {lab=E9}
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N 150 -180 260 -180 {lab=VSS}
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N 40 -300 220 -300 {lab=B3}
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N 50 -300 220 -300 {lab=B3}
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N 260 -270 260 -240 {lab=E3}
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N 150 -240 150 -180 {lab=VSS}
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N 40 -210 40 -180 {lab=VSS}
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N 40 -180 150 -180 {lab=VSS}
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N 50 -240 50 -180 {lab=VSS}
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N 50 -180 150 -180 {lab=VSS}
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N 690 -690 1110 -690 {lab=OUTI}
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N 180 -550 260 -550 {lab=E9}
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N 1110 -700 1110 -690 {lab=OUTI}
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@ -153,6 +153,7 @@ N 1110 -820 1110 -790 {lab=SA}
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N 860 -850 1070 -850 {lab=GA}
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N 340 -830 340 -780 {lab=C2}
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N 340 -720 340 -650 {lab=C9}
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N 220 -720 340 -720 {lab=C9}
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N 180 -690 180 -650 {lab=C5}
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N 1330 -680 1390 -680 {lab=OUT}
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N 1110 -680 1240 -680 {lab=OUTI}
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@ -183,7 +184,7 @@ N 340 -1270 560 -1270 {lab=VPP}
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N 1110 -1270 1110 -880 { lab=VPP}
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N 560 -1270 1110 -1270 {lab=VPP}
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N 230 -1040 800 -1040 { lab=#net2}
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N 0 -180 40 -180 {
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N 0 -180 50 -180 {
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lab=VSS}
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N 0 -140 1110 -140 {
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lab=VNN}
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@ -196,14 +197,6 @@ N 400 -620 400 -570 {
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lab=MINUS}
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N 380 -620 400 -620 {
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lab=MINUS}
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N 300 -720 340 -720 {
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lab=C9}
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N 220 -720 240 -720 {
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lab=#net8}
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N 40 -300 40 -270 {
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lab=B3}
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N 150 -400 150 -360 {
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lab=VPP}
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C {ipin.sym} 0 -620 0 0 {name=p0 lab=PLUS}
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C {ipin.sym} 0 -140 0 0 {name=p3 lab=VNN}
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C {nmos3.sym} 1090 -530 0 0 {name=xm2 model=irf540 m=1
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@ -294,9 +287,9 @@ url="http://www.futurlec.com/Datasheet/Diodes/1N746-1N759.pdf"
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net_name=true}
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C {npn.sym} 240 -300 0 0 {name=Q3 model=q2n2222 area=1 net_name=true}
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C {res.sym} 150 -330 0 1 {name=R1 m=1 value=10k net_name=true}
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C {lab_pin.sym} 150 -400 0 0 {name=p7 lab=VPP}
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C {lab_pin.sym} 150 -360 0 0 {name=p7 lab=VPP}
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C {res.sym} 260 -210 0 1 {name=R10 m=1 value=170 net_name=true}
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C {capa.sym} 40 -240 0 0 {name=C3 m=1 value=100n net_name=true}
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C {capa.sym} 50 -270 0 0 {name=C3 m=1 value=100n net_name=true}
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C {res.sym} 560 -700 0 1 {name=R12 m=1 value=1300 net_name=true}
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C {lab_pin.sym} 690 -890 0 0 {name=p12 lab=B1}
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C {lab_pin.sym} 340 -550 0 1 {name=p13 lab=E9}
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@ -305,7 +298,7 @@ C {lab_pin.sym} 560 -650 0 1 {name=p20 lab=E8}
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C {lab_pin.sym} 840 -940 0 0 {name=p21 lab=E11}
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C {lab_pin.sym} 260 -260 0 1 {name=p22 lab=E3}
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C {lab_pin.sym} 260 -350 0 0 {name=p26 lab=C3}
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C {lab_pin.sym} 40 -300 0 0 {name=p30 lab=B3}
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C {lab_pin.sym} 50 -300 0 0 {name=p30 lab=B3}
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C {lab_pin.sym} 520 -580 0 0 {name=p33 lab=VSS}
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C {res.sym} 340 -750 0 1 {name=R13 m=1 value=300 net_name=true}
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C {npn.sym} 200 -720 0 1 {name=Q7 model=q2n2222 area=1 net_name=true}
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@ -472,4 +465,3 @@ C {ngspice_get_expr.sym} 1130 -860 0 0 {name=r22
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node="[ngspice::get_current \{xm1.rd[i]\}]"
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descr = current
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}
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C {ammeter.sym} 270 -720 1 0 {name=v9 net_name=true }
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@ -38,8 +38,8 @@ B 2 1200 -500 1880 -310 {flags=graph
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y1 = -0.0059
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y2 = 11
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divy = 6
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x1=0.0228839
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x2=0.0242439
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x1=0.00562909
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x2=0.0165959
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divx=10
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node="i(v.x1.vu)
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i(v.x0.vu)
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@ -52,8 +52,8 @@ B 2 1200 -830 1880 -520 {flags=graph
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y1 = -49
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y2 = 58
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divy = 12
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x1=0.0228839
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x2=0.0242439
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x1=0.00562909
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x2=0.0165959
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divx=10
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node="outp
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outm
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@ -68,8 +68,8 @@ B 2 1200 -1020 1880 -830 {flags=graph
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y1 = 0
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y2 = 830
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divy = 6
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x1=0.0228839
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x2=0.0242439
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x1=0.00562909
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x2=0.0165959
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divx=10
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@ -82,8 +82,8 @@ B 2 1200 -310 1880 -120 {flags=graph
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y1 = 0
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y2 = 840
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divy = 6
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x1=0.0228839
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x2=0.0242439
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x1=0.00562909
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x2=0.0165959
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divx=10
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@ -185,8 +185,8 @@ N 240 -320 240 -220 { lab=INX}
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N 160 -1220 180 -1220 {lab=#net3}
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N 160 -1060 180 -1060 {lab=#net4}
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N 70 -1140 180 -1140 {lab=#net5}
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C {vsource.sym} 70 -1170 0 0 {name=V1 value="dc \{VPP\} pwl 0 0 1m \{VPP\}"}
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C {vsource.sym} 70 -1110 0 0 {name=V0 value="dc \{VPP\} pwl 0 0 1m \{VPP\}"}
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C {vsource.sym} 70 -1170 0 0 {name=V1 value="dc 50 pwl 0 0 1m 50"}
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C {vsource.sym} 70 -1110 0 0 {name=V0 value="dc 50 pwl 0 0 1m 50"}
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C {lab_pin.sym} 310 -1220 0 1 {name=p5 lab=VPP}
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C {lab_pin.sym} 310 -1060 0 1 {name=p6 lab=VNN}
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C {lab_pin.sym} 310 -1140 0 1 {name=p3 lab=VSS}
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@ -230,7 +230,7 @@ C {res.sym} 550 -460 0 1 {name=R2 m=1 value='100k'}
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C {res.sym} 550 -400 0 1 {name=R3 m=1 value="'100k/(gain-2)'"}
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C {vsource.sym} 870 -1140 0 0 {name=V3
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xvalue="dc 0 pulse -.1 .1 1m .1u .1u 10.1u 20u"
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value="dc 0 sin 0 0.5 \{frequ\} 1m"
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value="dc 0 sin 0 1 \{frequ\} 1m"
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}
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C {res.sym} 240 -810 0 1 {name=R4 m=1 value=100k}
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C {lab_pin.sym} 240 -860 0 0 {name=p18 lab=VPP}
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@ -338,8 +338,7 @@ spice_ignore=0
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value="
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.option ITL4=20000 ITL5=0
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vvss vss 0 dc 0
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.temp 27
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.param VPP=50
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.temp 30
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.param frequ=5k
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.param gain=45
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.option savecurrents
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@ -352,30 +351,13 @@ vvss vss 0 dc 0
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save all
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op
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write poweramp_op.raw
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tran 8e-7 0.025 uic
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tran 8e-7 0.07 uic
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* .FOUR 20k v(outm,outp)
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* .probe i(*)
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plot outp outm
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save p(r*) p(v*)
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write poweramp.raw
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alterparam VPP=30
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reset
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save all
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op
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write poweramp_op2.raw
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tran 8e-7 0.025 uic
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* .FOUR 20k v(outm,outp)
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* .probe i(*)
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save p(r*) p(v*)
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write poweramp2.raw
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quit 0
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.endc
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"}
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C {simulator_commands.sym} 1020 -870 0 0 {name=COMMANDS1
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@ -441,6 +423,3 @@ simswap
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"
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}
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C {launcher.sym} 1000 -220 0 0 {name=h8
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descr="Backannotate2"
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tclcommand="xschem annotate_op $netlist_dir/poweramp_op2.raw"}
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