function reset_flags() set flags on symbols and instances; call reset_flags before rebuilding connectivity to update cached values; add short.sym component that can be used to short two nets together (and remove the short using *_ignore=true); instcheck(): do not proces instances that have *_ignore=true set.
This commit is contained in:
stefan schippers
parent
a3ac9f6d1d
commit
ff216e8187
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@ -676,6 +676,7 @@ int set_rect_flags(xRect *r)
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dbg(1, "set_rect_flags(): flags=%d\n", f);
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return f;
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}
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int set_sym_flags(xSymbol *sym)
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{
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sym->flags = 0;
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@ -710,7 +711,15 @@ int set_inst_flags(xInstance *inst)
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{
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inst->flags=0;
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my_strdup2(_ALLOC_ID_, &inst->instname, get_tok_value(inst->prop_ptr, "name", 0));
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if(inst->ptr >=0) {
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char *type = xctx->sym[inst->ptr].type;
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int cond= type && IS_LABEL_SH_OR_PIN(type);
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if(cond) {
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inst->flags |= PIN_OR_LABEL;
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my_strdup2(_ALLOC_ID_, &(inst->lab), get_tok_value(inst->prop_ptr,"lab",0));
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}
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}
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if(!strcmp(get_tok_value(inst->prop_ptr,"hide",0), "true"))
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inst->flags |= HIDE_INST;
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@ -762,6 +771,18 @@ int set_text_flags(xText *t)
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return 0;
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}
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void reset_flags(void)
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{
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int i;
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for(i = 0; i < xctx->instances; i++) {
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set_inst_flags(&xctx->inst[i]);
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}
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for(i = 0; i < xctx->symbols; i++) {
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set_sym_flags(&xctx->sym[i]);
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}
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}
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/* what:
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* 1: create
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* 0: clear
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@ -1234,7 +1255,7 @@ int place_symbol(int pos, const char *symbol_name, double x, double y, short rot
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cond= type && IS_LABEL_SH_OR_PIN(type);
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if(cond) {
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xctx->inst[n].flags |= PIN_OR_LABEL;
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my_strdup(_ALLOC_ID_, &xctx->inst[n].lab, get_tok_value(xctx->inst[n].prop_ptr,"lab",0));
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my_strdup2(_ALLOC_ID_, &xctx->inst[n].lab, get_tok_value(xctx->inst[n].prop_ptr,"lab",0));
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}
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if(first_call && (draw_sym & 3) ) bbox(START, 0.0 , 0.0 , 0.0 , 0.0);
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xctx->instances++; /* must be updated before calling symbol_bbox() */
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@ -1403,7 +1403,7 @@ static int update_symbol(const char *result, int x, int first_sel)
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cond= type && IS_LABEL_SH_OR_PIN(type);
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if(cond) {
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xctx->inst[*ii].flags |= PIN_OR_LABEL;
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my_strdup(_ALLOC_ID_, &xctx->inst[*ii].lab,
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my_strdup2(_ALLOC_ID_, &xctx->inst[*ii].lab,
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get_tok_value(xctx->inst[*ii].prop_ptr, "lab",0));
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}
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else xctx->inst[*ii].flags &= ~PIN_OR_LABEL;
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@ -508,7 +508,7 @@ void hilight_parent_pins(void)
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for(j=0;j<rects; ++j)
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{
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char *p_n_s1, *p_n_s2;
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if(!xctx->inst[i].node[j]) continue;
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if(!xctx->inst[i].node || !xctx->inst[i].node[j]) continue;
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my_strdup(_ALLOC_ID_, &net_node, expandlabel(xctx->inst[i].node[j], &net_mult));
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dbg(1, "hilight_parent_pins(): net_node=%s\n", net_node);
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pin_name = get_tok_value((xctx->inst[i].ptr+ xctx->sym)->rect[PINLAYER][j].prop_ptr,"name",0);
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@ -566,7 +566,7 @@ void hilight_child_pins(void)
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char *p_n_s1, *p_n_s2;
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dbg(1, "hilight_child_pins(): inst_number=%d\n", inst_number);
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if(!xctx->inst[i].node[j]) continue;
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if(!xctx->inst[i].node || !xctx->inst[i].node[j]) continue;
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my_strdup(_ALLOC_ID_, &net_node, expandlabel(xctx->inst[i].node[j], &net_mult));
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dbg(1, "hilight_child_pins(): net_node=%s\n", net_node);
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pin_name = get_tok_value((xctx->inst[i].ptr+ xctx->sym)->rect[PINLAYER][j].prop_ptr,"name",0);
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@ -1219,7 +1219,7 @@ static void send_current_to_gaw(int simtype, const char *node)
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my_free(_ALLOC_ID_, &t);
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}
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/* hilight/clear pin/label instances attached to hilight nets, or instances with "hilight=true"
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/* hilight/clear pin/label instances attached to hilight nets, or instances with "highlight=true"
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* attr if en_hilight_conn_inst option is set
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*/
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void propagate_hilights(int set, int clear, int mode)
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@ -1242,7 +1242,7 @@ void propagate_hilights(int set, int clear, int mode)
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type = (xctx->inst[i].ptr+ xctx->sym)->type;
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hilight_connected_inst = en_hi &&
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((xctx->inst[i].flags & HILIGHT_CONN) || ((xctx->inst[i].ptr+ xctx->sym)->flags & HILIGHT_CONN));
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/* hilight/clear instances with hilight=true attr set and en_hilight_conn_inst option is set ... */
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/* hilight/clear instances with highlight=true attr set and en_hilight_conn_inst option is set ... */
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if(type && !IS_LABEL_SH_OR_PIN(type)) {
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if (hilight_connected_inst) {
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int rects, j, nohilight_pins;
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@ -1296,17 +1296,16 @@ void propagate_hilights(int set, int clear, int mode)
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static int get_logic_value(int inst, int n)
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{
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int /* mult, */ val;
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int /* mult, */ val = 2; /* LOGIC_X */
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Hilight_hashentry *entry;
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/* char *netname = NULL; */
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if(!xctx->inst[inst].node || !xctx->inst[inst].node[n]) return val;
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/* fast option: dont use net_name() (no expandlabel though) */
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/* THIS MUST BE DONE TO HANDLE VECTOR INSTANCES/BUSES */
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/* my_strdup(xxxx, &netname, net_name(inst, n, &mult, 1, 0)); */
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entry=hilight_hash_lookup(xctx->inst[inst].node[n], 0, XLOOKUP);
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if(!entry) {
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val = 2; /* LOGIC_X */
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} else {
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if(entry) {
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val = entry->value;
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val = (val == LOGIC_0) ? 0 : (val == LOGIC_1) ? 1 : (val == LOGIC_Z) ? 3 : 2;
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/* dbg(1, "get_logic_value(): inst=%d pin=%d net=%s val=%d\n", inst, n, netname, val); */
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@ -1562,7 +1561,10 @@ static void propagate_logic()
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clock_pin = xctx->simdata[i].pin[j].clock;
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if(clock_pin != -1) {
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/* no bus_hilight_lookup --> no bus expansion */
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entry = hilight_hash_lookup(xctx->inst[i].node[j], 0, XLOOKUP); /* clock pin */
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entry = NULL;
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if(xctx->inst[i].node && xctx->inst[i].node[j]) {
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entry = hilight_hash_lookup(xctx->inst[i].node[j], 0, XLOOKUP); /* clock pin */
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}
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clock_val = (!entry) ? LOGIC_X : entry->value;
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clock_oldval = (!entry) ? LOGIC_X : entry->oldvalue;
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if(entry) {
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@ -1625,6 +1627,7 @@ static void propagate_logic()
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for(i=0; i<xctx->instances; ++i) {
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for(j=0;j < xctx->simdata[i].npin; ++j) {
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if(xctx->simdata[i].pin[j].value != -10000) {
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if(!xctx->inst[i].node || !xctx->inst[i].node[j]) continue;
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entry = hilight_hash_lookup(xctx->inst[i].node[j], 0, XLOOKUP);
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if(!entry || xctx->hilight_time != entry->time) {
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hilight_hash_lookup(xctx->inst[i].node[j], xctx->simdata[i].pin[j].value, XINSERT);
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@ -344,9 +344,9 @@ void mem_push_undo(void)
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xctx->uslot[slot].iptr[i].instname = NULL;
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xctx->uslot[slot].iptr[i].lab = NULL;
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xctx->uslot[slot].iptr[i].node = NULL;
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my_strdup(_ALLOC_ID_, &xctx->uslot[slot].iptr[i].lab, xctx->inst[i].lab);
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my_strdup2(_ALLOC_ID_, &xctx->uslot[slot].iptr[i].lab, xctx->inst[i].lab);
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my_strdup2(_ALLOC_ID_, &xctx->uslot[slot].iptr[i].instname, xctx->inst[i].instname);
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my_strdup(_ALLOC_ID_, &xctx->uslot[slot].iptr[i].prop_ptr, xctx->inst[i].prop_ptr);
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my_strdup2(_ALLOC_ID_, &xctx->uslot[slot].iptr[i].prop_ptr, xctx->inst[i].prop_ptr);
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my_strdup2(_ALLOC_ID_, &xctx->uslot[slot].iptr[i].name, xctx->inst[i].name);
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}
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@ -503,10 +503,10 @@ void mem_pop_undo(int redo, int set_modify_status)
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xctx->inst[i].name = NULL;
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xctx->inst[i].instname = NULL;
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xctx->inst[i].lab = NULL;
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my_strdup(_ALLOC_ID_, &xctx->inst[i].prop_ptr, xctx->uslot[slot].iptr[i].prop_ptr);
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my_strdup2(_ALLOC_ID_, &xctx->inst[i].prop_ptr, xctx->uslot[slot].iptr[i].prop_ptr);
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my_strdup2(_ALLOC_ID_, &xctx->inst[i].name, xctx->uslot[slot].iptr[i].name);
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my_strdup2(_ALLOC_ID_, &xctx->inst[i].instname, xctx->uslot[slot].iptr[i].instname);
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my_strdup(_ALLOC_ID_, &xctx->inst[i].lab, xctx->uslot[slot].iptr[i].lab);
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my_strdup2(_ALLOC_ID_, &xctx->inst[i].lab, xctx->uslot[slot].iptr[i].lab);
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}
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/* symbols */
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15
src/move.c
15
src/move.c
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@ -516,8 +516,11 @@ void find_inst_to_be_redrawn(int what)
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if(type &&
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(
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IS_LABEL_OR_PIN(type) ||
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/* some pass through symbols have type show_label (metal option)
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* | */
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(!strcmp(type, "show_label") && (inst[n].ptr + xctx->sym)->rects[PINLAYER] > 1) ||
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/* bus taps */
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(!strcmp(type, "show_label") && (inst[n].ptr + xctx->sym)->rects[PINLAYER] == 2)
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!strcmp(type, "bus_tap")
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)
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) {
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for(p = 0; p < (inst[n].ptr + xctx->sym)->rects[PINLAYER]; p++) {
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@ -537,10 +540,10 @@ void find_inst_to_be_redrawn(int what)
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for(i=0; i < xctx->instances; ++i) {
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char *type=xctx->sym[xctx->inst[i].ptr].type;
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/* bus taps */
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if(type && !strcmp(type, "show_label") && (inst[i].ptr + xctx->sym)->rects[PINLAYER] == 2 ) {
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if(int_hash_lookup(&xctx->node_redraw_table, xctx->inst[i].node[0], 0, XLOOKUP)) {
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int_hash_lookup(&xctx->node_redraw_table, xctx->inst[i].node[1], 0, XINSERT_NOREPLACE);
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dbg(1, "bus_tap: propagate %s\n", xctx->inst[i].node[1]);
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if(type && !strcmp(type, "bus_tap")) {
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if(int_hash_lookup(&xctx->node_redraw_table, xctx->inst[i].node[1], 0, XLOOKUP)) {
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int_hash_lookup(&xctx->node_redraw_table, xctx->inst[i].node[0], 0, XINSERT_NOREPLACE);
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dbg(1, "bus_tap: propagate %s\n", xctx->inst[i].node[0]);
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}
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}
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}
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@ -985,7 +988,7 @@ void copy_objects(int what)
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xctx->inst[xctx->instances].name=NULL;
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my_strdup2(_ALLOC_ID_, &xctx->inst[xctx->instances].name, xctx->inst[n].name);
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my_strdup(_ALLOC_ID_, &xctx->inst[xctx->instances].prop_ptr, xctx->inst[n].prop_ptr);
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my_strdup(_ALLOC_ID_, &xctx->inst[xctx->instances].lab, xctx->inst[n].lab);
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my_strdup2(_ALLOC_ID_, &xctx->inst[xctx->instances].lab, xctx->inst[n].lab);
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xctx->inst[n].sel=0;
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xctx->inst[xctx->instances].embed = xctx->inst[n].embed;
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xctx->inst[xctx->instances].flags = xctx->inst[n].flags;
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@ -671,7 +671,7 @@ static void set_inst_node(int i, int j, const char *node)
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const char *dir = get_tok_value(rect[j].prop_ptr, "dir",0);
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bus_node_hash_lookup(inst[i].node[j], dir, XINSERT, 0,"","","","");
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}
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if(node[0] == '#') { /* update multilicity of unnamed node */
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if(node && node[0] == '#') { /* update multilicity of unnamed node */
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int pin_mult;
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expandlabel(get_tok_value(rect[j].prop_ptr, "name", 0), &pin_mult);
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get_unnamed_node(2, pin_mult * inst_mult, atoi((inst[i].node[j]) + 4));
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@ -859,29 +859,51 @@ static int instcheck(int n, int p)
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{
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int err = 0;
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xInstance * const inst = xctx->inst;
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xSymbol * const sym = xctx->sym;
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int j, sqx, sqy;
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double x0, y0;
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int rects = xctx->sym[inst[n].ptr].rects[PINLAYER];
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int bus_tap = !strcmp(xctx->sym[inst[n].ptr].type, "show_label") && rects == 2;
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int bus_tap = !strcmp(xctx->sym[inst[n].ptr].type, "bus_tap");
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int k = inst[n].ptr;
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/* process bus taps : type = show_label, pin 0 = bus connection, pin 1 = tap (lab=[n]) */
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if(bus_tap && p == 1) {
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if( xctx->netlist_type == CAD_VERILOG_NETLIST &&
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((inst[n].flags & VERILOG_IGNORE_INST) ||
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(k >= 0 && (sym[k].flags & VERILOG_IGNORE_INST))) ) return 0;
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if( xctx->netlist_type == CAD_SPICE_NETLIST &&
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((inst[n].flags & SPICE_IGNORE_INST) ||
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(k >= 0 && (sym[k].flags & SPICE_IGNORE_INST))) ) return 0;
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if( xctx->netlist_type == CAD_VHDL_NETLIST &&
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((inst[n].flags & VHDL_IGNORE_INST) ||
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(k >= 0 &&(sym[k].flags & VHDL_IGNORE_INST))) ) return 0;
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if( xctx->netlist_type == CAD_TEDAX_NETLIST &&
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((inst[n].flags & TEDAX_IGNORE_INST) ||
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(k >= 0 && (sym[k].flags & TEDAX_IGNORE_INST))) ) return 0;
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/* process bus taps : type = bus_tap */
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if(bus_tap && p == 0) {
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/* do nothing */
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dbg(0, "instcheck(): bus tap pin 1: node=%s\n", inst[n].node[p] ? inst[n].node[p] : "NULL");
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dbg(0, "instcheck(): bus tap pin 0: node=%s\n", inst[n].node[p] ? inst[n].node[p] : "NULL");
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}
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else if(bus_tap && p == 0) {
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else if(bus_tap && p == 1) {
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char *node_base_name = NULL;
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const char *tap;
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dbg(1, "instcheck: bus tap node: %s\n", inst[n].node[0]);
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if(!inst[n].node[1]) { /* still unnamed */
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dbg(1, "instcheck: bus tap node: %s\n", inst[n].node[p]);
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if(!inst[n].node[0]) { /* still unnamed */
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/* tap = get_tok_value(inst[n].prop_ptr, "lab", 0); */
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tap = inst[n].lab;
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/* Check if this is a bus slice and must be appended to bus base name */
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if(tap[0] == '[' || isonlydigit(tap)) {
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/* find bus basename, from beginning or first character after ',' and ' ' */
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char *nptr = strchr(inst[n].node[0], '[');
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char *nptr = strchr(inst[n].node[p], '[');
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if(nptr) {
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while(nptr > inst[n].node[0]) {
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while(nptr > inst[n].node[p]) {
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nptr--;
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if(*nptr == ',') {
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while(*(++nptr) ==' ');
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@ -889,22 +911,22 @@ static int instcheck(int n, int p)
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}
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}
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} else {
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nptr = inst[n].node[0];
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nptr = inst[n].node[p];
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}
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node_base_name = my_malloc(_ALLOC_ID_, strlen(inst[n].node[0]) + 1);
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node_base_name = my_malloc(_ALLOC_ID_, strlen(inst[n].node[p]) + 1);
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sscanf(nptr, "%[^[]", node_base_name);
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my_strcat(_ALLOC_ID_, &node_base_name, tap);
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}
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else {
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my_strdup2(_ALLOC_ID_, &node_base_name, tap);
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}
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set_inst_node(n, 1, node_base_name);
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get_inst_pin_coord(n, 1, &x0, &y0);
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set_inst_node(n, 0, node_base_name);
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get_inst_pin_coord(n, 0, &x0, &y0);
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get_square(x0, y0, &sqx, &sqy);
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err |= name_attached_nets(x0, y0, sqx, sqy, inst[n].node[1]);
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err |= name_attached_inst(n, x0, y0, sqx, sqy, inst[n].node[1]);
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err |= name_attached_nets(x0, y0, sqx, sqy, inst[n].node[0]);
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err |= name_attached_inst(n, x0, y0, sqx, sqy, inst[n].node[0]);
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} else {
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if(for_netlist>0) err |= signal_short("Bus tap", inst[n].node[0], inst[n].node[1]);
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if(for_netlist>0) err |= signal_short("Bus tap", inst[n].node[p], inst[n].node[0]);
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}
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my_free(_ALLOC_ID_, &node_base_name);
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}
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@ -1168,6 +1190,8 @@ int prepare_netlist_structs(int for_netl)
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for_netlist = for_netl;
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if(for_netlist>0 && xctx->prep_net_structs) return 0;
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else if(!for_netlist && xctx->prep_hi_structs) return 0;
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reset_flags();
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set_modify(-2); /* to reset floater cached values */
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/* delete instance pins spatial hash, wires spatial hash, node_hash, wires and inst nodes.*/
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if(for_netlist) {
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my_snprintf(nn, S(nn), "-----------%s", xctx->sch[xctx->currsch]);
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@ -2399,7 +2399,7 @@ void link_symbols_to_instances(int from)
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cond= type && IS_LABEL_SH_OR_PIN(type);
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if(cond) {
|
||||
xctx->inst[i].flags |= PIN_OR_LABEL; /* label or pin */
|
||||
my_strdup(_ALLOC_ID_, &xctx->inst[i].lab, get_tok_value(xctx->inst[i].prop_ptr,"lab",0));
|
||||
my_strdup2(_ALLOC_ID_, &xctx->inst[i].lab, get_tok_value(xctx->inst[i].prop_ptr,"lab",0));
|
||||
}
|
||||
else xctx->inst[i].flags &= ~PIN_OR_LABEL; /* ordinary symbol */
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2899,7 +2899,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
|
|||
cond= type && IS_LABEL_SH_OR_PIN(type);
|
||||
if(cond) {
|
||||
xctx->inst[inst].flags |= PIN_OR_LABEL;
|
||||
my_strdup(_ALLOC_ID_, &xctx->inst[inst].lab, get_tok_value(xctx->inst[inst].prop_ptr, "lab", 0));
|
||||
my_strdup2(_ALLOC_ID_, &xctx->inst[inst].lab, get_tok_value(xctx->inst[inst].prop_ptr, "lab", 0));
|
||||
}
|
||||
else xctx->inst[inst].flags &= ~PIN_OR_LABEL;
|
||||
|
||||
|
|
@ -2923,13 +2923,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
|
|||
* Reset cached instance and symbol cached flags (inst->flags, sym->flags) */
|
||||
else if(!strcmp(argv[1], "reset_flags"))
|
||||
{
|
||||
int i;
|
||||
for(i = 0; i < xctx->instances; i++) {
|
||||
set_inst_flags(&xctx->inst[i]);
|
||||
}
|
||||
for(i = 0; i < xctx->symbols; i++) {
|
||||
set_sym_flags(&xctx->sym[i]);
|
||||
}
|
||||
reset_flags();
|
||||
Tcl_ResetResult(interp);
|
||||
}
|
||||
|
||||
|
|
@ -3418,7 +3412,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
|
|||
cond= type && IS_LABEL_SH_OR_PIN(type);
|
||||
if(cond) {
|
||||
xctx->inst[inst].flags |= PIN_OR_LABEL;
|
||||
my_strdup(_ALLOC_ID_, &xctx->inst[inst].lab, get_tok_value(xctx->inst[inst].prop_ptr, "lab", 0));
|
||||
my_strdup2(_ALLOC_ID_, &xctx->inst[inst].lab, get_tok_value(xctx->inst[inst].prop_ptr, "lab", 0));
|
||||
}
|
||||
else xctx->inst[inst].flags &= ~PIN_OR_LABEL;
|
||||
|
||||
|
|
|
|||
10
src/xschem.h
10
src/xschem.h
|
|
@ -336,9 +336,14 @@ extern char win_temp_dir[PATH_MAX];
|
|||
|
||||
#define MINOR(a,b) ( (a) <= (b) ? (a) : (b) )
|
||||
|
||||
/* "show_label" type symbols are used for any type of symbol that
|
||||
* must be automatically highlighted by attached nets
|
||||
* show_label also used on metal option type symbols (pass-through symbols)
|
||||
* to optionally short two nets (using *_ignore=[true|false] attribute) */
|
||||
#define IS_LABEL_SH_OR_PIN(type) (!(strcmp(type,"label") && strcmp(type,"ipin") && strcmp(type,"opin") && \
|
||||
strcmp(type,"show_label") && strcmp(type,"iopin")))
|
||||
#define IS_LABEL_OR_PIN(type) (!(strcmp(type,"label") && strcmp(type,"ipin") && strcmp(type,"opin") && strcmp(type,"iopin")))
|
||||
strcmp(type,"show_label") && strcmp(type,"iopin") && strcmp(type,"bus_tap")))
|
||||
#define IS_LABEL_OR_PIN(type) (!(strcmp(type,"label") && strcmp(type,"ipin") && \
|
||||
strcmp(type,"opin") && strcmp(type,"iopin")))
|
||||
#define IS_PIN(type) (!(strcmp(type,"ipin") && strcmp(type,"opin") && strcmp(type,"iopin")))
|
||||
#define XSIGN(x) ( (x) < 0 ? -1 : 1)
|
||||
#define XSIGN0(x) ( (x) < 0 ? -1 : (x) > 0 ? 1 : 0)
|
||||
|
|
@ -1132,6 +1137,7 @@ extern int set_rect_flags(xRect *r);
|
|||
extern int set_text_flags(xText *t);
|
||||
extern int set_inst_flags(xInstance *inst);
|
||||
extern int set_sym_flags(xSymbol *sym);
|
||||
extern void reset_flags(void);
|
||||
extern const char *get_text_floater(int i);
|
||||
extern int set_rect_extraptr(int what, xRect *drptr);
|
||||
extern unsigned char *base64_decode(const char *data, const size_t input_length, size_t *output_length);
|
||||
|
|
|
|||
|
|
@ -32,4 +32,4 @@ xschem instance ../../../xschem_library/devices/bus_connect.sym 500 -530 0 0 {na
|
|||
xschem instance ../../../xschem_library/devices/bus_connect_nolab.sym 400 -530 0 0 {name=r1}
|
||||
xschem instance ../../../xschem_library/devices/lab_pin.sym 410 -600 3 1 {name=l4 sig_type=std_logic lab=BUS[2]}
|
||||
xschem save
|
||||
xschem exit
|
||||
xschem exit closewindow
|
||||
|
|
@ -77,4 +77,4 @@ xschem instance ../../../xschem_library/devices/lab_pin.sym 40 -350 0 1 {name=l5
|
|||
xschem instance ../../../xschem_library/devices/lab_pin.sym 40 -410 0 1 {name=l6 lab=INPUT_E verilog_type=reg}
|
||||
xschem instance ../../../xschem_library/devices/lab_pin.sym 40 -390 0 1 {name=l7 lab=INPUT_F verilog_type=reg}
|
||||
xschem save
|
||||
xschem exit
|
||||
xschem exit closewindow
|
||||
|
|
@ -83,4 +83,4 @@ xschem instance ../../../xschem_library/devices/gnd.sym 250 -130 0 0 {name=l1 la
|
|||
xschem instance ../../../xschem_library/devices/res.sym 550 -290 0 0 {name=R1 m=1 value=47K footprint=1206 device=resistor}
|
||||
xschem instance ../../../xschem_library/devices/lab_wire.sym 330 -260 0 0 {name=l3 lab=Z}
|
||||
xschem save
|
||||
xschem exit
|
||||
xschem exit closewindow
|
||||
|
|
@ -216,4 +216,4 @@ xschem instance ../../../xschem_library/devices/spice_probe.sym 1670 -740 0 0 {n
|
|||
xschem instance ../../../xschem_library/devices/lab_pin.sym 1670 -790 0 0 {name=l4 lab=LDBL[0,16,32,1,17,33,2,18,34]}
|
||||
xschem instance ../../../xschem_library/devices/spice_probe.sym 1670 -790 0 0 {name=p91 analysis=tran}
|
||||
xschem save
|
||||
xschem exit
|
||||
xschem exit closewindow
|
||||
|
|
@ -14,4 +14,4 @@ xschem wire -10 -70 -10 20
|
|||
xschem select_all
|
||||
xschem hilight
|
||||
xschem save
|
||||
xschem exit
|
||||
xschem exit closewindow
|
||||
|
|
@ -1,18 +1,18 @@
|
|||
v {xschem version=3.4.0 file_version=1.2
|
||||
}
|
||||
G {}
|
||||
K {type=show_label
|
||||
K {type=bus_tap
|
||||
template="name=l1 lab=[0]"
|
||||
net_name=true
|
||||
format="* tap: @#0:net_name --> @#1:net_name"
|
||||
verilog_format="// tap: @#0:net_name --> @#1:net_name"
|
||||
vhdl_format="-- tap: @#0:net_name --> @#1:net_name"
|
||||
tedax_format="# tap: @#0:net_name --> @#1:net_name"}
|
||||
format="* tap: @#1:net_name --> @#0:net_name"
|
||||
verilog_format="// tap: @#1:net_name --> @#0:net_name"
|
||||
vhdl_format="-- tap: @#1:net_name --> @#0:net_name"
|
||||
tedax_format="# tap: @#1:net_name --> @#0:net_name"}
|
||||
V {}
|
||||
S {}
|
||||
E {}
|
||||
L 1 0 0 10 -10 {}
|
||||
B 5 -0.625 -0.625 0.625 0.625 {name=bus dir=inout}
|
||||
B 5 9.375 -10.625 10.625 -9.375 {name=tap dir=inout}
|
||||
B 5 -0.625 -0.625 0.625 0.625 {name=bus dir=inout}
|
||||
T {@lab} 12.5 -12.5 3 0 0.27 0.27 {}
|
||||
T {@#1:net_name} 31.25 -12.5 3 0 0.15 0.15 {layer=15}
|
||||
T {@#0:net_name} 31.25 -12.5 3 0 0.15 0.15 {layer=15}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,16 @@
|
|||
v {xschem version=3.4.0 file_version=1.2
|
||||
}
|
||||
G {}
|
||||
K {type=show_label
|
||||
template="name=x1 value=0.1"
|
||||
format="@name @pinlist @symname value=@value"
|
||||
highlight=true}
|
||||
V {}
|
||||
S {}
|
||||
E {}
|
||||
L 1 -30 -0 30 0 {}
|
||||
B 5 -32.5 -2.5 -27.5 2.5 {name=A dir=inout }
|
||||
B 5 27.5 -2.5 32.5 2.5 {name=A dir=inout }
|
||||
T {short} 2.5 14 0 0 0.3 0.3 { layer=3
|
||||
hcenter=true}
|
||||
T {@name} 15 -22 0 0 0.2 0.2 {}
|
||||
|
|
@ -45,12 +45,12 @@ A 7 884.1666666666666 -210 39.58991173406564 210.3432488842396 198.9246444160511
|
|||
P 1 10 880 -490 870 -550 950 -530 910 -510 940 -480 920 -480 910 -460 890 -500 880 -480 880 -490 {dash=3}
|
||||
P 4 6 830 -470 830 -560 820 -510 820 -550 810 -520 810 -490 {}
|
||||
P 15 11 870 -520 880 -560 900 -530 910 -550 920 -520 940 -530 920 -490 890 -500 860 -480 840 -530 870 -520 {fill=true}
|
||||
T {Welcome to XSCHEM!} 110 -1060 0 0 1 1 {layer=5}
|
||||
T {Welcome to XSCHEM!} 110 -1100 0 0 1 1 {layer=5}
|
||||
T {This is a test schematic window
|
||||
|
||||
On the left you see some sample circuits. You may descend into any of these by selecting one with a left mouse button click and
|
||||
pressing the 'e' key, or by menu 'Edit -> Push Schematic'. You can return here after descending into a schematic by hitting
|
||||
'<Ctrl>-e' or by menu 'Edit -> Pop'.} 60 -990 0 0 0.4 0.4 {}
|
||||
'<Ctrl>-e' or by menu 'Edit -> Pop'.} 60 -1030 0 0 0.4 0.4 {}
|
||||
T {Lines} 960 -680 0 0 0.6 0.6 {layer=4}
|
||||
T {Rectangles} 960 -620 0 0 0.6 0.6 {layer=4}
|
||||
T {Polygons} 960 -530 0 0 0.6 0.6 {layer=4}
|
||||
|
|
@ -87,16 +87,16 @@ N 380 -310 640 -310 {lab=BUS[4:0]}
|
|||
N 510 -400 510 -320 {lab=BUS[1]}
|
||||
N 410 -350 410 -320 {lab=BUS[2]}
|
||||
N 460 -400 460 -320 {lab=BUS[2:1]}
|
||||
C {poweramp.sym} 480 -750 0 0 {name=x1
|
||||
C {poweramp.sym} 480 -790 0 0 {name=x1
|
||||
tclcommand="xschem descend"}
|
||||
C {tesla.sym} 160 -630 0 0 {name=x2}
|
||||
C {test_ne555.sym} 160 -590 0 0 {name=x3}
|
||||
C {test_lm324.sym} 160 -550 0 0 {name=x4}
|
||||
C {osc.sym} 160 -670 0 0 {name=x5}
|
||||
C {tesla.sym} 160 -670 0 0 {name=x2}
|
||||
C {test_ne555.sym} 160 -630 0 0 {name=x3}
|
||||
C {test_lm324.sym} 160 -590 0 0 {name=x4}
|
||||
C {osc.sym} 160 -710 0 0 {name=x5}
|
||||
C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
|
||||
C {cmos_example.sym} 160 -710 0 0 {name=x6}
|
||||
C {greycnt.sym} 160 -750 0 0 {name=x8}
|
||||
C {loading.sym} 160 -790 0 0 {name=x9}
|
||||
C {cmos_example.sym} 160 -750 0 0 {name=x6}
|
||||
C {greycnt.sym} 160 -790 0 0 {name=x8}
|
||||
C {loading.sym} 160 -830 0 0 {name=x9}
|
||||
C {inv_bsource.sym} 880 -320 0 0 {name=B1 TABLE="1.4 3.0 1.6 0.0"}
|
||||
C {launcher.sym} 460 -140 0 0 {name=h1
|
||||
descr="XSCHEM ON REPO.HU"
|
||||
|
|
@ -113,17 +113,17 @@ url="$\{XSCHEM_SHAREDIR\}/../doc/xschem/index.html"
|
|||
program=x-www-browser
|
||||
|
||||
}
|
||||
C {rlc.sym} 160 -830 0 0 {name=x0}
|
||||
C {rlc.sym} 160 -870 0 0 {name=x0}
|
||||
C {lab_pin.sym} 640 -310 0 1 {name=l2 sig_type=std_logic lab=BUS[4:0]}
|
||||
C {bus_connect.sym} 500 -310 0 0 {name=l3 lab=BUS[1]}
|
||||
C {bus_connect_nolab.sym} 400 -310 0 0 {name=r1}
|
||||
C {lab_pin.sym} 410 -350 3 1 {name=l4 sig_type=std_logic lab=BUS[2]}
|
||||
C {LCC_instances.sym} 160 -510 0 0 {name=x7}
|
||||
C {test_backannotated_subckt.sym} 160 -470 0 0 {name=x10}
|
||||
C {plot_manipulation.sym} 160 -430 0 0 {name=x11}
|
||||
C {logic_test.sym} 160 -390 0 0 {name=x12}
|
||||
C {simulate_ff.sym} 160 -350 0 0 {name=x13}
|
||||
C {test_mos_verilog.sym} 160 -310 0 0 {name=x14}
|
||||
C {LCC_instances.sym} 160 -550 0 0 {name=x7}
|
||||
C {test_backannotated_subckt.sym} 160 -510 0 0 {name=x10}
|
||||
C {plot_manipulation.sym} 160 -470 0 0 {name=x11}
|
||||
C {logic_test.sym} 160 -430 0 0 {name=x12}
|
||||
C {simulate_ff.sym} 160 -390 0 0 {name=x13}
|
||||
C {test_mos_verilog.sym} 160 -350 0 0 {name=x14}
|
||||
C {launcher.sym} 1265 -225 0 0 {name=h5
|
||||
descr=" Ctrl-Left-Click to load/
|
||||
unload waveforms"
|
||||
|
|
@ -1456,18 +1456,19 @@ xwtAgA9ve8fHC0Dod8blIpQLQJBdgRgxavQ/AAAAgEslwD6d7SiMdxwqP41maeirFRxABH/Rb+tVM0DO
|
|||
cwtAyKwqggMC8z8AAABAXz/APixDHOviNio/cIyWTt0GHEAHmaX3NW0zQHJvU5F/bTNA3V5CW3kqoL85tJeeXUIJQIB/waNeQglAcFfF8JIdC0DY7tjwBPjxPwAAALCc
|
||||
UsA+"
|
||||
}
|
||||
C {test_ac.sym} 160 -270 0 0 {name=x15}
|
||||
C {rom8k.sym} 480 -790 0 0 {name=x17}
|
||||
C {test_doublepin.sym} 160 -230 0 0 {name=x19}
|
||||
C {classD_amp.sym} 480 -830 0 0 {name=x20}
|
||||
C {delta_sigma.sym} 480 -670 0 0 {name=x21}
|
||||
C {solar_panel.sym} 480 -630 0 0 {name=xsolar}
|
||||
C {test_extracted_netlist.sym} 160 -190 0 0 {name=x23
|
||||
C {test_ac.sym} 160 -310 0 0 {name=x15}
|
||||
C {rom8k.sym} 480 -830 0 0 {name=x17}
|
||||
C {test_doublepin.sym} 160 -270 0 0 {name=x19}
|
||||
C {classD_amp.sym} 480 -870 0 0 {name=x20}
|
||||
C {delta_sigma.sym} 480 -710 0 0 {name=x21}
|
||||
C {solar_panel.sym} 480 -670 0 0 {name=xsolar}
|
||||
C {test_extracted_netlist.sym} 160 -230 0 0 {name=x23
|
||||
tclcommand="xschem descend"}
|
||||
C {poweramp_lcc.sym} 480 -710 0 0 {name=x16
|
||||
C {poweramp_lcc.sym} 480 -750 0 0 {name=x16
|
||||
tclcommand="xschem descend"}
|
||||
C {test_symbolgen.sym} 480 -590 0 0 {name=x18}
|
||||
C {inst_sch_select.sym} 480 -550 0 0 {name=x24}
|
||||
C {test_bus_tap.sym} 480 -510 0 0 {name=x22}
|
||||
C {test_symbolgen.sym} 480 -630 0 0 {name=x18}
|
||||
C {inst_sch_select.sym} 480 -590 0 0 {name=x24}
|
||||
C {test_bus_tap.sym} 480 -550 0 0 {name=x22}
|
||||
C {bus_tap.sym} 450 -310 1 1 {name=l5 lab=[2:1]}
|
||||
C {test_jfet.sym} 480 -470 0 0 {name=x25}
|
||||
C {test_jfet.sym} 480 -510 0 0 {name=x25}
|
||||
C {test_short_option.sym} 480 -470 0 0 {name=x26}
|
||||
|
|
|
|||
|
|
@ -102,6 +102,10 @@ N 1110 -1170 1110 -800 {
|
|||
lab=DOUT[15:0]}
|
||||
N 620 -600 620 -590 {
|
||||
lab=VCC}
|
||||
N 390 -970 390 -910 {
|
||||
lab=ADD[1]}
|
||||
N 390 -850 390 -830 {
|
||||
lab=VSS}
|
||||
C {bus_tap.sym} 400 -390 3 0 {name=l1 lab=[3]
|
||||
}
|
||||
C {bus_tap.sym} 290 -390 3 0 {name=l2 lab=[13]
|
||||
|
|
@ -314,3 +318,13 @@ C {bus_tap.sym} 1120 -790 3 0 {name=l19 lab=[15:0]
|
|||
}
|
||||
C {lab_pin.sym} 620 -600 0 0 {name=p23 sig_type=std_logic lab=VCC
|
||||
}
|
||||
C {bus_tap.sym} 380 -980 1 0 {name=l20 lab=[1]
|
||||
}
|
||||
C {res.sym} 390 -880 0 0 {name=R20
|
||||
value=1k
|
||||
footprint=1206
|
||||
device=resistor
|
||||
m=1
|
||||
}
|
||||
C {lab_pin.sym} 390 -830 0 0 {name=p31 sig_type=std_logic lab=VSS
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,131 @@
|
|||
v {xschem version=3.4.0 file_version=1.2
|
||||
}
|
||||
G {}
|
||||
K {}
|
||||
V {}
|
||||
S {}
|
||||
E {}
|
||||
L 7 920 -190 1100 -190 {}
|
||||
P 4 7 320 -630 320 -550 310 -550 320 -530 330 -550 320 -550 320 -630 {}
|
||||
P 4 7 640 -540 590 -540 590 -550 570 -540 590 -530 590 -540 640 -540 {}
|
||||
P 4 7 950 -470 950 -380 940 -380 950 -360 960 -380 950 -380 950 -470 {}
|
||||
T {Title symbol has embedded TCL command
|
||||
to enable show_pin_net_names.} 130 -130 0 0 0.4 0.4 { layer=7}
|
||||
T {Set tcl variable IGNORE to 1 or 0 to
|
||||
enable / disable some components in
|
||||
title instance attributes} 50 -940 0 0 1 1 {}
|
||||
T {tcleval(IGNORE=$IGNORE)} 920 -230 0 0 0.6 0.6 {name=l1}
|
||||
T {The short component is a pass-through symbol. It can be used to short two nets.
|
||||
Setting spice_ignore=true will disable the component and remove the short.} 80 -690 0 0 0.4 0.4 {}
|
||||
T {This is the lab_show component
|
||||
it is used only to display the net
|
||||
name it is attached to. This works if
|
||||
Options->Show net names on symbol pins
|
||||
is enabled.} 650 -600 0 0 0.4 0.4 {}
|
||||
N 120 -230 170 -230 {
|
||||
lab=NET_A}
|
||||
N 470 -230 520 -230 {
|
||||
lab=NET_A}
|
||||
N 170 -330 170 -230 {
|
||||
lab=NET_A}
|
||||
N 470 -330 470 -230 {
|
||||
lab=NET_A}
|
||||
N 170 -330 290 -330 {
|
||||
lab=NET_A}
|
||||
N 350 -330 470 -330 {
|
||||
lab=NET_A}
|
||||
N 120 -420 170 -420 {
|
||||
lab=NET_C}
|
||||
N 470 -420 520 -420 {
|
||||
lab=NET_C}
|
||||
N 170 -520 170 -420 {
|
||||
lab=NET_C}
|
||||
N 470 -520 470 -420 {
|
||||
lab=NET_C}
|
||||
N 170 -520 290 -520 {
|
||||
lab=NET_C}
|
||||
N 350 -520 470 -520 {
|
||||
lab=NET_C}
|
||||
N 370 -420 470 -420 {
|
||||
lab=NET_C}
|
||||
N 170 -420 290 -420 {
|
||||
lab=NET_C}
|
||||
N 370 -230 470 -230 {
|
||||
lab=NET_A}
|
||||
N 170 -230 290 -230 {
|
||||
lab=NET_A}
|
||||
N 600 -420 650 -420 {
|
||||
lab=#net1}
|
||||
N 650 -400 650 -340 {
|
||||
lab=#net1}
|
||||
N 650 -340 740 -340 {
|
||||
lab=#net1}
|
||||
N 650 -300 740 -300 {
|
||||
lab=NET_B}
|
||||
N 650 -300 650 -230 {
|
||||
lab=NET_B}
|
||||
N 600 -230 650 -230 {
|
||||
lab=NET_B}
|
||||
N 860 -320 900 -320 {
|
||||
lab=#net1}
|
||||
N 650 -400 750 -400 {
|
||||
lab=#net1}
|
||||
N 810 -400 860 -400 {
|
||||
lab=#net1}
|
||||
N 860 -400 860 -320 {
|
||||
lab=#net1}
|
||||
N 650 -420 650 -400 {
|
||||
lab=#net1}
|
||||
N 840 -320 860 -320 {
|
||||
lab=#net1}
|
||||
C {lab_pin.sym} 120 -230 0 0 {name=p3 sig_type=std_logic lab=NET_A}
|
||||
C {iopin.sym} 80 -140 0 1 { name=p4 lab=NET_A }
|
||||
C {title.sym} 160 -30 0 0 {name=l1
|
||||
author="tcleval([
|
||||
if \{$show_pin_net_names == 0\} \{
|
||||
set IGNORE 1
|
||||
set show_pin_net_names 1
|
||||
xschem update_all_sym_bboxes
|
||||
\}
|
||||
return \{Stefan Schippers\}
|
||||
])"
|
||||
}
|
||||
C {short.sym} 320 -330 0 0 {name=x2
|
||||
spice_ignore="tcleval([if \{$IGNORE == 1\} \{return \{false\}\} else \{return \{true\}\}])"
|
||||
}
|
||||
C {lab_pin.sym} 650 -230 0 1 {name=p5 sig_type=std_logic lab=NET_B}
|
||||
C {lab_show.sym} 470 -330 0 1 {name=l2 }
|
||||
C {lab_pin.sym} 120 -420 0 0 {name=p1 sig_type=std_logic lab=NET_C}
|
||||
C {short.sym} 320 -520 0 0 {name=x5
|
||||
spice_ignore="tcleval([if \{$IGNORE == 1\} \{return \{true\}\} else \{return \{false\}\}])"
|
||||
}
|
||||
C {lab_show.sym} 470 -520 0 1 {name=l3 }
|
||||
C {iopin.sym} 80 -110 0 1 { name=p7 lab=NET_C }
|
||||
C {lab_show.sym} 650 -420 0 1 {name=l5 }
|
||||
C {iv.sym} 560 -420 0 0 {name=x3 delay="70 ps" del=70}
|
||||
C {iv.sym} 560 -230 0 0 {name=x6 delay="70 ps" del=70}
|
||||
C {iv.sym} 330 -420 0 0 {name=x7 delay="70 ps" del=70
|
||||
spice_ignore="tcleval([if \{$IGNORE == 1\} \{return \{false\}\} else \{return \{true\}\}])"
|
||||
}
|
||||
C {iv.sym} 330 -230 0 0 {name=x8 delay="70 ps" del=70
|
||||
spice_ignore="tcleval([if \{$IGNORE == 1\} \{return \{true\}\} else \{return \{false\}\}])"
|
||||
}
|
||||
C {nd2.sym} 780 -320 0 0 {name=a1 del=120
|
||||
spice_ignore="tcleval([if \{$IGNORE == 1\} \{return \{false\}\} else \{return \{true\}\}])"
|
||||
}
|
||||
C {short.sym} 780 -400 0 0 {name=x1
|
||||
spice_ignore="tcleval([if \{$IGNORE == 1\} \{return \{true\}\} else \{return \{false\}\}])"
|
||||
}
|
||||
C {lab_show.sym} 900 -320 0 1 {name=l4 }
|
||||
C {launcher.sym} 750 -90 0 0 {name=h1
|
||||
descr="Toggle IGNORE variable and
|
||||
rebuild connectivity"
|
||||
tclcommand="
|
||||
if \{![info exists IGNORE]\} \{
|
||||
set IGNORE 1
|
||||
\} else \{
|
||||
set IGNORE [expr \{!$IGNORE\}]
|
||||
\}
|
||||
xschem rebuild_connectivity
|
||||
xschem unhilight_all
|
||||
"}
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
v {xschem version=3.4.0 file_version=1.2}
|
||||
K {type=subcircuit
|
||||
format="@name @pinlist @symname"
|
||||
template="name=x1"
|
||||
}
|
||||
T {@symname} -94.5 -6 0 0 0.3 0.3 {}
|
||||
T {@name} 135 -22 0 0 0.2 0.2 {}
|
||||
L 4 -130 -10 130 -10 {}
|
||||
L 4 -130 10 130 10 {}
|
||||
L 4 -130 -10 -130 10 {}
|
||||
L 4 130 -10 130 10 {}
|
||||
Loading…
Reference in New Issue