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update test schematic with new dataset node plotting functions

This commit is contained in:
stefan schippers 2023-10-14 00:19:38 +02:00
parent 8ceb4b6b41
commit 63bc486391
4 changed files with 290 additions and 1600 deletions
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9
xschem_library/examples/LCC_instances.sch
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@ -1,4 +1,4 @@
v {xschem version=3.4.4 file_version=1.2
v {xschem version=3.4.5 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@ -51,10 +51,11 @@ x2=3
divx=6
node="a
zz
zz%1
zzz"
color="4 6 8"
color="8 6 12 7"
sweep="v(a)"
dataset=-1}
dataset=0}
B 2 10 -950 570 -720 {flags=graph
y1 = 0
y2 = 3
@ -66,7 +67,7 @@ node="z
a"
color="4 6"
sweep="v(a) v(z)"
dataset=-1}
}
P 4 5 560 -700 560 -510 1350 -510 1350 -700 560 -700 {dash=3}
P 4 5 820 -920 820 -730 1350 -730 1350 -920 820 -920 {dash=3}
P 4 5 0 -1160 1840 -1160 1840 0 -0 0 0 -1160 {dash=4}

1441
xschem_library/examples/cmos_example.sch
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File diff suppressed because it is too large Load Diff

62
xschem_library/examples/test_ac.sch
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File diff suppressed because one or more lines are too long

378
xschem_library/ngspice/autozero_comp.sch
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@ -24,9 +24,9 @@ K {}
V {}
S {}
E {}
L 3 250 -310 250 -120 {}
L 3 410 -310 410 -170 {}
L 3 570 -310 570 -120 {}
L 3 250 -270 250 -120 {}
L 3 410 -270 410 -170 {}
L 3 570 -270 570 -120 {}
L 4 150 -100 250 -100 {}
L 4 250 -120 250 -100 {}
L 4 250 -120 570 -120 {}
@ -42,8 +42,8 @@ B 2 350 -1020 810 -860 {flags=graph
y1 = 0
y2 = 0.93
divy = 5
x1=9.31247e-08
x2=4.30871e-07
x1=1.02182e-07
x2=4.39927e-07
divx=5
subdivx=4
unitx=n
@ -55,27 +55,29 @@ color="8 14 7 12"
linewidth_mult=1.0
hilight_wave=-1
dataset=-1}
dataset=70}
B 2 350 -1160 810 -1030 {flags=graph
y1 = 0.647319
y2 = 0.652563
divy = 5
x1=9.31247e-08
x2=4.30871e-07
x1=1.02182e-07
x2=4.39927e-07
unitx=n
divx=5
subdivx=4
node="plus%0
minus%0"
subdivx=2
node="plus
minus"
color="4 5"
dataset=-1
linewidth_mult=1.0}
dataset=70
linewidth_mult=1.0
divy=3
subdivy=1}
B 2 350 -1320 810 -1160 {flags=graph
y1 = 0
y2 = 0.9
divy = 5
x1=9.31247e-08
x2=4.30871e-07
x1=1.02182e-07
x2=4.39927e-07
unitx=n
divx=5
subdivx=4
@ -87,7 +89,7 @@ cal
--failure--
\\"SAOUT#70; vss,saout%70\\""
color="4 4 4 8 8 7 7"
dataset=-1
dataset=70
digital=1
ypos1=0.0825406
ypos2=0.767045
@ -98,14 +100,14 @@ B 2 350 -1450 810 -1330 {flags=graph
y1 = -8.54414e-05
y2 = 2.7198e-05
divy = 5
x1=9.31247e-08
x2=4.30871e-07
x1=1.02182e-07
x2=4.39927e-07
divx=5
subdivx=4
unitx=n
dataset=-1
dataset=70
color="4 7"
node="\\"power dset 97 ; i(vvcc) vcc * % 23\\"
\\"power dset 70 ; i(vvcc) vcc * % 70\\""
@ -114,11 +116,11 @@ linewidth_mult=1.0}
T {CAL} 140 -180 0 1 0.4 0.4 {}
T {EN} 140 -130 0 1 0.4 0.4 {}
T {CALIBRATION
30ns} 400 -300 0 1 0.4 0.4 {}
30ns} 400 -260 0 1 0.4 0.4 {}
T {SENSING
30ns} 530 -300 0 1 0.4 0.4 {}
T {OFF} 660 -300 0 1 0.4 0.4 {}
T {OFF} 210 -300 0 1 0.4 0.4 {}
30ns} 530 -260 0 1 0.4 0.4 {}
T {OFF} 660 -260 0 1 0.4 0.4 {}
T {OFF} 210 -260 0 1 0.4 0.4 {}
T {NGSPICE MISMATCH SIMULATION} 1210 -310 0 0 0.8 0.8 {}
T {Offset-compensated comparator. Detects +/- 2mv differential signal on PLUS, MINUS.
Output on SAOUT
@ -129,143 +131,143 @@ N 120 -470 120 -450 {lab=TEMPERAT}
N 360 -530 390 -530 {lab=VSS}
N 360 -500 360 -480 {lab=VSS}
N 360 -580 360 -560 {lab=VSSI}
N 1200 -1070 1230 -1070 {lab=VSS}
N 1200 -1230 1230 -1230 {lab=VCC}
N 1170 -1300 1200 -1300 {lab=VCC}
N 1200 -1300 1200 -1260 {lab=VCC}
N 1170 -940 1200 -940 {lab=VSSI}
N 1200 -980 1200 -940 {lab=VSSI}
N 1060 -1070 1160 -1070 {lab=ZERO0}
N 1060 -1160 1060 -1070 {lab=ZERO0}
N 980 -1160 1060 -1160 {lab=ZERO0}
N 870 -1160 900 -1160 {lab=#net1}
N 870 -1340 870 -1160 {lab=#net1}
N 870 -1340 1300 -1340 {lab=#net1}
N 1200 -1160 1300 -1160 {lab=#net1}
N 1690 -1070 1720 -1070 {lab=VSS}
N 1690 -1230 1720 -1230 {lab=VCC}
N 1660 -1300 1690 -1300 {lab=VCC}
N 1690 -1300 1690 -1260 {lab=VCC}
N 1660 -940 1690 -940 {lab=VSSI}
N 1690 -980 1690 -940 {lab=VSSI}
N 1550 -1070 1650 -1070 {lab=ZERO1}
N 1550 -1160 1550 -1070 {lab=ZERO1}
N 1470 -1160 1550 -1160 {lab=ZERO1}
N 1360 -1160 1390 -1160 {lab=#net2}
N 1360 -1340 1360 -1160 {lab=#net2}
N 1360 -1340 1790 -1340 {lab=#net2}
N 1690 -1160 1790 -1160 {lab=#net2}
N 1300 -1340 1300 -1160 {lab=#net1}
N 1200 -1200 1200 -1160 {lab=#net1}
N 1060 -1230 1060 -1160 {lab=ZERO0}
N 1690 -1200 1690 -1160 {lab=#net2}
N 1550 -1230 1550 -1160 {lab=ZERO1}
N 1790 -1340 1790 -1160 {lab=#net2}
N 1200 -1160 1230 -1160 {lab=VSS}
N 1200 -1320 1230 -1320 {lab=VCC}
N 1170 -1390 1200 -1390 {lab=VCC}
N 1200 -1390 1200 -1350 {lab=VCC}
N 1170 -1030 1200 -1030 {lab=VSSI}
N 1200 -1070 1200 -1030 {lab=VSSI}
N 1060 -1160 1160 -1160 {lab=ZERO0}
N 1060 -1250 1060 -1160 {lab=ZERO0}
N 980 -1250 1060 -1250 {lab=ZERO0}
N 870 -1250 900 -1250 {lab=#net1}
N 870 -1430 870 -1250 {lab=#net1}
N 870 -1430 1300 -1430 {lab=#net1}
N 1200 -1250 1300 -1250 {lab=#net1}
N 1690 -1160 1720 -1160 {lab=VSS}
N 1690 -1320 1720 -1320 {lab=VCC}
N 1660 -1390 1690 -1390 {lab=VCC}
N 1690 -1390 1690 -1350 {lab=VCC}
N 1660 -1030 1690 -1030 {lab=VSSI}
N 1690 -1070 1690 -1030 {lab=VSSI}
N 1550 -1160 1650 -1160 {lab=ZERO1}
N 1550 -1250 1550 -1160 {lab=ZERO1}
N 1470 -1250 1550 -1250 {lab=ZERO1}
N 1360 -1250 1390 -1250 {lab=#net2}
N 1360 -1430 1360 -1250 {lab=#net2}
N 1360 -1430 1790 -1430 {lab=#net2}
N 1690 -1250 1790 -1250 {lab=#net2}
N 1300 -1430 1300 -1250 {lab=#net1}
N 1200 -1290 1200 -1250 {lab=#net1}
N 1060 -1320 1060 -1250 {lab=ZERO0}
N 1690 -1290 1690 -1250 {lab=#net2}
N 1550 -1320 1550 -1250 {lab=ZERO1}
N 1790 -1430 1790 -1250 {lab=#net2}
N 970 -640 1000 -640 {lab=VSS}
N 1140 -640 1170 -640 {lab=VSS}
N 1170 -800 1200 -800 {lab=VCC}
N 940 -800 970 -800 {lab=VCC}
N 1010 -800 1130 -800 {lab=GN}
N 1010 -800 1010 -770 {lab=GN}
N 970 -770 1010 -770 {lab=GN}
N 970 -770 970 -670 {lab=GN}
N 1170 -870 1200 -870 {lab=VCC}
N 940 -870 970 -870 {lab=VCC}
N 1030 -870 1130 -870 {lab=GN}
N 1030 -870 1030 -820 {lab=GN}
N 970 -820 1030 -820 {lab=GN}
N 970 -740 970 -670 {lab=#net3}
N 1170 -710 1170 -670 {lab=OUTDIFF}
N 970 -860 970 -830 {lab=VCC}
N 1070 -860 1170 -860 {lab=VCC}
N 1170 -860 1170 -830 {lab=VCC}
N 970 -930 970 -900 {lab=VCC}
N 1070 -930 1170 -930 {lab=VCC}
N 1170 -930 1170 -900 {lab=VCC}
N 1170 -610 1170 -590 {lab=SN}
N 1070 -590 1170 -590 {lab=SN}
N 970 -610 970 -590 {lab=SN}
N 1070 -510 1100 -510 {lab=VSS}
N 1070 -590 1070 -540 {lab=SN}
N 1070 -880 1070 -860 {lab=VCC}
N 1070 -950 1070 -930 {lab=VCC}
N 1040 -380 1070 -380 {lab=VSSI}
N 1070 -420 1070 -380 {lab=VSSI}
N 1550 -510 1580 -510 {lab=VSS}
N 1550 -800 1580 -800 {lab=VCC}
N 1520 -870 1550 -870 {lab=VCC}
N 1550 -870 1550 -830 {lab=VCC}
N 1550 -870 1580 -870 {lab=VCC}
N 1520 -940 1550 -940 {lab=VCC}
N 1550 -940 1550 -900 {lab=VCC}
N 1520 -380 1550 -380 {lab=VSSI}
N 1550 -420 1550 -380 {lab=VSSI}
N 1550 -710 1550 -540 {lab=SAOUTF}
N 1300 -710 1440 -710 {lab=OUTDIFF}
N 970 -860 1070 -860 {lab=VCC}
N 970 -930 1070 -930 {lab=VCC}
N 970 -590 1070 -590 {lab=SN}
N 1200 -1160 1200 -1100 {lab=#net1}
N 1690 -1160 1690 -1100 {lab=#net2}
N 1200 -1250 1200 -1190 {lab=#net1}
N 1690 -1250 1690 -1190 {lab=#net2}
N 1440 -710 1440 -510 {lab=OUTDIFF}
N 1300 -840 1300 -710 {lab=OUTDIFF}
N 1790 -840 1790 -710 {lab=SAOUTF}
N 1790 -710 1930 -710 {lab=SAOUTF}
N 1170 -710 1300 -710 {lab=OUTDIFF}
N 1170 -770 1170 -710 {lab=OUTDIFF}
N 1440 -800 1440 -710 {lab=OUTDIFF}
N 1550 -1230 1650 -1230 {lab=ZERO1}
N 1060 -1230 1160 -1230 {lab=ZERO0}
N 1440 -800 1510 -800 {lab=OUTDIFF}
N 1170 -740 1170 -710 {lab=OUTDIFF}
N 1440 -870 1440 -710 {lab=OUTDIFF}
N 1550 -1320 1650 -1320 {lab=ZERO1}
N 1060 -1320 1160 -1320 {lab=ZERO0}
N 1440 -870 1510 -870 {lab=OUTDIFF}
N 1440 -510 1510 -510 {lab=OUTDIFF}
N 2040 -510 2070 -510 {lab=VSS}
N 2040 -800 2070 -800 {lab=VCC}
N 2010 -870 2040 -870 {lab=VCC}
N 2040 -870 2040 -830 {lab=VCC}
N 2040 -870 2070 -870 {lab=VCC}
N 2010 -940 2040 -940 {lab=VCC}
N 2040 -940 2040 -900 {lab=VCC}
N 2010 -380 2040 -380 {lab=VSSI}
N 2040 -420 2040 -380 {lab=VSSI}
N 2040 -710 2040 -540 {lab=SAOUT}
N 1930 -710 1930 -510 {lab=SAOUTF}
N 2180 -1070 2210 -1070 {lab=VSS}
N 2180 -1230 2210 -1230 {lab=VCC}
N 2150 -1300 2180 -1300 {lab=VCC}
N 2180 -1300 2180 -1260 {lab=VCC}
N 2150 -940 2180 -940 {lab=VSSI}
N 2180 -980 2180 -940 {lab=VSSI}
N 2040 -1070 2140 -1070 {lab=ZERO2}
N 2040 -1160 2040 -1070 {lab=ZERO2}
N 1960 -1160 2040 -1160 {lab=ZERO2}
N 1850 -1160 1880 -1160 {lab=#net3}
N 1850 -1340 1850 -1160 {lab=#net3}
N 1850 -1340 2370 -1340 {lab=#net3}
N 2180 -1160 2370 -1160 {lab=#net3}
N 2180 -1200 2180 -1160 {lab=#net3}
N 2040 -1230 2040 -1160 {lab=ZERO2}
N 2370 -1340 2370 -1160 {lab=#net3}
N 2180 -1160 2180 -1100 {lab=#net3}
N 2180 -1160 2210 -1160 {lab=VSS}
N 2180 -1320 2210 -1320 {lab=VCC}
N 2150 -1390 2180 -1390 {lab=VCC}
N 2180 -1390 2180 -1350 {lab=VCC}
N 2150 -1030 2180 -1030 {lab=VSSI}
N 2180 -1070 2180 -1030 {lab=VSSI}
N 2040 -1160 2140 -1160 {lab=ZERO2}
N 2040 -1250 2040 -1160 {lab=ZERO2}
N 1960 -1250 2040 -1250 {lab=ZERO2}
N 1850 -1250 1880 -1250 {lab=#net4}
N 1850 -1430 1850 -1250 {lab=#net4}
N 1850 -1430 2370 -1430 {lab=#net4}
N 2180 -1250 2370 -1250 {lab=#net4}
N 2180 -1290 2180 -1250 {lab=#net4}
N 2040 -1320 2040 -1250 {lab=ZERO2}
N 2370 -1430 2370 -1250 {lab=#net4}
N 2180 -1250 2180 -1190 {lab=#net4}
N 2370 -840 2370 -710 {lab=SAOUT}
N 2040 -1230 2140 -1230 {lab=ZERO2}
N 1930 -800 2000 -800 {lab=SAOUTF}
N 2040 -1320 2140 -1320 {lab=ZERO2}
N 1930 -870 2000 -870 {lab=SAOUTF}
N 1930 -510 2000 -510 {lab=SAOUTF}
N 1550 -710 1790 -710 {lab=SAOUTF}
N 2040 -710 2370 -710 {lab=SAOUT}
N 1930 -800 1930 -710 {lab=SAOUTF}
N 2040 -770 2040 -710 {lab=SAOUT}
N 1550 -770 1550 -710 {lab=SAOUTF}
N 2260 -710 2370 -710 {lab=SAOUT}
N 1930 -870 1930 -710 {lab=SAOUTF}
N 2040 -840 2040 -710 {lab=SAOUT}
N 1550 -840 1550 -710 {lab=SAOUTF}
N 2260 -810 2290 -810 {lab=VCC}
N 2230 -880 2260 -880 {lab=VCC}
N 2260 -880 2260 -840 {lab=VCC}
N 2260 -780 2260 -710 {lab=SAOUT}
N 720 -590 750 -590 {lab=VCC}
N 550 -650 550 -620 {lab=SP}
N 650 -650 750 -650 {lab=SP}
N 660 -650 750 -650 {lab=SP}
N 750 -650 750 -620 {lab=SP}
N 550 -650 650 -650 {lab=SP}
N 550 -650 660 -650 {lab=SP}
N 550 -590 580 -590 {lab=VCC}
N 520 -460 550 -460 {lab=VSS}
N 750 -460 780 -460 {lab=VSS}
N 590 -460 710 -460 {lab=GP}
N 590 -510 590 -460 {lab=GP}
N 550 -510 590 -510 {lab=GP}
N 550 -560 550 -510 {lab=GP}
N 750 -560 750 -490 {lab=OUTDIFF}
N 750 -430 750 -410 {lab=VSSI}
N 550 -410 750 -410 {lab=VSSI}
N 550 -430 550 -410 {lab=VSSI}
N 620 -370 650 -370 {lab=VSSI}
N 650 -410 650 -370 {lab=VSSI}
N 520 -410 550 -410 {lab=VSS}
N 750 -410 780 -410 {lab=VSS}
N 590 -410 710 -410 {lab=GP}
N 590 -460 590 -410 {lab=GP}
N 550 -460 590 -460 {lab=GP}
N 550 -490 550 -460 {lab=GP}
N 750 -470 750 -440 {lab=OUTDIFF}
N 750 -380 750 -360 {lab=VSSI}
N 650 -360 750 -360 {lab=VSSI}
N 550 -380 550 -360 {lab=VSSI}
N 620 -320 650 -320 {lab=VSSI}
N 650 -360 650 -320 {lab=VSSI}
N 660 -780 690 -780 {lab=VCC}
N 660 -680 660 -650 {lab=SP}
N 660 -830 660 -810 {lab=VCC}
N 750 -520 810 -520 {lab=OUTDIFF}
N 660 -750 660 -740 {lab=#net4}
N 550 -510 550 -490 {
N 750 -470 810 -470 {lab=OUTDIFF}
N 660 -750 660 -740 {lab=#net5}
N 550 -460 550 -440 {
lab=GP}
N 490 -590 510 -590 {
lab=MINUS}
@ -275,13 +277,24 @@ N 910 -640 930 -640 {
lab=MINUS}
N 1210 -640 1230 -640 {
lab=PLUS}
N 1300 -1160 1300 -900 {lab=#net1}
N 1790 -1160 1790 -900 {lab=#net2}
N 2370 -1160 2370 -900 {lab=#net3}
N 1300 -1250 1300 -900 {lab=#net1}
N 1790 -1250 1790 -900 {lab=#net2}
N 2370 -1250 2370 -900 {lab=#net4}
N 570 -780 620 -780 {
lab=GP}
N 990 -510 1030 -510 {
lab=GN}
N 2040 -710 2260 -710 {lab=SAOUT}
N 550 -360 650 -360 {lab=VSSI}
N 750 -490 750 -470 {lab=OUTDIFF}
N 970 -820 970 -800 {lab=GN}
N 1170 -840 1170 -800 {lab=#net6}
N 550 -560 550 -550 {lab=#net7}
N 750 -560 750 -550 {lab=#net8}
N 1010 -870 1030 -870 {
lab=GN}
N 970 -840 970 -820 {
lab=GN}
C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
C {ipin.sym} 110 -850 0 0 { name=p92 lab=CAL }
C {ipin.sym} 110 -910 0 0 { name=p93 lab=PLUS }
@ -352,56 +365,56 @@ C {lab_pin.sym} 360 -480 0 0 {name=p284 lab=VSS}
C {lab_pin.sym} 360 -580 0 0 {name=p199 lab=VSSI}
C {nmos4-v.sym} 340 -530 0 0 {name=M67 verilog_gate=nmos del=50,50,50 model=nmos w=5u l=0.13u extra="delvto='agauss(0,ABSVAR,3)'"}
C {parax_cap.sym} 360 -470 0 0 {name=c38 value=2p}
C {passgate.sym} 940 -1160 0 1 {name=x1 m=1
C {passgate.sym} 940 -1250 0 1 {name=x1 m=1
+ wn=0.4u ln=0.13u
+ wp=0.4u lp=0.13u
+ VCCBPIN=VCC VSSBPIN=VSS extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 940 -1190 0 1 {name=l19 sig_type=std_logic lab=CALB}
C {lab_pin.sym} 940 -1130 0 1 {name=l44 sig_type=std_logic lab=CALBB}
C {nmos4-v.sym} 1180 -1070 0 0 {name=M3 verilog_gate=nmos del=50,50,50 model=nmos w=1.0u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1230 -1070 0 1 {name=p179 lab=VSS}
C {pmos4-v.sym} 1180 -1230 0 0 {name=M4 verilog_gate=pmos del=50,50,50 model=pmos w=2.0u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1230 -1230 0 1 {name=p180 lab=VCC}
C {lab_pin.sym} 1170 -1300 0 0 {name=p181 lab=VCC}
C {lab_pin.sym} 1170 -940 0 0 {name=p182 lab=VSSI}
C {passgate.sym} 1430 -1160 0 1 {name=x2 m=1
C {lab_pin.sym} 940 -1280 0 1 {name=l19 sig_type=std_logic lab=CALB}
C {lab_pin.sym} 940 -1220 0 1 {name=l44 sig_type=std_logic lab=CALBB}
C {nmos4-v.sym} 1180 -1160 0 0 {name=M3 verilog_gate=nmos del=50,50,50 model=nmos w=1.0u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1230 -1160 0 1 {name=p179 lab=VSS}
C {pmos4-v.sym} 1180 -1320 0 0 {name=M4 verilog_gate=pmos del=50,50,50 model=pmos w=2.0u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1230 -1320 0 1 {name=p180 lab=VCC}
C {lab_pin.sym} 1170 -1390 0 0 {name=p181 lab=VCC}
C {lab_pin.sym} 1170 -1030 0 0 {name=p182 lab=VSSI}
C {passgate.sym} 1430 -1250 0 1 {name=x2 m=1
+ wn=0.4u ln=0.13u
+ wp=0.4u lp=0.13u
+ VCCBPIN=VCC VSSBPIN=VSS extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1430 -1190 0 1 {name=l45 sig_type=std_logic lab=CALB}
C {lab_pin.sym} 1430 -1130 0 1 {name=l46 sig_type=std_logic lab=CALBB}
C {nmos4-v.sym} 1670 -1070 0 0 {name=M7 verilog_gate=nmos del=50,50,50 model=nmos w=1.3u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1720 -1070 0 1 {name=p183 lab=VSS}
C {pmos4-v.sym} 1670 -1230 0 0 {name=M9 verilog_gate=pmos del=50,50,50 model=pmos w=2.6u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1720 -1230 0 1 {name=p184 lab=VCC}
C {lab_pin.sym} 1660 -1300 0 0 {name=p185 lab=VCC}
C {lab_pin.sym} 1660 -940 0 0 {name=p186 lab=VSSI}
C {lab_pin.sym} 1550 -1220 0 0 {name=l47 lab=ZERO1}
C {lab_pin.sym} 1060 -1220 0 0 {name=l48 lab=ZERO0}
C {lab_pin.sym} 1430 -1280 0 1 {name=l45 sig_type=std_logic lab=CALB}
C {lab_pin.sym} 1430 -1220 0 1 {name=l46 sig_type=std_logic lab=CALBB}
C {nmos4-v.sym} 1670 -1160 0 0 {name=M7 verilog_gate=nmos del=50,50,50 model=nmos w=1.3u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1720 -1160 0 1 {name=p183 lab=VSS}
C {pmos4-v.sym} 1670 -1320 0 0 {name=M9 verilog_gate=pmos del=50,50,50 model=pmos w=2.6u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1720 -1320 0 1 {name=p184 lab=VCC}
C {lab_pin.sym} 1660 -1390 0 0 {name=p185 lab=VCC}
C {lab_pin.sym} 1660 -1030 0 0 {name=p186 lab=VSSI}
C {lab_pin.sym} 1550 -1310 0 0 {name=l47 lab=ZERO1}
C {lab_pin.sym} 1060 -1310 0 0 {name=l48 lab=ZERO0}
C {nmos4-v.sym} 950 -640 0 0 {name=M20 verilog_gate=nmos del=50,50,50 model=nmos w=2u l=0.4u extra="delvto='agauss(0,ABSVAR,3)'"}
C {nmos4-v.sym} 1190 -640 0 1 {name=M8 verilog_gate=nmos del=50,50,50 model=nmos w=2u l=0.4u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1000 -640 0 1 {name=p187 lab=VSS}
C {lab_pin.sym} 1140 -640 0 0 {name=p188 lab=VSS}
C {pmos4-v.sym} 1150 -800 0 0 {name=M30 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1200 -800 0 1 {name=p189 lab=VCC}
C {pmos4-v.sym} 990 -800 0 1 {name=M12 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 940 -800 0 0 {name=p190 lab=VCC}
C {pmos4-v.sym} 1150 -870 0 0 {name=M30 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1200 -870 0 1 {name=p189 lab=VCC}
C {pmos4-v.sym} 990 -870 0 1 {name=M12 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 940 -870 0 0 {name=p190 lab=VCC}
C {nmos4-v.sym} 1050 -510 0 0 {name=M32 verilog_gate=nmos del=50,50,50 model=nmos w=1u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1100 -510 0 1 {name=p191 lab=VSS}
C {lab_pin.sym} 1070 -880 0 0 {name=p192 lab=VCC}
C {lab_pin.sym} 1070 -950 0 0 {name=p192 lab=VCC}
C {lab_pin.sym} 1040 -380 0 0 {name=p193 lab=VSSI}
C {nmos4-v.sym} 1530 -510 0 0 {name=M17 verilog_gate=nmos del=50,50,50 model=nmos w=1u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1580 -510 0 1 {name=p194 lab=VSS}
C {pmos4-v.sym} 1530 -800 0 0 {name=M13 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1580 -800 0 1 {name=p195 lab=VCC}
C {lab_pin.sym} 1520 -870 0 0 {name=p196 lab=VCC}
C {pmos4-v.sym} 1530 -870 0 0 {name=M13 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1580 -870 0 1 {name=p195 lab=VCC}
C {lab_pin.sym} 1520 -940 0 0 {name=p196 lab=VCC}
C {lab_pin.sym} 1520 -380 0 0 {name=p197 lab=VSSI}
C {lab_pin.sym} 1790 -750 0 0 {name=l49 lab=SAOUTF}
C {parax_cap.sym} 1620 -700 0 0 {name=c3 value=4f}
C {lab_pin.sym} 1300 -750 0 0 {name=l51 lab=OUTDIFF}
C {lab_pin.sym} 1070 -570 0 0 {name=l52 lab=SN}
C {lab_pin.sym} 1010 -770 0 1 {name=l53 lab=GN}
C {parax_cap.sym} 1060 -790 0 0 {name=c5 value=4f}
C {lab_pin.sym} 1030 -820 0 1 {name=l53 lab=GN}
C {parax_cap.sym} 1060 -860 0 0 {name=c5 value=4f}
C {parax_cap.sym} 990 -580 0 0 {name=c30 value=2f}
C {parax_cap.sym} 1260 -700 0 0 {name=c31 value=4f}
C {lab_pin.sym} 990 -510 0 0 {name=p198 lab=GN}
@ -409,31 +422,31 @@ C {lab_pin.sym} 1230 -640 0 1 {name=l54 lab=PLUS}
C {lab_pin.sym} 910 -640 0 0 {name=l55 lab=MINUS}
C {ammeter.sym} 1070 -450 0 0 {name=vdiffn}
C {ammeter.sym} 1550 -450 0 0 {name=v3}
C {ammeter.sym} 1690 -1010 0 0 {name=v4}
C {ammeter.sym} 1200 -1010 0 0 {name=v6}
C {ammeter.sym} 1690 -1100 0 0 {name=v4}
C {ammeter.sym} 1200 -1100 0 0 {name=v6}
C {nmos4-v.sym} 2020 -510 0 0 {name=M19 verilog_gate=nmos del=50,50,50 model=nmos w=1u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 2070 -510 0 1 {name=p9 lab=VSS}
C {pmos4-v.sym} 2020 -800 0 0 {name=M21 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 2070 -800 0 1 {name=p10 lab=VCC}
C {lab_pin.sym} 2010 -870 0 0 {name=p11 lab=VCC}
C {pmos4-v.sym} 2020 -870 0 0 {name=M21 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 2070 -870 0 1 {name=p10 lab=VCC}
C {lab_pin.sym} 2010 -940 0 0 {name=p11 lab=VCC}
C {lab_pin.sym} 2010 -380 0 0 {name=p12 lab=VSSI}
C {parax_cap.sym} 2110 -700 0 0 {name=c1 value=4f}
C {ammeter.sym} 2040 -450 0 0 {name=v1}
C {lab_pin.sym} 2370 -710 0 1 {name=l3 lab=SAOUT}
C {passgate.sym} 1920 -1160 0 1 {name=x3 m=1
C {passgate.sym} 1920 -1250 0 1 {name=x3 m=1
+ wn=0.4u ln=0.13u
+ wp=0.4u lp=0.13u
+ VCCBPIN=VCC VSSBPIN=VSS extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 1920 -1190 0 1 {name=l5 sig_type=std_logic lab=CALB}
C {lab_pin.sym} 1920 -1130 0 1 {name=l6 sig_type=std_logic lab=CALBB}
C {nmos4-v.sym} 2160 -1070 0 0 {name=M23 verilog_gate=nmos del=50,50,50 model=nmos w=1.5u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 2210 -1070 0 1 {name=p13 lab=VSS}
C {pmos4-v.sym} 2160 -1230 0 0 {name=M24 verilog_gate=pmos del=50,50,50 model=pmos w=3u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 2210 -1230 0 1 {name=p14 lab=VCC}
C {lab_pin.sym} 2150 -1300 0 0 {name=p16 lab=VCC}
C {lab_pin.sym} 2150 -940 0 0 {name=p17 lab=VSSI}
C {lab_pin.sym} 2040 -1220 0 0 {name=l8 lab=ZERO2}
C {ammeter.sym} 2180 -1010 0 0 {name=v5}
C {lab_pin.sym} 1920 -1280 0 1 {name=l5 sig_type=std_logic lab=CALB}
C {lab_pin.sym} 1920 -1220 0 1 {name=l6 sig_type=std_logic lab=CALBB}
C {nmos4-v.sym} 2160 -1160 0 0 {name=M23 verilog_gate=nmos del=50,50,50 model=nmos w=1.5u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 2210 -1160 0 1 {name=p13 lab=VSS}
C {pmos4-v.sym} 2160 -1320 0 0 {name=M24 verilog_gate=pmos del=50,50,50 model=pmos w=3u l=1.0u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 2210 -1320 0 1 {name=p14 lab=VCC}
C {lab_pin.sym} 2150 -1390 0 0 {name=p16 lab=VCC}
C {lab_pin.sym} 2150 -1030 0 0 {name=p17 lab=VSSI}
C {lab_pin.sym} 2040 -1310 0 0 {name=l8 lab=ZERO2}
C {ammeter.sym} 2180 -1100 0 0 {name=v5}
C {pmos4-v.sym} 2240 -810 0 0 {name=M6 verilog_gate=pmos del=50,50,50 model=pmos w=0.6u l=0.2u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 2290 -810 0 1 {name=p18 lab=VCC}
C {lab_pin.sym} 2230 -880 0 0 {name=p19 lab=VCC}
@ -442,27 +455,27 @@ C {pmos4-v.sym} 770 -590 0 1 {name=M18 verilog_gate=pmos del=50,50,50 model=pmos
C {lab_pin.sym} 720 -590 0 0 {name=p20 lab=VCC}
C {pmos4-v.sym} 530 -590 0 0 {name=M25 verilog_gate=pmos del=50,50,50 model=pmos w=4u l=0.4u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 580 -590 0 1 {name=p21 lab=VCC}
C {lab_pin.sym} 520 -460 0 0 {name=p22 lab=VSS}
C {lab_pin.sym} 780 -460 0 1 {name=p23 lab=VSS}
C {lab_pin.sym} 620 -370 0 0 {name=p24 lab=VSSI}
C {lab_pin.sym} 520 -410 0 0 {name=p22 lab=VSS}
C {lab_pin.sym} 780 -410 0 1 {name=p23 lab=VSS}
C {lab_pin.sym} 620 -320 0 0 {name=p24 lab=VSSI}
C {pmos4-v.sym} 640 -780 0 0 {name=M28 verilog_gate=pmos del=50,50,50 model=pmos w=2u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {lab_pin.sym} 690 -780 0 1 {name=p25 lab=VCC}
C {lab_pin.sym} 660 -830 0 0 {name=p26 lab=VCC}
C {lab_pin.sym} 570 -780 0 0 {name=l7 lab=GP}
C {lab_pin.sym} 550 -530 0 1 {name=l9 lab=GP}
C {lab_pin.sym} 550 -480 0 1 {name=l9 lab=GP}
C {lab_pin.sym} 490 -590 0 0 {name=l10 lab=MINUS}
C {lab_pin.sym} 810 -590 0 1 {name=l11 lab=PLUS}
C {lab_pin.sym} 810 -520 0 1 {name=l12 lab=OUTDIFF}
C {nmos4-v.sym} 730 -460 0 0 {name=M26 verilog_gate=nmos del=50,50,50 model=nmos w=1u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {nmos4-v.sym} 570 -460 0 1 {name=M1 verilog_gate=nmos del=50,50,50 model=nmos w=1u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {parax_cap.sym} 630 -450 0 0 {name=c2 value=4f}
C {lab_pin.sym} 810 -470 0 1 {name=l12 lab=OUTDIFF}
C {nmos4-v.sym} 730 -410 0 0 {name=M26 verilog_gate=nmos del=50,50,50 model=nmos w=1u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {nmos4-v.sym} 570 -410 0 1 {name=M1 verilog_gate=nmos del=50,50,50 model=nmos w=1u l=0.5u extra="delvto='agauss(0,ABSVAR,3)'"}
C {parax_cap.sym} 630 -400 0 0 {name=c2 value=4f}
C {lab_pin.sym} 660 -670 0 0 {name=l13 lab=SP}
C {launcher.sym} 930 -260 0 0 {name=h2
descr="Simulate"
tclcommand="xschem netlist; xschem simulate"}
C {parax_cap.sym} 1060 -1060 0 0 {name=c4 value=5f}
C {parax_cap.sym} 1550 -1060 0 0 {name=c6 value=5f}
C {parax_cap.sym} 2040 -1060 0 0 {name=c7 value=5f}
C {parax_cap.sym} 1060 -1150 0 0 {name=c4 value=5f}
C {parax_cap.sym} 1550 -1150 0 0 {name=c6 value=5f}
C {parax_cap.sym} 2040 -1150 0 0 {name=c7 value=5f}
C {launcher.sym} 65 -1075 0 0 {name=h1
descr="Select arrow and
Ctrl-Left-Click to
@ -475,4 +488,7 @@ C {ammeter.sym} 660 -710 0 0 {name=vdiffp}
C {ammeter.sym} 1300 -870 0 0 {name=vcalib0}
C {ammeter.sym} 1790 -870 0 0 {name=vcalib1}
C {ammeter.sym} 2370 -870 0 0 {name=vcalib2}
C {test_generators.sym} 480 -500 0 0 {name=x28}
C {ammeter.sym} 970 -770 0 0 {name=vnleft}
C {ammeter.sym} 1170 -770 0 1 {name=vnright}
C {ammeter.sym} 550 -520 0 0 {name=vpleft}
C {ammeter.sym} 750 -520 0 0 {name=vpright}